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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Driver for CPM (SCC/SMC) serial ports; core driver
0004  *
0005  *  Based on arch/ppc/cpm2_io/uart.c by Dan Malek
0006  *  Based on ppc8xx.c by Thomas Gleixner
0007  *  Based on drivers/serial/amba.c by Russell King
0008  *
0009  *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
0010  *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
0011  *
0012  *  Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
0013  *            (C) 2004 Intracom, S.A.
0014  *            (C) 2005-2006 MontaVista Software, Inc.
0015  *      Vitaly Bordug <vbordug@ru.mvista.com>
0016  */
0017 
0018 #include <linux/module.h>
0019 #include <linux/tty.h>
0020 #include <linux/tty_flip.h>
0021 #include <linux/ioport.h>
0022 #include <linux/init.h>
0023 #include <linux/serial.h>
0024 #include <linux/console.h>
0025 #include <linux/sysrq.h>
0026 #include <linux/device.h>
0027 #include <linux/memblock.h>
0028 #include <linux/dma-mapping.h>
0029 #include <linux/fs_uart_pd.h>
0030 #include <linux/of_address.h>
0031 #include <linux/of_irq.h>
0032 #include <linux/of_platform.h>
0033 #include <linux/gpio/consumer.h>
0034 #include <linux/clk.h>
0035 
0036 #include <asm/io.h>
0037 #include <asm/irq.h>
0038 #include <asm/delay.h>
0039 #include <asm/fs_pd.h>
0040 #include <asm/udbg.h>
0041 
0042 #include <linux/serial_core.h>
0043 #include <linux/kernel.h>
0044 
0045 #include "cpm_uart.h"
0046 
0047 
0048 /**************************************************************/
0049 
0050 static int  cpm_uart_tx_pump(struct uart_port *port);
0051 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
0052 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
0053 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
0054 
0055 /**************************************************************/
0056 
0057 #define HW_BUF_SPD_THRESHOLD    2400
0058 
0059 /*
0060  * Check, if transmit buffers are processed
0061 */
0062 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
0063 {
0064     struct uart_cpm_port *pinfo =
0065         container_of(port, struct uart_cpm_port, port);
0066     cbd_t __iomem *bdp = pinfo->tx_bd_base;
0067     int ret = 0;
0068 
0069     while (1) {
0070         if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
0071             break;
0072 
0073         if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
0074             ret = TIOCSER_TEMT;
0075             break;
0076         }
0077         bdp++;
0078     }
0079 
0080     pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
0081 
0082     return ret;
0083 }
0084 
0085 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0086 {
0087     struct uart_cpm_port *pinfo =
0088         container_of(port, struct uart_cpm_port, port);
0089 
0090     if (pinfo->gpios[GPIO_RTS])
0091         gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
0092 
0093     if (pinfo->gpios[GPIO_DTR])
0094         gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
0095 }
0096 
0097 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
0098 {
0099     struct uart_cpm_port *pinfo =
0100         container_of(port, struct uart_cpm_port, port);
0101     unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
0102 
0103     if (pinfo->gpios[GPIO_CTS]) {
0104         if (gpiod_get_value(pinfo->gpios[GPIO_CTS]))
0105             mctrl &= ~TIOCM_CTS;
0106     }
0107 
0108     if (pinfo->gpios[GPIO_DSR]) {
0109         if (gpiod_get_value(pinfo->gpios[GPIO_DSR]))
0110             mctrl &= ~TIOCM_DSR;
0111     }
0112 
0113     if (pinfo->gpios[GPIO_DCD]) {
0114         if (gpiod_get_value(pinfo->gpios[GPIO_DCD]))
0115             mctrl &= ~TIOCM_CAR;
0116     }
0117 
0118     if (pinfo->gpios[GPIO_RI]) {
0119         if (!gpiod_get_value(pinfo->gpios[GPIO_RI]))
0120             mctrl |= TIOCM_RNG;
0121     }
0122 
0123     return mctrl;
0124 }
0125 
0126 /*
0127  * Stop transmitter
0128  */
0129 static void cpm_uart_stop_tx(struct uart_port *port)
0130 {
0131     struct uart_cpm_port *pinfo =
0132         container_of(port, struct uart_cpm_port, port);
0133     smc_t __iomem *smcp = pinfo->smcp;
0134     scc_t __iomem *sccp = pinfo->sccp;
0135 
0136     pr_debug("CPM uart[%d]:stop tx\n", port->line);
0137 
0138     if (IS_SMC(pinfo))
0139         clrbits8(&smcp->smc_smcm, SMCM_TX);
0140     else
0141         clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
0142 }
0143 
0144 /*
0145  * Start transmitter
0146  */
0147 static void cpm_uart_start_tx(struct uart_port *port)
0148 {
0149     struct uart_cpm_port *pinfo =
0150         container_of(port, struct uart_cpm_port, port);
0151     smc_t __iomem *smcp = pinfo->smcp;
0152     scc_t __iomem *sccp = pinfo->sccp;
0153 
0154     pr_debug("CPM uart[%d]:start tx\n", port->line);
0155 
0156     if (IS_SMC(pinfo)) {
0157         if (in_8(&smcp->smc_smcm) & SMCM_TX)
0158             return;
0159     } else {
0160         if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
0161             return;
0162     }
0163 
0164     if (cpm_uart_tx_pump(port) != 0) {
0165         if (IS_SMC(pinfo)) {
0166             setbits8(&smcp->smc_smcm, SMCM_TX);
0167         } else {
0168             setbits16(&sccp->scc_sccm, UART_SCCM_TX);
0169         }
0170     }
0171 }
0172 
0173 /*
0174  * Stop receiver
0175  */
0176 static void cpm_uart_stop_rx(struct uart_port *port)
0177 {
0178     struct uart_cpm_port *pinfo =
0179         container_of(port, struct uart_cpm_port, port);
0180     smc_t __iomem *smcp = pinfo->smcp;
0181     scc_t __iomem *sccp = pinfo->sccp;
0182 
0183     pr_debug("CPM uart[%d]:stop rx\n", port->line);
0184 
0185     if (IS_SMC(pinfo))
0186         clrbits8(&smcp->smc_smcm, SMCM_RX);
0187     else
0188         clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
0189 }
0190 
0191 /*
0192  * Generate a break.
0193  */
0194 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
0195 {
0196     struct uart_cpm_port *pinfo =
0197         container_of(port, struct uart_cpm_port, port);
0198 
0199     pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
0200         break_state);
0201 
0202     if (break_state)
0203         cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
0204     else
0205         cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
0206 }
0207 
0208 /*
0209  * Transmit characters, refill buffer descriptor, if possible
0210  */
0211 static void cpm_uart_int_tx(struct uart_port *port)
0212 {
0213     pr_debug("CPM uart[%d]:TX INT\n", port->line);
0214 
0215     cpm_uart_tx_pump(port);
0216 }
0217 
0218 #ifdef CONFIG_CONSOLE_POLL
0219 static int serial_polled;
0220 #endif
0221 
0222 /*
0223  * Receive characters
0224  */
0225 static void cpm_uart_int_rx(struct uart_port *port)
0226 {
0227     int i;
0228     unsigned char ch;
0229     u8 *cp;
0230     struct tty_port *tport = &port->state->port;
0231     struct uart_cpm_port *pinfo =
0232         container_of(port, struct uart_cpm_port, port);
0233     cbd_t __iomem *bdp;
0234     u16 status;
0235     unsigned int flg;
0236 
0237     pr_debug("CPM uart[%d]:RX INT\n", port->line);
0238 
0239     /* Just loop through the closed BDs and copy the characters into
0240      * the buffer.
0241      */
0242     bdp = pinfo->rx_cur;
0243     for (;;) {
0244 #ifdef CONFIG_CONSOLE_POLL
0245         if (unlikely(serial_polled)) {
0246             serial_polled = 0;
0247             return;
0248         }
0249 #endif
0250         /* get status */
0251         status = in_be16(&bdp->cbd_sc);
0252         /* If this one is empty, return happy */
0253         if (status & BD_SC_EMPTY)
0254             break;
0255 
0256         /* get number of characters, and check spce in flip-buffer */
0257         i = in_be16(&bdp->cbd_datlen);
0258 
0259         /* If we have not enough room in tty flip buffer, then we try
0260          * later, which will be the next rx-interrupt or a timeout
0261          */
0262         if (tty_buffer_request_room(tport, i) < i) {
0263             printk(KERN_WARNING "No room in flip buffer\n");
0264             return;
0265         }
0266 
0267         /* get pointer */
0268         cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
0269 
0270         /* loop through the buffer */
0271         while (i-- > 0) {
0272             ch = *cp++;
0273             port->icount.rx++;
0274             flg = TTY_NORMAL;
0275 
0276             if (status &
0277                 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
0278                 goto handle_error;
0279             if (uart_handle_sysrq_char(port, ch))
0280                 continue;
0281 #ifdef CONFIG_CONSOLE_POLL
0282             if (unlikely(serial_polled)) {
0283                 serial_polled = 0;
0284                 return;
0285             }
0286 #endif
0287               error_return:
0288             tty_insert_flip_char(tport, ch, flg);
0289 
0290         }       /* End while (i--) */
0291 
0292         /* This BD is ready to be used again. Clear status. get next */
0293         clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
0294                                 BD_SC_OV | BD_SC_ID);
0295         setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
0296 
0297         if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
0298             bdp = pinfo->rx_bd_base;
0299         else
0300             bdp++;
0301 
0302     } /* End for (;;) */
0303 
0304     /* Write back buffer pointer */
0305     pinfo->rx_cur = bdp;
0306 
0307     /* activate BH processing */
0308     tty_flip_buffer_push(tport);
0309 
0310     return;
0311 
0312     /* Error processing */
0313 
0314       handle_error:
0315     /* Statistics */
0316     if (status & BD_SC_BR)
0317         port->icount.brk++;
0318     if (status & BD_SC_PR)
0319         port->icount.parity++;
0320     if (status & BD_SC_FR)
0321         port->icount.frame++;
0322     if (status & BD_SC_OV)
0323         port->icount.overrun++;
0324 
0325     /* Mask out ignored conditions */
0326     status &= port->read_status_mask;
0327 
0328     /* Handle the remaining ones */
0329     if (status & BD_SC_BR)
0330         flg = TTY_BREAK;
0331     else if (status & BD_SC_PR)
0332         flg = TTY_PARITY;
0333     else if (status & BD_SC_FR)
0334         flg = TTY_FRAME;
0335 
0336     /* overrun does not affect the current character ! */
0337     if (status & BD_SC_OV) {
0338         ch = 0;
0339         flg = TTY_OVERRUN;
0340         /* We skip this buffer */
0341         /* CHECK: Is really nothing senseful there */
0342         /* ASSUMPTION: it contains nothing valid */
0343         i = 0;
0344     }
0345     port->sysrq = 0;
0346     goto error_return;
0347 }
0348 
0349 /*
0350  * Asynchron mode interrupt handler
0351  */
0352 static irqreturn_t cpm_uart_int(int irq, void *data)
0353 {
0354     u8 events;
0355     struct uart_port *port = data;
0356     struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
0357     smc_t __iomem *smcp = pinfo->smcp;
0358     scc_t __iomem *sccp = pinfo->sccp;
0359 
0360     pr_debug("CPM uart[%d]:IRQ\n", port->line);
0361 
0362     if (IS_SMC(pinfo)) {
0363         events = in_8(&smcp->smc_smce);
0364         out_8(&smcp->smc_smce, events);
0365         if (events & SMCM_BRKE)
0366             uart_handle_break(port);
0367         if (events & SMCM_RX)
0368             cpm_uart_int_rx(port);
0369         if (events & SMCM_TX)
0370             cpm_uart_int_tx(port);
0371     } else {
0372         events = in_be16(&sccp->scc_scce);
0373         out_be16(&sccp->scc_scce, events);
0374         if (events & UART_SCCM_BRKE)
0375             uart_handle_break(port);
0376         if (events & UART_SCCM_RX)
0377             cpm_uart_int_rx(port);
0378         if (events & UART_SCCM_TX)
0379             cpm_uart_int_tx(port);
0380     }
0381     return (events) ? IRQ_HANDLED : IRQ_NONE;
0382 }
0383 
0384 static int cpm_uart_startup(struct uart_port *port)
0385 {
0386     int retval;
0387     struct uart_cpm_port *pinfo =
0388         container_of(port, struct uart_cpm_port, port);
0389 
0390     pr_debug("CPM uart[%d]:startup\n", port->line);
0391 
0392     /* If the port is not the console, make sure rx is disabled. */
0393     if (!(pinfo->flags & FLAG_CONSOLE)) {
0394         /* Disable UART rx */
0395         if (IS_SMC(pinfo)) {
0396             clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
0397             clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
0398         } else {
0399             clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
0400             clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
0401         }
0402         cpm_uart_initbd(pinfo);
0403         if (IS_SMC(pinfo)) {
0404             out_be32(&pinfo->smcup->smc_rstate, 0);
0405             out_be32(&pinfo->smcup->smc_tstate, 0);
0406             out_be16(&pinfo->smcup->smc_rbptr,
0407                  in_be16(&pinfo->smcup->smc_rbase));
0408             out_be16(&pinfo->smcup->smc_tbptr,
0409                  in_be16(&pinfo->smcup->smc_tbase));
0410         } else {
0411             cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
0412         }
0413     }
0414     /* Install interrupt handler. */
0415     retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
0416     if (retval)
0417         return retval;
0418 
0419     /* Startup rx-int */
0420     if (IS_SMC(pinfo)) {
0421         setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
0422         setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
0423     } else {
0424         setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
0425         setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
0426     }
0427 
0428     return 0;
0429 }
0430 
0431 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
0432 {
0433     set_current_state(TASK_UNINTERRUPTIBLE);
0434     schedule_timeout(pinfo->wait_closing);
0435 }
0436 
0437 /*
0438  * Shutdown the uart
0439  */
0440 static void cpm_uart_shutdown(struct uart_port *port)
0441 {
0442     struct uart_cpm_port *pinfo =
0443         container_of(port, struct uart_cpm_port, port);
0444 
0445     pr_debug("CPM uart[%d]:shutdown\n", port->line);
0446 
0447     /* free interrupt handler */
0448     free_irq(port->irq, port);
0449 
0450     /* If the port is not the console, disable Rx and Tx. */
0451     if (!(pinfo->flags & FLAG_CONSOLE)) {
0452         /* Wait for all the BDs marked sent */
0453         while(!cpm_uart_tx_empty(port)) {
0454             set_current_state(TASK_UNINTERRUPTIBLE);
0455             schedule_timeout(2);
0456         }
0457 
0458         if (pinfo->wait_closing)
0459             cpm_uart_wait_until_send(pinfo);
0460 
0461         /* Stop uarts */
0462         if (IS_SMC(pinfo)) {
0463             smc_t __iomem *smcp = pinfo->smcp;
0464             clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
0465             clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
0466         } else {
0467             scc_t __iomem *sccp = pinfo->sccp;
0468             clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
0469             clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
0470         }
0471 
0472         /* Shut them really down and reinit buffer descriptors */
0473         if (IS_SMC(pinfo)) {
0474             out_be16(&pinfo->smcup->smc_brkcr, 0);
0475             cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
0476         } else {
0477             out_be16(&pinfo->sccup->scc_brkcr, 0);
0478             cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
0479         }
0480 
0481         cpm_uart_initbd(pinfo);
0482     }
0483 }
0484 
0485 static void cpm_uart_set_termios(struct uart_port *port,
0486                                  struct ktermios *termios,
0487                                  struct ktermios *old)
0488 {
0489     int baud;
0490     unsigned long flags;
0491     u16 cval, scval, prev_mode;
0492     int bits, sbits;
0493     struct uart_cpm_port *pinfo =
0494         container_of(port, struct uart_cpm_port, port);
0495     smc_t __iomem *smcp = pinfo->smcp;
0496     scc_t __iomem *sccp = pinfo->sccp;
0497     int maxidl;
0498 
0499     pr_debug("CPM uart[%d]:set_termios\n", port->line);
0500 
0501     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
0502     if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY)
0503         pinfo->rx_fifosize = 1;
0504     else
0505         pinfo->rx_fifosize = RX_BUF_SIZE;
0506 
0507     /* MAXIDL is the timeout after which a receive buffer is closed
0508      * when not full if no more characters are received.
0509      * We calculate it from the baudrate so that the duration is
0510      * always the same at standard rates: about 4ms.
0511      */
0512     maxidl = baud / 2400;
0513     if (maxidl < 1)
0514         maxidl = 1;
0515     if (maxidl > 0x10)
0516         maxidl = 0x10;
0517 
0518     /* Character length programmed into the mode register is the
0519      * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
0520      * 1 or 2 stop bits, minus 1.
0521      * The value 'bits' counts this for us.
0522      */
0523     cval = 0;
0524     scval = 0;
0525 
0526     /* byte size */
0527     bits = tty_get_char_size(termios->c_cflag);
0528     sbits = bits - 5;
0529 
0530     if (termios->c_cflag & CSTOPB) {
0531         cval |= SMCMR_SL;   /* Two stops */
0532         scval |= SCU_PSMR_SL;
0533         bits++;
0534     }
0535 
0536     if (termios->c_cflag & PARENB) {
0537         cval |= SMCMR_PEN;
0538         scval |= SCU_PSMR_PEN;
0539         bits++;
0540         if (!(termios->c_cflag & PARODD)) {
0541             cval |= SMCMR_PM_EVEN;
0542             scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
0543         }
0544     }
0545 
0546     /*
0547      * Update the timeout
0548      */
0549     uart_update_timeout(port, termios->c_cflag, baud);
0550 
0551     /*
0552      * Set up parity check flag
0553      */
0554     port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
0555     if (termios->c_iflag & INPCK)
0556         port->read_status_mask |= BD_SC_FR | BD_SC_PR;
0557     if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
0558         port->read_status_mask |= BD_SC_BR;
0559 
0560     /*
0561      * Characters to ignore
0562      */
0563     port->ignore_status_mask = 0;
0564     if (termios->c_iflag & IGNPAR)
0565         port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
0566     if (termios->c_iflag & IGNBRK) {
0567         port->ignore_status_mask |= BD_SC_BR;
0568         /*
0569          * If we're ignore parity and break indicators, ignore
0570          * overruns too.  (For real raw support).
0571          */
0572         if (termios->c_iflag & IGNPAR)
0573             port->ignore_status_mask |= BD_SC_OV;
0574     }
0575     /*
0576      * !!! ignore all characters if CREAD is not set
0577      */
0578     if ((termios->c_cflag & CREAD) == 0)
0579         port->read_status_mask &= ~BD_SC_EMPTY;
0580 
0581     spin_lock_irqsave(&port->lock, flags);
0582 
0583     /* Start bit has not been added (so don't, because we would just
0584      * subtract it later), and we need to add one for the number of
0585      * stops bits (there is always at least one).
0586      */
0587     bits++;
0588     if (IS_SMC(pinfo)) {
0589         /*
0590          * MRBLR can be changed while an SMC/SCC is operating only
0591          * if it is done in a single bus cycle with one 16-bit move
0592          * (not two 8-bit bus cycles back-to-back). This occurs when
0593          * the cp shifts control to the next RxBD, so the change does
0594          * not take effect immediately. To guarantee the exact RxBD
0595          * on which the change occurs, change MRBLR only while the
0596          * SMC/SCC receiver is disabled.
0597          */
0598         out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
0599         out_be16(&pinfo->smcup->smc_maxidl, maxidl);
0600 
0601         /* Set the mode register.  We want to keep a copy of the
0602          * enables, because we want to put them back if they were
0603          * present.
0604          */
0605         prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
0606         /* Output in *one* operation, so we don't interrupt RX/TX if they
0607          * were already enabled. */
0608         out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
0609             SMCMR_SM_UART | prev_mode);
0610     } else {
0611         out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
0612         out_be16(&pinfo->sccup->scc_maxidl, maxidl);
0613         out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
0614     }
0615 
0616     if (pinfo->clk)
0617         clk_set_rate(pinfo->clk, baud);
0618     else
0619         cpm_set_brg(pinfo->brg - 1, baud);
0620     spin_unlock_irqrestore(&port->lock, flags);
0621 }
0622 
0623 static const char *cpm_uart_type(struct uart_port *port)
0624 {
0625     pr_debug("CPM uart[%d]:uart_type\n", port->line);
0626 
0627     return port->type == PORT_CPM ? "CPM UART" : NULL;
0628 }
0629 
0630 /*
0631  * verify the new serial_struct (for TIOCSSERIAL).
0632  */
0633 static int cpm_uart_verify_port(struct uart_port *port,
0634                 struct serial_struct *ser)
0635 {
0636     int ret = 0;
0637 
0638     pr_debug("CPM uart[%d]:verify_port\n", port->line);
0639 
0640     if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
0641         ret = -EINVAL;
0642     if (ser->irq < 0 || ser->irq >= nr_irqs)
0643         ret = -EINVAL;
0644     if (ser->baud_base < 9600)
0645         ret = -EINVAL;
0646     return ret;
0647 }
0648 
0649 /*
0650  * Transmit characters, refill buffer descriptor, if possible
0651  */
0652 static int cpm_uart_tx_pump(struct uart_port *port)
0653 {
0654     cbd_t __iomem *bdp;
0655     u8 *p;
0656     int count;
0657     struct uart_cpm_port *pinfo =
0658         container_of(port, struct uart_cpm_port, port);
0659     struct circ_buf *xmit = &port->state->xmit;
0660 
0661     /* Handle xon/xoff */
0662     if (port->x_char) {
0663         /* Pick next descriptor and fill from buffer */
0664         bdp = pinfo->tx_cur;
0665 
0666         p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
0667 
0668         *p++ = port->x_char;
0669 
0670         out_be16(&bdp->cbd_datlen, 1);
0671         setbits16(&bdp->cbd_sc, BD_SC_READY);
0672         /* Get next BD. */
0673         if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
0674             bdp = pinfo->tx_bd_base;
0675         else
0676             bdp++;
0677         pinfo->tx_cur = bdp;
0678 
0679         port->icount.tx++;
0680         port->x_char = 0;
0681         return 1;
0682     }
0683 
0684     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0685         cpm_uart_stop_tx(port);
0686         return 0;
0687     }
0688 
0689     /* Pick next descriptor and fill from buffer */
0690     bdp = pinfo->tx_cur;
0691 
0692     while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
0693            xmit->tail != xmit->head) {
0694         count = 0;
0695         p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
0696         while (count < pinfo->tx_fifosize) {
0697             *p++ = xmit->buf[xmit->tail];
0698             xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0699             port->icount.tx++;
0700             count++;
0701             if (xmit->head == xmit->tail)
0702                 break;
0703         }
0704         out_be16(&bdp->cbd_datlen, count);
0705         setbits16(&bdp->cbd_sc, BD_SC_READY);
0706         /* Get next BD. */
0707         if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
0708             bdp = pinfo->tx_bd_base;
0709         else
0710             bdp++;
0711     }
0712     pinfo->tx_cur = bdp;
0713 
0714     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0715         uart_write_wakeup(port);
0716 
0717     if (uart_circ_empty(xmit)) {
0718         cpm_uart_stop_tx(port);
0719         return 0;
0720     }
0721 
0722     return 1;
0723 }
0724 
0725 /*
0726  * init buffer descriptors
0727  */
0728 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
0729 {
0730     int i;
0731     u8 *mem_addr;
0732     cbd_t __iomem *bdp;
0733 
0734     pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
0735 
0736     /* Set the physical address of the host memory
0737      * buffers in the buffer descriptors, and the
0738      * virtual address for us to work with.
0739      */
0740     mem_addr = pinfo->mem_addr;
0741     bdp = pinfo->rx_cur = pinfo->rx_bd_base;
0742     for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
0743         out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
0744         out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
0745         mem_addr += pinfo->rx_fifosize;
0746     }
0747 
0748     out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
0749     out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
0750 
0751     /* Set the physical address of the host memory
0752      * buffers in the buffer descriptors, and the
0753      * virtual address for us to work with.
0754      */
0755     mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
0756     bdp = pinfo->tx_cur = pinfo->tx_bd_base;
0757     for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
0758         out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
0759         out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
0760         mem_addr += pinfo->tx_fifosize;
0761     }
0762 
0763     out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
0764     out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
0765 }
0766 
0767 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
0768 {
0769     scc_t __iomem *scp;
0770     scc_uart_t __iomem *sup;
0771 
0772     pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
0773 
0774     scp = pinfo->sccp;
0775     sup = pinfo->sccup;
0776 
0777     /* Store address */
0778     out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
0779              (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
0780     out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
0781              (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
0782 
0783     /* Set up the uart parameters in the
0784      * parameter ram.
0785      */
0786 
0787     cpm_set_scc_fcr(sup);
0788 
0789     out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
0790     out_be16(&sup->scc_maxidl, 0x10);
0791     out_be16(&sup->scc_brkcr, 1);
0792     out_be16(&sup->scc_parec, 0);
0793     out_be16(&sup->scc_frmec, 0);
0794     out_be16(&sup->scc_nosec, 0);
0795     out_be16(&sup->scc_brkec, 0);
0796     out_be16(&sup->scc_uaddr1, 0);
0797     out_be16(&sup->scc_uaddr2, 0);
0798     out_be16(&sup->scc_toseq, 0);
0799     out_be16(&sup->scc_char1, 0x8000);
0800     out_be16(&sup->scc_char2, 0x8000);
0801     out_be16(&sup->scc_char3, 0x8000);
0802     out_be16(&sup->scc_char4, 0x8000);
0803     out_be16(&sup->scc_char5, 0x8000);
0804     out_be16(&sup->scc_char6, 0x8000);
0805     out_be16(&sup->scc_char7, 0x8000);
0806     out_be16(&sup->scc_char8, 0x8000);
0807     out_be16(&sup->scc_rccm, 0xc0ff);
0808 
0809     /* Send the CPM an initialize command.
0810      */
0811     cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
0812 
0813     /* Set UART mode, 8 bit, no parity, one stop.
0814      * Enable receive and transmit.
0815      */
0816     out_be32(&scp->scc_gsmrh, 0);
0817     out_be32(&scp->scc_gsmrl,
0818              SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
0819 
0820     /* Enable rx interrupts  and clear all pending events.  */
0821     out_be16(&scp->scc_sccm, 0);
0822     out_be16(&scp->scc_scce, 0xffff);
0823     out_be16(&scp->scc_dsr, 0x7e7e);
0824     out_be16(&scp->scc_psmr, 0x3000);
0825 
0826     setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
0827 }
0828 
0829 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
0830 {
0831     smc_t __iomem *sp;
0832     smc_uart_t __iomem *up;
0833 
0834     pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
0835 
0836     sp = pinfo->smcp;
0837     up = pinfo->smcup;
0838 
0839     /* Store address */
0840     out_be16(&pinfo->smcup->smc_rbase,
0841              (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
0842     out_be16(&pinfo->smcup->smc_tbase,
0843              (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
0844 
0845 /*
0846  *  In case SMC is being relocated...
0847  */
0848     out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
0849     out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
0850     out_be32(&up->smc_rstate, 0);
0851     out_be32(&up->smc_tstate, 0);
0852     out_be16(&up->smc_brkcr, 1);              /* number of break chars */
0853     out_be16(&up->smc_brkec, 0);
0854 
0855     /* Set up the uart parameters in the
0856      * parameter ram.
0857      */
0858     cpm_set_smc_fcr(up);
0859 
0860     /* Using idle character time requires some additional tuning.  */
0861     out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
0862     out_be16(&up->smc_maxidl, 0x10);
0863     out_be16(&up->smc_brklen, 0);
0864     out_be16(&up->smc_brkec, 0);
0865     out_be16(&up->smc_brkcr, 1);
0866 
0867     /* Set UART mode, 8 bit, no parity, one stop.
0868      * Enable receive and transmit.
0869      */
0870     out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
0871 
0872     /* Enable only rx interrupts clear all pending events. */
0873     out_8(&sp->smc_smcm, 0);
0874     out_8(&sp->smc_smce, 0xff);
0875 
0876     setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
0877 }
0878 
0879 /*
0880  * Initialize port. This is called from early_console stuff
0881  * so we have to be careful here !
0882  */
0883 static int cpm_uart_request_port(struct uart_port *port)
0884 {
0885     struct uart_cpm_port *pinfo =
0886         container_of(port, struct uart_cpm_port, port);
0887     int ret;
0888 
0889     pr_debug("CPM uart[%d]:request port\n", port->line);
0890 
0891     if (pinfo->flags & FLAG_CONSOLE)
0892         return 0;
0893 
0894     if (IS_SMC(pinfo)) {
0895         clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
0896         clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
0897     } else {
0898         clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
0899         clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
0900     }
0901 
0902     ret = cpm_uart_allocbuf(pinfo, 0);
0903 
0904     if (ret)
0905         return ret;
0906 
0907     cpm_uart_initbd(pinfo);
0908     if (IS_SMC(pinfo))
0909         cpm_uart_init_smc(pinfo);
0910     else
0911         cpm_uart_init_scc(pinfo);
0912 
0913     return 0;
0914 }
0915 
0916 static void cpm_uart_release_port(struct uart_port *port)
0917 {
0918     struct uart_cpm_port *pinfo =
0919         container_of(port, struct uart_cpm_port, port);
0920 
0921     if (!(pinfo->flags & FLAG_CONSOLE))
0922         cpm_uart_freebuf(pinfo);
0923 }
0924 
0925 /*
0926  * Configure/autoconfigure the port.
0927  */
0928 static void cpm_uart_config_port(struct uart_port *port, int flags)
0929 {
0930     pr_debug("CPM uart[%d]:config_port\n", port->line);
0931 
0932     if (flags & UART_CONFIG_TYPE) {
0933         port->type = PORT_CPM;
0934         cpm_uart_request_port(port);
0935     }
0936 }
0937 
0938 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
0939 /*
0940  * Write a string to the serial port
0941  * Note that this is called with interrupts already disabled
0942  */
0943 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
0944         const char *string, u_int count, bool handle_linefeed)
0945 {
0946     unsigned int i;
0947     cbd_t __iomem *bdp, *bdbase;
0948     unsigned char *cpm_outp_addr;
0949 
0950     /* Get the address of the host memory buffer.
0951      */
0952     bdp = pinfo->tx_cur;
0953     bdbase = pinfo->tx_bd_base;
0954 
0955     /*
0956      * Now, do each character.  This is not as bad as it looks
0957      * since this is a holding FIFO and not a transmitting FIFO.
0958      * We could add the complexity of filling the entire transmit
0959      * buffer, but we would just wait longer between accesses......
0960      */
0961     for (i = 0; i < count; i++, string++) {
0962         /* Wait for transmitter fifo to empty.
0963          * Ready indicates output is ready, and xmt is doing
0964          * that, not that it is ready for us to send.
0965          */
0966         while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
0967             ;
0968 
0969         /* Send the character out.
0970          * If the buffer address is in the CPM DPRAM, don't
0971          * convert it.
0972          */
0973         cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
0974                     pinfo);
0975         *cpm_outp_addr = *string;
0976 
0977         out_be16(&bdp->cbd_datlen, 1);
0978         setbits16(&bdp->cbd_sc, BD_SC_READY);
0979 
0980         if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
0981             bdp = bdbase;
0982         else
0983             bdp++;
0984 
0985         /* if a LF, also do CR... */
0986         if (handle_linefeed && *string == 10) {
0987             while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
0988                 ;
0989 
0990             cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
0991                         pinfo);
0992             *cpm_outp_addr = 13;
0993 
0994             out_be16(&bdp->cbd_datlen, 1);
0995             setbits16(&bdp->cbd_sc, BD_SC_READY);
0996 
0997             if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
0998                 bdp = bdbase;
0999             else
1000                 bdp++;
1001         }
1002     }
1003 
1004     /*
1005      * Finally, Wait for transmitter & holding register to empty
1006      *  and restore the IER
1007      */
1008     while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1009         ;
1010 
1011     pinfo->tx_cur = bdp;
1012 }
1013 #endif
1014 
1015 #ifdef CONFIG_CONSOLE_POLL
1016 /* Serial polling routines for writing and reading from the uart while
1017  * in an interrupt or debug context.
1018  */
1019 
1020 #define GDB_BUF_SIZE    512 /* power of 2, please */
1021 
1022 static char poll_buf[GDB_BUF_SIZE];
1023 static char *pollp;
1024 static int poll_chars;
1025 
1026 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1027 {
1028     u_char      c, *cp;
1029     volatile cbd_t  *bdp;
1030     int     i;
1031 
1032     /* Get the address of the host memory buffer.
1033      */
1034     bdp = pinfo->rx_cur;
1035     if (bdp->cbd_sc & BD_SC_EMPTY)
1036         return NO_POLL_CHAR;
1037 
1038     /* If the buffer address is in the CPM DPRAM, don't
1039      * convert it.
1040      */
1041     cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1042 
1043     if (obuf) {
1044         i = c = bdp->cbd_datlen;
1045         while (i-- > 0)
1046             *obuf++ = *cp++;
1047     } else
1048         c = *cp;
1049     bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1050     bdp->cbd_sc |= BD_SC_EMPTY;
1051 
1052     if (bdp->cbd_sc & BD_SC_WRAP)
1053         bdp = pinfo->rx_bd_base;
1054     else
1055         bdp++;
1056     pinfo->rx_cur = (cbd_t *)bdp;
1057 
1058     return (int)c;
1059 }
1060 
1061 static int cpm_get_poll_char(struct uart_port *port)
1062 {
1063     struct uart_cpm_port *pinfo =
1064         container_of(port, struct uart_cpm_port, port);
1065 
1066     if (!serial_polled) {
1067         serial_polled = 1;
1068         poll_chars = 0;
1069     }
1070     if (poll_chars <= 0) {
1071         int ret = poll_wait_key(poll_buf, pinfo);
1072 
1073         if (ret == NO_POLL_CHAR)
1074             return ret;
1075         poll_chars = ret;
1076         pollp = poll_buf;
1077     }
1078     poll_chars--;
1079     return *pollp++;
1080 }
1081 
1082 static void cpm_put_poll_char(struct uart_port *port,
1083              unsigned char c)
1084 {
1085     struct uart_cpm_port *pinfo =
1086         container_of(port, struct uart_cpm_port, port);
1087     static char ch[2];
1088 
1089     ch[0] = (char)c;
1090     cpm_uart_early_write(pinfo, ch, 1, false);
1091 }
1092 
1093 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1094 static struct uart_port *udbg_port;
1095 
1096 static void udbg_cpm_putc(char c)
1097 {
1098     if (c == '\n')
1099         cpm_put_poll_char(udbg_port, '\r');
1100     cpm_put_poll_char(udbg_port, c);
1101 }
1102 
1103 static int udbg_cpm_getc_poll(void)
1104 {
1105     int c = cpm_get_poll_char(udbg_port);
1106 
1107     return c == NO_POLL_CHAR ? -1 : c;
1108 }
1109 
1110 static int udbg_cpm_getc(void)
1111 {
1112     int c;
1113 
1114     while ((c = udbg_cpm_getc_poll()) == -1)
1115         cpu_relax();
1116     return c;
1117 }
1118 #endif /* CONFIG_SERIAL_CPM_CONSOLE */
1119 
1120 #endif /* CONFIG_CONSOLE_POLL */
1121 
1122 static const struct uart_ops cpm_uart_pops = {
1123     .tx_empty   = cpm_uart_tx_empty,
1124     .set_mctrl  = cpm_uart_set_mctrl,
1125     .get_mctrl  = cpm_uart_get_mctrl,
1126     .stop_tx    = cpm_uart_stop_tx,
1127     .start_tx   = cpm_uart_start_tx,
1128     .stop_rx    = cpm_uart_stop_rx,
1129     .break_ctl  = cpm_uart_break_ctl,
1130     .startup    = cpm_uart_startup,
1131     .shutdown   = cpm_uart_shutdown,
1132     .set_termios    = cpm_uart_set_termios,
1133     .type       = cpm_uart_type,
1134     .release_port   = cpm_uart_release_port,
1135     .request_port   = cpm_uart_request_port,
1136     .config_port    = cpm_uart_config_port,
1137     .verify_port    = cpm_uart_verify_port,
1138 #ifdef CONFIG_CONSOLE_POLL
1139     .poll_get_char = cpm_get_poll_char,
1140     .poll_put_char = cpm_put_poll_char,
1141 #endif
1142 };
1143 
1144 struct uart_cpm_port cpm_uart_ports[UART_NR];
1145 
1146 static int cpm_uart_init_port(struct device_node *np,
1147                               struct uart_cpm_port *pinfo)
1148 {
1149     const u32 *data;
1150     void __iomem *mem, *pram;
1151     struct device *dev = pinfo->port.dev;
1152     int len;
1153     int ret;
1154     int i;
1155 
1156     data = of_get_property(np, "clock", NULL);
1157     if (data) {
1158         struct clk *clk = clk_get(NULL, (const char*)data);
1159         if (!IS_ERR(clk))
1160             pinfo->clk = clk;
1161     }
1162     if (!pinfo->clk) {
1163         data = of_get_property(np, "fsl,cpm-brg", &len);
1164         if (!data || len != 4) {
1165             printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1166                             "fsl,cpm-brg property.\n", np);
1167             return -EINVAL;
1168         }
1169         pinfo->brg = *data;
1170     }
1171 
1172     data = of_get_property(np, "fsl,cpm-command", &len);
1173     if (!data || len != 4) {
1174         printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1175                         "fsl,cpm-command property.\n", np);
1176         return -EINVAL;
1177     }
1178     pinfo->command = *data;
1179 
1180     mem = of_iomap(np, 0);
1181     if (!mem)
1182         return -ENOMEM;
1183 
1184     if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1185         of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1186         pinfo->sccp = mem;
1187         pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1188     } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1189                of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1190         pinfo->flags |= FLAG_SMC;
1191         pinfo->smcp = mem;
1192         pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1193     } else {
1194         ret = -ENODEV;
1195         goto out_mem;
1196     }
1197 
1198     if (!pram) {
1199         ret = -ENOMEM;
1200         goto out_mem;
1201     }
1202 
1203     pinfo->tx_nrfifos = TX_NUM_FIFO;
1204     pinfo->tx_fifosize = TX_BUF_SIZE;
1205     pinfo->rx_nrfifos = RX_NUM_FIFO;
1206     pinfo->rx_fifosize = RX_BUF_SIZE;
1207 
1208     pinfo->port.uartclk = ppc_proc_freq;
1209     pinfo->port.mapbase = (unsigned long)mem;
1210     pinfo->port.type = PORT_CPM;
1211     pinfo->port.ops = &cpm_uart_pops;
1212     pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE);
1213     pinfo->port.iotype = UPIO_MEM;
1214     pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1215     spin_lock_init(&pinfo->port.lock);
1216 
1217     pinfo->port.irq = irq_of_parse_and_map(np, 0);
1218     if (pinfo->port.irq == NO_IRQ) {
1219         ret = -EINVAL;
1220         goto out_pram;
1221     }
1222 
1223     for (i = 0; i < NUM_GPIOS; i++) {
1224         struct gpio_desc *gpiod;
1225 
1226         pinfo->gpios[i] = NULL;
1227 
1228         gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS);
1229 
1230         if (IS_ERR(gpiod)) {
1231             ret = PTR_ERR(gpiod);
1232             goto out_irq;
1233         }
1234 
1235         if (gpiod) {
1236             if (i == GPIO_RTS || i == GPIO_DTR)
1237                 ret = gpiod_direction_output(gpiod, 0);
1238             else
1239                 ret = gpiod_direction_input(gpiod);
1240             if (ret) {
1241                 pr_err("can't set direction for gpio #%d: %d\n",
1242                     i, ret);
1243                 continue;
1244             }
1245             pinfo->gpios[i] = gpiod;
1246         }
1247     }
1248 
1249 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1250 #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE)
1251     if (!udbg_port)
1252 #endif
1253         udbg_putc = NULL;
1254 #endif
1255 
1256     return cpm_uart_request_port(&pinfo->port);
1257 
1258 out_irq:
1259     irq_dispose_mapping(pinfo->port.irq);
1260 out_pram:
1261     cpm_uart_unmap_pram(pinfo, pram);
1262 out_mem:
1263     iounmap(mem);
1264     return ret;
1265 }
1266 
1267 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1268 /*
1269  *  Print a string to the serial port trying not to disturb
1270  *  any possible real use of the port...
1271  *
1272  *  Note that this is called with interrupts already disabled
1273  */
1274 static void cpm_uart_console_write(struct console *co, const char *s,
1275                    u_int count)
1276 {
1277     struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1278     unsigned long flags;
1279     int nolock = oops_in_progress;
1280 
1281     if (unlikely(nolock)) {
1282         local_irq_save(flags);
1283     } else {
1284         spin_lock_irqsave(&pinfo->port.lock, flags);
1285     }
1286 
1287     cpm_uart_early_write(pinfo, s, count, true);
1288 
1289     if (unlikely(nolock)) {
1290         local_irq_restore(flags);
1291     } else {
1292         spin_unlock_irqrestore(&pinfo->port.lock, flags);
1293     }
1294 }
1295 
1296 
1297 static int __init cpm_uart_console_setup(struct console *co, char *options)
1298 {
1299     int baud = 38400;
1300     int bits = 8;
1301     int parity = 'n';
1302     int flow = 'n';
1303     int ret;
1304     struct uart_cpm_port *pinfo;
1305     struct uart_port *port;
1306 
1307     struct device_node *np;
1308     int i = 0;
1309 
1310     if (co->index >= UART_NR) {
1311         printk(KERN_ERR "cpm_uart: console index %d too high\n",
1312                co->index);
1313         return -ENODEV;
1314     }
1315 
1316     for_each_node_by_type(np, "serial") {
1317         if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1318             !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1319             !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1320             !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1321             continue;
1322 
1323         if (i++ == co->index)
1324             break;
1325     }
1326 
1327     if (!np)
1328         return -ENODEV;
1329 
1330     pinfo = &cpm_uart_ports[co->index];
1331 
1332     pinfo->flags |= FLAG_CONSOLE;
1333     port = &pinfo->port;
1334 
1335     ret = cpm_uart_init_port(np, pinfo);
1336     of_node_put(np);
1337     if (ret)
1338         return ret;
1339 
1340     if (options) {
1341         uart_parse_options(options, &baud, &parity, &bits, &flow);
1342     } else {
1343         if ((baud = uart_baudrate()) == -1)
1344             baud = 9600;
1345     }
1346 
1347     if (IS_SMC(pinfo)) {
1348         out_be16(&pinfo->smcup->smc_brkcr, 0);
1349         cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1350         clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1351         clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1352     } else {
1353         out_be16(&pinfo->sccup->scc_brkcr, 0);
1354         cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1355         clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1356         clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1357     }
1358 
1359     ret = cpm_uart_allocbuf(pinfo, 1);
1360 
1361     if (ret)
1362         return ret;
1363 
1364     cpm_uart_initbd(pinfo);
1365 
1366     if (IS_SMC(pinfo))
1367         cpm_uart_init_smc(pinfo);
1368     else
1369         cpm_uart_init_scc(pinfo);
1370 
1371     uart_set_options(port, co, baud, parity, bits, flow);
1372     cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1373 
1374 #ifdef CONFIG_CONSOLE_POLL
1375     if (!udbg_port) {
1376         udbg_port = &pinfo->port;
1377         udbg_putc = udbg_cpm_putc;
1378         udbg_getc = udbg_cpm_getc;
1379         udbg_getc_poll = udbg_cpm_getc_poll;
1380     }
1381 #endif
1382 
1383     return 0;
1384 }
1385 
1386 static struct uart_driver cpm_reg;
1387 static struct console cpm_scc_uart_console = {
1388     .name       = "ttyCPM",
1389     .write      = cpm_uart_console_write,
1390     .device     = uart_console_device,
1391     .setup      = cpm_uart_console_setup,
1392     .flags      = CON_PRINTBUFFER,
1393     .index      = -1,
1394     .data       = &cpm_reg,
1395 };
1396 
1397 static int __init cpm_uart_console_init(void)
1398 {
1399     cpm_muram_init();
1400     register_console(&cpm_scc_uart_console);
1401     return 0;
1402 }
1403 
1404 console_initcall(cpm_uart_console_init);
1405 
1406 #define CPM_UART_CONSOLE    &cpm_scc_uart_console
1407 #else
1408 #define CPM_UART_CONSOLE    NULL
1409 #endif
1410 
1411 static struct uart_driver cpm_reg = {
1412     .owner      = THIS_MODULE,
1413     .driver_name    = "ttyCPM",
1414     .dev_name   = "ttyCPM",
1415     .major      = SERIAL_CPM_MAJOR,
1416     .minor      = SERIAL_CPM_MINOR,
1417     .cons       = CPM_UART_CONSOLE,
1418     .nr     = UART_NR,
1419 };
1420 
1421 static int probe_index;
1422 
1423 static int cpm_uart_probe(struct platform_device *ofdev)
1424 {
1425     int index = probe_index++;
1426     struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1427     int ret;
1428 
1429     pinfo->port.line = index;
1430 
1431     if (index >= UART_NR)
1432         return -ENODEV;
1433 
1434     platform_set_drvdata(ofdev, pinfo);
1435 
1436     /* initialize the device pointer for the port */
1437     pinfo->port.dev = &ofdev->dev;
1438 
1439     ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1440     if (ret)
1441         return ret;
1442 
1443     return uart_add_one_port(&cpm_reg, &pinfo->port);
1444 }
1445 
1446 static int cpm_uart_remove(struct platform_device *ofdev)
1447 {
1448     struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1449     return uart_remove_one_port(&cpm_reg, &pinfo->port);
1450 }
1451 
1452 static const struct of_device_id cpm_uart_match[] = {
1453     {
1454         .compatible = "fsl,cpm1-smc-uart",
1455     },
1456     {
1457         .compatible = "fsl,cpm1-scc-uart",
1458     },
1459     {
1460         .compatible = "fsl,cpm2-smc-uart",
1461     },
1462     {
1463         .compatible = "fsl,cpm2-scc-uart",
1464     },
1465     {}
1466 };
1467 MODULE_DEVICE_TABLE(of, cpm_uart_match);
1468 
1469 static struct platform_driver cpm_uart_driver = {
1470     .driver = {
1471         .name = "cpm_uart",
1472         .of_match_table = cpm_uart_match,
1473     },
1474     .probe = cpm_uart_probe,
1475     .remove = cpm_uart_remove,
1476  };
1477 
1478 static int __init cpm_uart_init(void)
1479 {
1480     int ret = uart_register_driver(&cpm_reg);
1481     if (ret)
1482         return ret;
1483 
1484     ret = platform_driver_register(&cpm_uart_driver);
1485     if (ret)
1486         uart_unregister_driver(&cpm_reg);
1487 
1488     return ret;
1489 }
1490 
1491 static void __exit cpm_uart_exit(void)
1492 {
1493     platform_driver_unregister(&cpm_uart_driver);
1494     uart_unregister_driver(&cpm_reg);
1495 }
1496 
1497 module_init(cpm_uart_init);
1498 module_exit(cpm_uart_exit);
1499 
1500 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1501 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1502 MODULE_LICENSE("GPL");
1503 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
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