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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Derived from many drivers using generic_serial interface.
0004  *
0005  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
0006  *
0007  *  Serial driver for BCM63xx integrated UART.
0008  *
0009  * Hardware flow control was _not_ tested since I only have RX/TX on
0010  * my board.
0011  */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/init.h>
0016 #include <linux/delay.h>
0017 #include <linux/module.h>
0018 #include <linux/console.h>
0019 #include <linux/clk.h>
0020 #include <linux/tty.h>
0021 #include <linux/tty_flip.h>
0022 #include <linux/sysrq.h>
0023 #include <linux/serial.h>
0024 #include <linux/serial_core.h>
0025 #include <linux/serial_bcm63xx.h>
0026 #include <linux/io.h>
0027 #include <linux/of.h>
0028 
0029 #define BCM63XX_NR_UARTS    2
0030 
0031 static struct uart_port ports[BCM63XX_NR_UARTS];
0032 
0033 /*
0034  * rx interrupt mask / stat
0035  *
0036  * mask:
0037  *  - rx fifo full
0038  *  - rx fifo above threshold
0039  *  - rx fifo not empty for too long
0040  */
0041 #define UART_RX_INT_MASK    (UART_IR_MASK(UART_IR_RXOVER) |     \
0042                 UART_IR_MASK(UART_IR_RXTHRESH) |    \
0043                 UART_IR_MASK(UART_IR_RXTIMEOUT))
0044 
0045 #define UART_RX_INT_STAT    (UART_IR_STAT(UART_IR_RXOVER) |     \
0046                 UART_IR_STAT(UART_IR_RXTHRESH) |    \
0047                 UART_IR_STAT(UART_IR_RXTIMEOUT))
0048 
0049 /*
0050  * tx interrupt mask / stat
0051  *
0052  * mask:
0053  * - tx fifo empty
0054  * - tx fifo below threshold
0055  */
0056 #define UART_TX_INT_MASK    (UART_IR_MASK(UART_IR_TXEMPTY) |    \
0057                 UART_IR_MASK(UART_IR_TXTRESH))
0058 
0059 #define UART_TX_INT_STAT    (UART_IR_STAT(UART_IR_TXEMPTY) |    \
0060                 UART_IR_STAT(UART_IR_TXTRESH))
0061 
0062 /*
0063  * external input interrupt
0064  *
0065  * mask: any edge on CTS, DCD
0066  */
0067 #define UART_EXTINP_INT_MASK    (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
0068                  UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
0069 
0070 /*
0071  * handy uart register accessor
0072  */
0073 static inline unsigned int bcm_uart_readl(struct uart_port *port,
0074                      unsigned int offset)
0075 {
0076     return __raw_readl(port->membase + offset);
0077 }
0078 
0079 static inline void bcm_uart_writel(struct uart_port *port,
0080                   unsigned int value, unsigned int offset)
0081 {
0082     __raw_writel(value, port->membase + offset);
0083 }
0084 
0085 /*
0086  * serial core request to check if uart tx fifo is empty
0087  */
0088 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
0089 {
0090     unsigned int val;
0091 
0092     val = bcm_uart_readl(port, UART_IR_REG);
0093     return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
0094 }
0095 
0096 /*
0097  * serial core request to set RTS and DTR pin state and loopback mode
0098  */
0099 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
0100 {
0101     unsigned int val;
0102 
0103     val = bcm_uart_readl(port, UART_MCTL_REG);
0104     val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
0105     /* invert of written value is reflected on the pin */
0106     if (!(mctrl & TIOCM_DTR))
0107         val |= UART_MCTL_DTR_MASK;
0108     if (!(mctrl & TIOCM_RTS))
0109         val |= UART_MCTL_RTS_MASK;
0110     bcm_uart_writel(port, val, UART_MCTL_REG);
0111 
0112     val = bcm_uart_readl(port, UART_CTL_REG);
0113     if (mctrl & TIOCM_LOOP)
0114         val |= UART_CTL_LOOPBACK_MASK;
0115     else
0116         val &= ~UART_CTL_LOOPBACK_MASK;
0117     bcm_uart_writel(port, val, UART_CTL_REG);
0118 }
0119 
0120 /*
0121  * serial core request to return RI, CTS, DCD and DSR pin state
0122  */
0123 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
0124 {
0125     unsigned int val, mctrl;
0126 
0127     mctrl = 0;
0128     val = bcm_uart_readl(port, UART_EXTINP_REG);
0129     if (val & UART_EXTINP_RI_MASK)
0130         mctrl |= TIOCM_RI;
0131     if (val & UART_EXTINP_CTS_MASK)
0132         mctrl |= TIOCM_CTS;
0133     if (val & UART_EXTINP_DCD_MASK)
0134         mctrl |= TIOCM_CD;
0135     if (val & UART_EXTINP_DSR_MASK)
0136         mctrl |= TIOCM_DSR;
0137     return mctrl;
0138 }
0139 
0140 /*
0141  * serial core request to disable tx ASAP (used for flow control)
0142  */
0143 static void bcm_uart_stop_tx(struct uart_port *port)
0144 {
0145     unsigned int val;
0146 
0147     val = bcm_uart_readl(port, UART_CTL_REG);
0148     val &= ~(UART_CTL_TXEN_MASK);
0149     bcm_uart_writel(port, val, UART_CTL_REG);
0150 
0151     val = bcm_uart_readl(port, UART_IR_REG);
0152     val &= ~UART_TX_INT_MASK;
0153     bcm_uart_writel(port, val, UART_IR_REG);
0154 }
0155 
0156 /*
0157  * serial core request to (re)enable tx
0158  */
0159 static void bcm_uart_start_tx(struct uart_port *port)
0160 {
0161     unsigned int val;
0162 
0163     val = bcm_uart_readl(port, UART_IR_REG);
0164     val |= UART_TX_INT_MASK;
0165     bcm_uart_writel(port, val, UART_IR_REG);
0166 
0167     val = bcm_uart_readl(port, UART_CTL_REG);
0168     val |= UART_CTL_TXEN_MASK;
0169     bcm_uart_writel(port, val, UART_CTL_REG);
0170 }
0171 
0172 /*
0173  * serial core request to stop rx, called before port shutdown
0174  */
0175 static void bcm_uart_stop_rx(struct uart_port *port)
0176 {
0177     unsigned int val;
0178 
0179     val = bcm_uart_readl(port, UART_IR_REG);
0180     val &= ~UART_RX_INT_MASK;
0181     bcm_uart_writel(port, val, UART_IR_REG);
0182 }
0183 
0184 /*
0185  * serial core request to enable modem status interrupt reporting
0186  */
0187 static void bcm_uart_enable_ms(struct uart_port *port)
0188 {
0189     unsigned int val;
0190 
0191     val = bcm_uart_readl(port, UART_IR_REG);
0192     val |= UART_IR_MASK(UART_IR_EXTIP);
0193     bcm_uart_writel(port, val, UART_IR_REG);
0194 }
0195 
0196 /*
0197  * serial core request to start/stop emitting break char
0198  */
0199 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
0200 {
0201     unsigned long flags;
0202     unsigned int val;
0203 
0204     spin_lock_irqsave(&port->lock, flags);
0205 
0206     val = bcm_uart_readl(port, UART_CTL_REG);
0207     if (ctl)
0208         val |= UART_CTL_XMITBRK_MASK;
0209     else
0210         val &= ~UART_CTL_XMITBRK_MASK;
0211     bcm_uart_writel(port, val, UART_CTL_REG);
0212 
0213     spin_unlock_irqrestore(&port->lock, flags);
0214 }
0215 
0216 /*
0217  * return port type in string format
0218  */
0219 static const char *bcm_uart_type(struct uart_port *port)
0220 {
0221     return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
0222 }
0223 
0224 /*
0225  * read all chars in rx fifo and send them to core
0226  */
0227 static void bcm_uart_do_rx(struct uart_port *port)
0228 {
0229     struct tty_port *tty_port = &port->state->port;
0230     unsigned int max_count;
0231 
0232     /* limit number of char read in interrupt, should not be
0233      * higher than fifo size anyway since we're much faster than
0234      * serial port */
0235     max_count = 32;
0236     do {
0237         unsigned int iestat, c, cstat;
0238         char flag;
0239 
0240         /* get overrun/fifo empty information from ier
0241          * register */
0242         iestat = bcm_uart_readl(port, UART_IR_REG);
0243 
0244         if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
0245             unsigned int val;
0246 
0247             /* fifo reset is required to clear
0248              * interrupt */
0249             val = bcm_uart_readl(port, UART_CTL_REG);
0250             val |= UART_CTL_RSTRXFIFO_MASK;
0251             bcm_uart_writel(port, val, UART_CTL_REG);
0252 
0253             port->icount.overrun++;
0254             tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
0255         }
0256 
0257         if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
0258             break;
0259 
0260         cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
0261         port->icount.rx++;
0262         flag = TTY_NORMAL;
0263         c &= 0xff;
0264 
0265         if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
0266             /* do stats first */
0267             if (cstat & UART_FIFO_BRKDET_MASK) {
0268                 port->icount.brk++;
0269                 if (uart_handle_break(port))
0270                     continue;
0271             }
0272 
0273             if (cstat & UART_FIFO_PARERR_MASK)
0274                 port->icount.parity++;
0275             if (cstat & UART_FIFO_FRAMEERR_MASK)
0276                 port->icount.frame++;
0277 
0278             /* update flag wrt read_status_mask */
0279             cstat &= port->read_status_mask;
0280             if (cstat & UART_FIFO_BRKDET_MASK)
0281                 flag = TTY_BREAK;
0282             if (cstat & UART_FIFO_FRAMEERR_MASK)
0283                 flag = TTY_FRAME;
0284             if (cstat & UART_FIFO_PARERR_MASK)
0285                 flag = TTY_PARITY;
0286         }
0287 
0288         if (uart_handle_sysrq_char(port, c))
0289             continue;
0290 
0291 
0292         if ((cstat & port->ignore_status_mask) == 0)
0293             tty_insert_flip_char(tty_port, c, flag);
0294 
0295     } while (--max_count);
0296 
0297     tty_flip_buffer_push(tty_port);
0298 }
0299 
0300 /*
0301  * fill tx fifo with chars to send, stop when fifo is about to be full
0302  * or when all chars have been sent.
0303  */
0304 static void bcm_uart_do_tx(struct uart_port *port)
0305 {
0306     struct circ_buf *xmit;
0307     unsigned int val, max_count;
0308 
0309     if (port->x_char) {
0310         bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
0311         port->icount.tx++;
0312         port->x_char = 0;
0313         return;
0314     }
0315 
0316     if (uart_tx_stopped(port)) {
0317         bcm_uart_stop_tx(port);
0318         return;
0319     }
0320 
0321     xmit = &port->state->xmit;
0322     if (uart_circ_empty(xmit))
0323         goto txq_empty;
0324 
0325     val = bcm_uart_readl(port, UART_MCTL_REG);
0326     val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
0327     max_count = port->fifosize - val;
0328 
0329     while (max_count--) {
0330         unsigned int c;
0331 
0332         c = xmit->buf[xmit->tail];
0333         bcm_uart_writel(port, c, UART_FIFO_REG);
0334         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0335         port->icount.tx++;
0336         if (uart_circ_empty(xmit))
0337             break;
0338     }
0339 
0340     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0341         uart_write_wakeup(port);
0342 
0343     if (uart_circ_empty(xmit))
0344         goto txq_empty;
0345     return;
0346 
0347 txq_empty:
0348     /* nothing to send, disable transmit interrupt */
0349     val = bcm_uart_readl(port, UART_IR_REG);
0350     val &= ~UART_TX_INT_MASK;
0351     bcm_uart_writel(port, val, UART_IR_REG);
0352     return;
0353 }
0354 
0355 /*
0356  * process uart interrupt
0357  */
0358 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
0359 {
0360     struct uart_port *port;
0361     unsigned int irqstat;
0362 
0363     port = dev_id;
0364     spin_lock(&port->lock);
0365 
0366     irqstat = bcm_uart_readl(port, UART_IR_REG);
0367     if (irqstat & UART_RX_INT_STAT)
0368         bcm_uart_do_rx(port);
0369 
0370     if (irqstat & UART_TX_INT_STAT)
0371         bcm_uart_do_tx(port);
0372 
0373     if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
0374         unsigned int estat;
0375 
0376         estat = bcm_uart_readl(port, UART_EXTINP_REG);
0377         if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
0378             uart_handle_cts_change(port,
0379                            estat & UART_EXTINP_CTS_MASK);
0380         if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
0381             uart_handle_dcd_change(port,
0382                            estat & UART_EXTINP_DCD_MASK);
0383     }
0384 
0385     spin_unlock(&port->lock);
0386     return IRQ_HANDLED;
0387 }
0388 
0389 /*
0390  * enable rx & tx operation on uart
0391  */
0392 static void bcm_uart_enable(struct uart_port *port)
0393 {
0394     unsigned int val;
0395 
0396     val = bcm_uart_readl(port, UART_CTL_REG);
0397     val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
0398     bcm_uart_writel(port, val, UART_CTL_REG);
0399 }
0400 
0401 /*
0402  * disable rx & tx operation on uart
0403  */
0404 static void bcm_uart_disable(struct uart_port *port)
0405 {
0406     unsigned int val;
0407 
0408     val = bcm_uart_readl(port, UART_CTL_REG);
0409     val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
0410          UART_CTL_RXEN_MASK);
0411     bcm_uart_writel(port, val, UART_CTL_REG);
0412 }
0413 
0414 /*
0415  * clear all unread data in rx fifo and unsent data in tx fifo
0416  */
0417 static void bcm_uart_flush(struct uart_port *port)
0418 {
0419     unsigned int val;
0420 
0421     /* empty rx and tx fifo */
0422     val = bcm_uart_readl(port, UART_CTL_REG);
0423     val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
0424     bcm_uart_writel(port, val, UART_CTL_REG);
0425 
0426     /* read any pending char to make sure all irq status are
0427      * cleared */
0428     (void)bcm_uart_readl(port, UART_FIFO_REG);
0429 }
0430 
0431 /*
0432  * serial core request to initialize uart and start rx operation
0433  */
0434 static int bcm_uart_startup(struct uart_port *port)
0435 {
0436     unsigned int val;
0437     int ret;
0438 
0439     /* mask all irq and flush port */
0440     bcm_uart_disable(port);
0441     bcm_uart_writel(port, 0, UART_IR_REG);
0442     bcm_uart_flush(port);
0443 
0444     /* clear any pending external input interrupt */
0445     (void)bcm_uart_readl(port, UART_EXTINP_REG);
0446 
0447     /* set rx/tx fifo thresh to fifo half size */
0448     val = bcm_uart_readl(port, UART_MCTL_REG);
0449     val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
0450     val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
0451     val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
0452     bcm_uart_writel(port, val, UART_MCTL_REG);
0453 
0454     /* set rx fifo timeout to 1 char time */
0455     val = bcm_uart_readl(port, UART_CTL_REG);
0456     val &= ~UART_CTL_RXTMOUTCNT_MASK;
0457     val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
0458     bcm_uart_writel(port, val, UART_CTL_REG);
0459 
0460     /* report any edge on dcd and cts */
0461     val = UART_EXTINP_INT_MASK;
0462     val |= UART_EXTINP_DCD_NOSENSE_MASK;
0463     val |= UART_EXTINP_CTS_NOSENSE_MASK;
0464     bcm_uart_writel(port, val, UART_EXTINP_REG);
0465 
0466     /* register irq and enable rx interrupts */
0467     ret = request_irq(port->irq, bcm_uart_interrupt, 0,
0468               dev_name(port->dev), port);
0469     if (ret)
0470         return ret;
0471     bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
0472     bcm_uart_enable(port);
0473     return 0;
0474 }
0475 
0476 /*
0477  * serial core request to flush & disable uart
0478  */
0479 static void bcm_uart_shutdown(struct uart_port *port)
0480 {
0481     unsigned long flags;
0482 
0483     spin_lock_irqsave(&port->lock, flags);
0484     bcm_uart_writel(port, 0, UART_IR_REG);
0485     spin_unlock_irqrestore(&port->lock, flags);
0486 
0487     bcm_uart_disable(port);
0488     bcm_uart_flush(port);
0489     free_irq(port->irq, port);
0490 }
0491 
0492 /*
0493  * serial core request to change current uart setting
0494  */
0495 static void bcm_uart_set_termios(struct uart_port *port,
0496                  struct ktermios *new,
0497                  struct ktermios *old)
0498 {
0499     unsigned int ctl, baud, quot, ier;
0500     unsigned long flags;
0501     int tries;
0502 
0503     spin_lock_irqsave(&port->lock, flags);
0504 
0505     /* Drain the hot tub fully before we power it off for the winter. */
0506     for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
0507         mdelay(10);
0508 
0509     /* disable uart while changing speed */
0510     bcm_uart_disable(port);
0511     bcm_uart_flush(port);
0512 
0513     /* update Control register */
0514     ctl = bcm_uart_readl(port, UART_CTL_REG);
0515     ctl &= ~UART_CTL_BITSPERSYM_MASK;
0516 
0517     switch (new->c_cflag & CSIZE) {
0518     case CS5:
0519         ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
0520         break;
0521     case CS6:
0522         ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
0523         break;
0524     case CS7:
0525         ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
0526         break;
0527     default:
0528         ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
0529         break;
0530     }
0531 
0532     ctl &= ~UART_CTL_STOPBITS_MASK;
0533     if (new->c_cflag & CSTOPB)
0534         ctl |= UART_CTL_STOPBITS_2;
0535     else
0536         ctl |= UART_CTL_STOPBITS_1;
0537 
0538     ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
0539     if (new->c_cflag & PARENB)
0540         ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
0541     ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
0542     if (new->c_cflag & PARODD)
0543         ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
0544     bcm_uart_writel(port, ctl, UART_CTL_REG);
0545 
0546     /* update Baudword register */
0547     baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
0548     quot = uart_get_divisor(port, baud) - 1;
0549     bcm_uart_writel(port, quot, UART_BAUD_REG);
0550 
0551     /* update Interrupt register */
0552     ier = bcm_uart_readl(port, UART_IR_REG);
0553 
0554     ier &= ~UART_IR_MASK(UART_IR_EXTIP);
0555     if (UART_ENABLE_MS(port, new->c_cflag))
0556         ier |= UART_IR_MASK(UART_IR_EXTIP);
0557 
0558     bcm_uart_writel(port, ier, UART_IR_REG);
0559 
0560     /* update read/ignore mask */
0561     port->read_status_mask = UART_FIFO_VALID_MASK;
0562     if (new->c_iflag & INPCK) {
0563         port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
0564         port->read_status_mask |= UART_FIFO_PARERR_MASK;
0565     }
0566     if (new->c_iflag & (IGNBRK | BRKINT))
0567         port->read_status_mask |= UART_FIFO_BRKDET_MASK;
0568 
0569     port->ignore_status_mask = 0;
0570     if (new->c_iflag & IGNPAR)
0571         port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
0572     if (new->c_iflag & IGNBRK)
0573         port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
0574     if (!(new->c_cflag & CREAD))
0575         port->ignore_status_mask |= UART_FIFO_VALID_MASK;
0576 
0577     uart_update_timeout(port, new->c_cflag, baud);
0578     bcm_uart_enable(port);
0579     spin_unlock_irqrestore(&port->lock, flags);
0580 }
0581 
0582 /*
0583  * serial core request to claim uart iomem
0584  */
0585 static int bcm_uart_request_port(struct uart_port *port)
0586 {
0587     /* UARTs always present */
0588     return 0;
0589 }
0590 
0591 /*
0592  * serial core request to release uart iomem
0593  */
0594 static void bcm_uart_release_port(struct uart_port *port)
0595 {
0596     /* Nothing to release ... */
0597 }
0598 
0599 /*
0600  * serial core request to do any port required autoconfiguration
0601  */
0602 static void bcm_uart_config_port(struct uart_port *port, int flags)
0603 {
0604     if (flags & UART_CONFIG_TYPE) {
0605         if (bcm_uart_request_port(port))
0606             return;
0607         port->type = PORT_BCM63XX;
0608     }
0609 }
0610 
0611 /*
0612  * serial core request to check that port information in serinfo are
0613  * suitable
0614  */
0615 static int bcm_uart_verify_port(struct uart_port *port,
0616                 struct serial_struct *serinfo)
0617 {
0618     if (port->type != PORT_BCM63XX)
0619         return -EINVAL;
0620     if (port->irq != serinfo->irq)
0621         return -EINVAL;
0622     if (port->iotype != serinfo->io_type)
0623         return -EINVAL;
0624     if (port->mapbase != (unsigned long)serinfo->iomem_base)
0625         return -EINVAL;
0626     return 0;
0627 }
0628 
0629 /* serial core callbacks */
0630 static const struct uart_ops bcm_uart_ops = {
0631     .tx_empty   = bcm_uart_tx_empty,
0632     .get_mctrl  = bcm_uart_get_mctrl,
0633     .set_mctrl  = bcm_uart_set_mctrl,
0634     .start_tx   = bcm_uart_start_tx,
0635     .stop_tx    = bcm_uart_stop_tx,
0636     .stop_rx    = bcm_uart_stop_rx,
0637     .enable_ms  = bcm_uart_enable_ms,
0638     .break_ctl  = bcm_uart_break_ctl,
0639     .startup    = bcm_uart_startup,
0640     .shutdown   = bcm_uart_shutdown,
0641     .set_termios    = bcm_uart_set_termios,
0642     .type       = bcm_uart_type,
0643     .release_port   = bcm_uart_release_port,
0644     .request_port   = bcm_uart_request_port,
0645     .config_port    = bcm_uart_config_port,
0646     .verify_port    = bcm_uart_verify_port,
0647 };
0648 
0649 
0650 
0651 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
0652 static void wait_for_xmitr(struct uart_port *port)
0653 {
0654     unsigned int tmout;
0655 
0656     /* Wait up to 10ms for the character(s) to be sent. */
0657     tmout = 10000;
0658     while (--tmout) {
0659         unsigned int val;
0660 
0661         val = bcm_uart_readl(port, UART_IR_REG);
0662         if (val & UART_IR_STAT(UART_IR_TXEMPTY))
0663             break;
0664         udelay(1);
0665     }
0666 
0667     /* Wait up to 1s for flow control if necessary */
0668     if (port->flags & UPF_CONS_FLOW) {
0669         tmout = 1000000;
0670         while (--tmout) {
0671             unsigned int val;
0672 
0673             val = bcm_uart_readl(port, UART_EXTINP_REG);
0674             if (val & UART_EXTINP_CTS_MASK)
0675                 break;
0676             udelay(1);
0677         }
0678     }
0679 }
0680 
0681 /*
0682  * output given char
0683  */
0684 static void bcm_console_putchar(struct uart_port *port, unsigned char ch)
0685 {
0686     wait_for_xmitr(port);
0687     bcm_uart_writel(port, ch, UART_FIFO_REG);
0688 }
0689 
0690 /*
0691  * console core request to output given string
0692  */
0693 static void bcm_console_write(struct console *co, const char *s,
0694                   unsigned int count)
0695 {
0696     struct uart_port *port;
0697     unsigned long flags;
0698     int locked;
0699 
0700     port = &ports[co->index];
0701 
0702     local_irq_save(flags);
0703     if (port->sysrq) {
0704         /* bcm_uart_interrupt() already took the lock */
0705         locked = 0;
0706     } else if (oops_in_progress) {
0707         locked = spin_trylock(&port->lock);
0708     } else {
0709         spin_lock(&port->lock);
0710         locked = 1;
0711     }
0712 
0713     /* call helper to deal with \r\n */
0714     uart_console_write(port, s, count, bcm_console_putchar);
0715 
0716     /* and wait for char to be transmitted */
0717     wait_for_xmitr(port);
0718 
0719     if (locked)
0720         spin_unlock(&port->lock);
0721     local_irq_restore(flags);
0722 }
0723 
0724 /*
0725  * console core request to setup given console, find matching uart
0726  * port and setup it.
0727  */
0728 static int bcm_console_setup(struct console *co, char *options)
0729 {
0730     struct uart_port *port;
0731     int baud = 9600;
0732     int bits = 8;
0733     int parity = 'n';
0734     int flow = 'n';
0735 
0736     if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
0737         return -EINVAL;
0738     port = &ports[co->index];
0739     if (!port->membase)
0740         return -ENODEV;
0741     if (options)
0742         uart_parse_options(options, &baud, &parity, &bits, &flow);
0743 
0744     return uart_set_options(port, co, baud, parity, bits, flow);
0745 }
0746 
0747 static struct uart_driver bcm_uart_driver;
0748 
0749 static struct console bcm63xx_console = {
0750     .name       = "ttyS",
0751     .write      = bcm_console_write,
0752     .device     = uart_console_device,
0753     .setup      = bcm_console_setup,
0754     .flags      = CON_PRINTBUFFER,
0755     .index      = -1,
0756     .data       = &bcm_uart_driver,
0757 };
0758 
0759 static int __init bcm63xx_console_init(void)
0760 {
0761     register_console(&bcm63xx_console);
0762     return 0;
0763 }
0764 
0765 console_initcall(bcm63xx_console_init);
0766 
0767 static void bcm_early_write(struct console *con, const char *s, unsigned n)
0768 {
0769     struct earlycon_device *dev = con->data;
0770 
0771     uart_console_write(&dev->port, s, n, bcm_console_putchar);
0772     wait_for_xmitr(&dev->port);
0773 }
0774 
0775 static int __init bcm_early_console_setup(struct earlycon_device *device,
0776                       const char *opt)
0777 {
0778     if (!device->port.membase)
0779         return -ENODEV;
0780 
0781     device->con->write = bcm_early_write;
0782     return 0;
0783 }
0784 
0785 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
0786 
0787 #define BCM63XX_CONSOLE (&bcm63xx_console)
0788 #else
0789 #define BCM63XX_CONSOLE NULL
0790 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
0791 
0792 static struct uart_driver bcm_uart_driver = {
0793     .owner      = THIS_MODULE,
0794     .driver_name    = "bcm63xx_uart",
0795     .dev_name   = "ttyS",
0796     .major      = TTY_MAJOR,
0797     .minor      = 64,
0798     .nr     = BCM63XX_NR_UARTS,
0799     .cons       = BCM63XX_CONSOLE,
0800 };
0801 
0802 /*
0803  * platform driver probe/remove callback
0804  */
0805 static int bcm_uart_probe(struct platform_device *pdev)
0806 {
0807     struct resource *res_mem;
0808     struct uart_port *port;
0809     struct clk *clk;
0810     int ret;
0811 
0812     if (pdev->dev.of_node) {
0813         pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
0814 
0815         if (pdev->id < 0)
0816             pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
0817     }
0818 
0819     if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
0820         return -EINVAL;
0821 
0822     port = &ports[pdev->id];
0823     if (port->membase)
0824         return -EBUSY;
0825     memset(port, 0, sizeof(*port));
0826 
0827     res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0828     if (!res_mem)
0829         return -ENODEV;
0830 
0831     port->mapbase = res_mem->start;
0832     port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
0833     if (IS_ERR(port->membase))
0834         return PTR_ERR(port->membase);
0835 
0836     ret = platform_get_irq(pdev, 0);
0837     if (ret < 0)
0838         return ret;
0839     port->irq = ret;
0840 
0841     clk = clk_get(&pdev->dev, "refclk");
0842     if (IS_ERR(clk) && pdev->dev.of_node)
0843         clk = of_clk_get(pdev->dev.of_node, 0);
0844 
0845     if (IS_ERR(clk))
0846         return -ENODEV;
0847 
0848     port->iotype = UPIO_MEM;
0849     port->ops = &bcm_uart_ops;
0850     port->flags = UPF_BOOT_AUTOCONF;
0851     port->dev = &pdev->dev;
0852     port->fifosize = 16;
0853     port->uartclk = clk_get_rate(clk) / 2;
0854     port->line = pdev->id;
0855     port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
0856     clk_put(clk);
0857 
0858     ret = uart_add_one_port(&bcm_uart_driver, port);
0859     if (ret) {
0860         ports[pdev->id].membase = NULL;
0861         return ret;
0862     }
0863     platform_set_drvdata(pdev, port);
0864     return 0;
0865 }
0866 
0867 static int bcm_uart_remove(struct platform_device *pdev)
0868 {
0869     struct uart_port *port;
0870 
0871     port = platform_get_drvdata(pdev);
0872     uart_remove_one_port(&bcm_uart_driver, port);
0873     /* mark port as free */
0874     ports[pdev->id].membase = NULL;
0875     return 0;
0876 }
0877 
0878 static const struct of_device_id bcm63xx_of_match[] = {
0879     { .compatible = "brcm,bcm6345-uart" },
0880     { /* sentinel */ }
0881 };
0882 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
0883 
0884 /*
0885  * platform driver stuff
0886  */
0887 static struct platform_driver bcm_uart_platform_driver = {
0888     .probe  = bcm_uart_probe,
0889     .remove = bcm_uart_remove,
0890     .driver = {
0891         .name  = "bcm63xx_uart",
0892         .of_match_table = bcm63xx_of_match,
0893     },
0894 };
0895 
0896 static int __init bcm_uart_init(void)
0897 {
0898     int ret;
0899 
0900     ret = uart_register_driver(&bcm_uart_driver);
0901     if (ret)
0902         return ret;
0903 
0904     ret = platform_driver_register(&bcm_uart_platform_driver);
0905     if (ret)
0906         uart_unregister_driver(&bcm_uart_driver);
0907 
0908     return ret;
0909 }
0910 
0911 static void __exit bcm_uart_exit(void)
0912 {
0913     platform_driver_unregister(&bcm_uart_platform_driver);
0914     uart_unregister_driver(&bcm_uart_driver);
0915 }
0916 
0917 module_init(bcm_uart_init);
0918 module_exit(bcm_uart_exit);
0919 
0920 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
0921 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
0922 MODULE_LICENSE("GPL");
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