tty/serial/amba-pl010.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Driver for AMBA serial ports
0004  *
0005  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
0006  *
0007  *  Copyright 1999 ARM Limited
0008  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
0009  *
0010  * This is a generic driver for ARM AMBA-type serial ports.  They
0011  * have a lot of 16550-like features, but are not register compatible.
0012  * Note that although they do have CTS, DCD and DSR inputs, they do
0013  * not have an RI input, nor do they have DTR or RTS outputs.  If
0014  * required, these have to be supplied via some other means (eg, GPIO)
0015  * and hooked into this driver.
0016  */
0017
0018 #include <linux/module.h>
0019 #include <linux/ioport.h>
0020 #include <linux/init.h>
0021 #include <linux/console.h>
0022 #include <linux/sysrq.h>
0023 #include <linux/device.h>
0024 #include <linux/tty.h>
0025 #include <linux/tty_flip.h>
0026 #include <linux/serial_core.h>
0027 #include <linux/serial.h>
0028 #include <linux/amba/bus.h>
0029 #include <linux/amba/serial.h>
0030 #include <linux/clk.h>
0031 #include <linux/slab.h>
0032 #include <linux/io.h>
0033
0034 #define UART_NR     8
0035
0036 #define SERIAL_AMBA_MAJOR   204
0037 #define SERIAL_AMBA_MINOR   16
0038 #define SERIAL_AMBA_NR      UART_NR
0039
0040 #define AMBA_ISR_PASS_LIMIT 256
0041
0042 #define UART_RX_DATA(s)     (((s) & UART01x_FR_RXFE) == 0)
0043 #define UART_TX_READY(s)    (((s) & UART01x_FR_TXFF) == 0)
0044
0045 #define UART_DUMMY_RSR_RX   256
0046 #define UART_PORT_SIZE      64
0047
0048 /*
0049  * We wrap our port structure around the generic uart_port.
0050  */
0051 struct uart_amba_port {
0052     struct uart_port    port;
0053     struct clk      *clk;
0054     struct amba_device  *dev;
0055     struct amba_pl010_data  *data;
0056     unsigned int        old_status;
0057 };
0058
0059 static void pl010_stop_tx(struct uart_port *port)
0060 {
0061     struct uart_amba_port *uap =
0062         container_of(port, struct uart_amba_port, port);
0063     unsigned int cr;
0064
0065     cr = readb(uap->port.membase + UART010_CR);
0066     cr &= ~UART010_CR_TIE;
0067     writel(cr, uap->port.membase + UART010_CR);
0068 }
0069
0070 static void pl010_start_tx(struct uart_port *port)
0071 {
0072     struct uart_amba_port *uap =
0073         container_of(port, struct uart_amba_port, port);
0074     unsigned int cr;
0075
0076     cr = readb(uap->port.membase + UART010_CR);
0077     cr |= UART010_CR_TIE;
0078     writel(cr, uap->port.membase + UART010_CR);
0079 }
0080
0081 static void pl010_stop_rx(struct uart_port *port)
0082 {
0083     struct uart_amba_port *uap =
0084         container_of(port, struct uart_amba_port, port);
0085     unsigned int cr;
0086
0087     cr = readb(uap->port.membase + UART010_CR);
0088     cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
0089     writel(cr, uap->port.membase + UART010_CR);
0090 }
0091
0092 static void pl010_disable_ms(struct uart_port *port)
0093 {
0094     struct uart_amba_port *uap = (struct uart_amba_port *)port;
0095     unsigned int cr;
0096
0097     cr = readb(uap->port.membase + UART010_CR);
0098     cr &= ~UART010_CR_MSIE;
0099     writel(cr, uap->port.membase + UART010_CR);
0100 }
0101
0102 static void pl010_enable_ms(struct uart_port *port)
0103 {
0104     struct uart_amba_port *uap =
0105         container_of(port, struct uart_amba_port, port);
0106     unsigned int cr;
0107
0108     cr = readb(uap->port.membase + UART010_CR);
0109     cr |= UART010_CR_MSIE;
0110     writel(cr, uap->port.membase + UART010_CR);
0111 }
0112
0113 static void pl010_rx_chars(struct uart_port *port)
0114 {
0115     unsigned int status, ch, flag, rsr, max_count = 256;
0116
0117     status = readb(port->membase + UART01x_FR);
0118     while (UART_RX_DATA(status) && max_count--) {
0119         ch = readb(port->membase + UART01x_DR);
0120         flag = TTY_NORMAL;
0121
0122         port->icount.rx++;
0123
0124         /*
0125          * Note that the error handling code is
0126          * out of the main execution path
0127          */
0128         rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
0129         if (unlikely(rsr & UART01x_RSR_ANY)) {
0130             writel(0, port->membase + UART01x_ECR);
0131
0132             if (rsr & UART01x_RSR_BE) {
0133                 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
0134                 port->icount.brk++;
0135                 if (uart_handle_break(port))
0136                     goto ignore_char;
0137             } else if (rsr & UART01x_RSR_PE)
0138                 port->icount.parity++;
0139             else if (rsr & UART01x_RSR_FE)
0140                 port->icount.frame++;
0141             if (rsr & UART01x_RSR_OE)
0142                 port->icount.overrun++;
0143
0144             rsr &= port->read_status_mask;
0145
0146             if (rsr & UART01x_RSR_BE)
0147                 flag = TTY_BREAK;
0148             else if (rsr & UART01x_RSR_PE)
0149                 flag = TTY_PARITY;
0150             else if (rsr & UART01x_RSR_FE)
0151                 flag = TTY_FRAME;
0152         }
0153
0154         if (uart_handle_sysrq_char(port, ch))
0155             goto ignore_char;
0156
0157         uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
0158
0159     ignore_char:
0160         status = readb(port->membase + UART01x_FR);
0161     }
0162     tty_flip_buffer_push(&port->state->port);
0163 }
0164
0165 static void pl010_tx_chars(struct uart_port *port)
0166 {
0167     struct circ_buf *xmit = &port->state->xmit;
0168     int count;
0169
0170     if (port->x_char) {
0171         writel(port->x_char, port->membase + UART01x_DR);
0172         port->icount.tx++;
0173         port->x_char = 0;
0174         return;
0175     }
0176     if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
0177         pl010_stop_tx(port);
0178         return;
0179     }
0180
0181     count = port->fifosize >> 1;
0182     do {
0183         writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
0184         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
0185         port->icount.tx++;
0186         if (uart_circ_empty(xmit))
0187             break;
0188     } while (--count > 0);
0189
0190     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0191         uart_write_wakeup(port);
0192
0193     if (uart_circ_empty(xmit))
0194         pl010_stop_tx(port);
0195 }
0196
0197 static void pl010_modem_status(struct uart_amba_port *uap)
0198 {
0199     struct uart_port *port = &uap->port;
0200     unsigned int status, delta;
0201
0202     writel(0, port->membase + UART010_ICR);
0203
0204     status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
0205
0206     delta = status ^ uap->old_status;
0207     uap->old_status = status;
0208
0209     if (!delta)
0210         return;
0211
0212     if (delta & UART01x_FR_DCD)
0213         uart_handle_dcd_change(port, status & UART01x_FR_DCD);
0214
0215     if (delta & UART01x_FR_DSR)
0216         port->icount.dsr++;
0217
0218     if (delta & UART01x_FR_CTS)
0219         uart_handle_cts_change(port, status & UART01x_FR_CTS);
0220
0221     wake_up_interruptible(&port->state->port.delta_msr_wait);
0222 }
0223
0224 static irqreturn_t pl010_int(int irq, void *dev_id)
0225 {
0226     struct uart_amba_port *uap = dev_id;
0227     struct uart_port *port = &uap->port;
0228     unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
0229     int handled = 0;
0230
0231     spin_lock(&port->lock);
0232
0233     status = readb(port->membase + UART010_IIR);
0234     if (status) {
0235         do {
0236             if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
0237                 pl010_rx_chars(port);
0238             if (status & UART010_IIR_MIS)
0239                 pl010_modem_status(uap);
0240             if (status & UART010_IIR_TIS)
0241                 pl010_tx_chars(port);
0242
0243             if (pass_counter-- == 0)
0244                 break;
0245
0246             status = readb(port->membase + UART010_IIR);
0247         } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
0248                    UART010_IIR_TIS));
0249         handled = 1;
0250     }
0251
0252     spin_unlock(&port->lock);
0253
0254     return IRQ_RETVAL(handled);
0255 }
0256
0257 static unsigned int pl010_tx_empty(struct uart_port *port)
0258 {
0259     unsigned int status = readb(port->membase + UART01x_FR);
0260
0261     return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
0262 }
0263
0264 static unsigned int pl010_get_mctrl(struct uart_port *port)
0265 {
0266     unsigned int result = 0;
0267     unsigned int status;
0268
0269     status = readb(port->membase + UART01x_FR);
0270     if (status & UART01x_FR_DCD)
0271         result |= TIOCM_CAR;
0272     if (status & UART01x_FR_DSR)
0273         result |= TIOCM_DSR;
0274     if (status & UART01x_FR_CTS)
0275         result |= TIOCM_CTS;
0276
0277     return result;
0278 }
0279
0280 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
0281 {
0282     struct uart_amba_port *uap =
0283         container_of(port, struct uart_amba_port, port);
0284
0285     if (uap->data)
0286         uap->data->set_mctrl(uap->dev, port->membase, mctrl);
0287 }
0288
0289 static void pl010_break_ctl(struct uart_port *port, int break_state)
0290 {
0291     unsigned long flags;
0292     unsigned int lcr_h;
0293
0294     spin_lock_irqsave(&port->lock, flags);
0295     lcr_h = readb(port->membase + UART010_LCRH);
0296     if (break_state == -1)
0297         lcr_h |= UART01x_LCRH_BRK;
0298     else
0299         lcr_h &= ~UART01x_LCRH_BRK;
0300     writel(lcr_h, port->membase + UART010_LCRH);
0301     spin_unlock_irqrestore(&port->lock, flags);
0302 }
0303
0304 static int pl010_startup(struct uart_port *port)
0305 {
0306     struct uart_amba_port *uap =
0307         container_of(port, struct uart_amba_port, port);
0308     int retval;
0309
0310     /*
0311      * Try to enable the clock producer.
0312      */
0313     retval = clk_prepare_enable(uap->clk);
0314     if (retval)
0315         goto out;
0316
0317     port->uartclk = clk_get_rate(uap->clk);
0318
0319     /*
0320      * Allocate the IRQ
0321      */
0322     retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", uap);
0323     if (retval)
0324         goto clk_dis;
0325
0326     /*
0327      * initialise the old status of the modem signals
0328      */
0329     uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
0330
0331     /*
0332      * Finally, enable interrupts
0333      */
0334     writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
0335            port->membase + UART010_CR);
0336
0337     return 0;
0338
0339  clk_dis:
0340     clk_disable_unprepare(uap->clk);
0341  out:
0342     return retval;
0343 }
0344
0345 static void pl010_shutdown(struct uart_port *port)
0346 {
0347     struct uart_amba_port *uap =
0348         container_of(port, struct uart_amba_port, port);
0349
0350     /*
0351      * Free the interrupt
0352      */
0353     free_irq(port->irq, uap);
0354
0355     /*
0356      * disable all interrupts, disable the port
0357      */
0358     writel(0, port->membase + UART010_CR);
0359
0360     /* disable break condition and fifos */
0361     writel(readb(port->membase + UART010_LCRH) &
0362         ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
0363            port->membase + UART010_LCRH);
0364
0365     /*
0366      * Shut down the clock producer
0367      */
0368     clk_disable_unprepare(uap->clk);
0369 }
0370
0371 static void
0372 pl010_set_termios(struct uart_port *port, struct ktermios *termios,
0373              struct ktermios *old)
0374 {
0375     unsigned int lcr_h, old_cr;
0376     unsigned long flags;
0377     unsigned int baud, quot;
0378
0379     /*
0380      * Ask the core to calculate the divisor for us.
0381      */
0382     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
0383     quot = uart_get_divisor(port, baud);
0384
0385     switch (termios->c_cflag & CSIZE) {
0386     case CS5:
0387         lcr_h = UART01x_LCRH_WLEN_5;
0388         break;
0389     case CS6:
0390         lcr_h = UART01x_LCRH_WLEN_6;
0391         break;
0392     case CS7:
0393         lcr_h = UART01x_LCRH_WLEN_7;
0394         break;
0395     default: // CS8
0396         lcr_h = UART01x_LCRH_WLEN_8;
0397         break;
0398     }
0399     if (termios->c_cflag & CSTOPB)
0400         lcr_h |= UART01x_LCRH_STP2;
0401     if (termios->c_cflag & PARENB) {
0402         lcr_h |= UART01x_LCRH_PEN;
0403         if (!(termios->c_cflag & PARODD))
0404             lcr_h |= UART01x_LCRH_EPS;
0405     }
0406     if (port->fifosize > 1)
0407         lcr_h |= UART01x_LCRH_FEN;
0408
0409     spin_lock_irqsave(&port->lock, flags);
0410
0411     /*
0412      * Update the per-port timeout.
0413      */
0414     uart_update_timeout(port, termios->c_cflag, baud);
0415
0416     port->read_status_mask = UART01x_RSR_OE;
0417     if (termios->c_iflag & INPCK)
0418         port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
0419     if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
0420         port->read_status_mask |= UART01x_RSR_BE;
0421
0422     /*
0423      * Characters to ignore
0424      */
0425     port->ignore_status_mask = 0;
0426     if (termios->c_iflag & IGNPAR)
0427         port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
0428     if (termios->c_iflag & IGNBRK) {
0429         port->ignore_status_mask |= UART01x_RSR_BE;
0430         /*
0431          * If we're ignoring parity and break indicators,
0432          * ignore overruns too (for real raw support).
0433          */
0434         if (termios->c_iflag & IGNPAR)
0435             port->ignore_status_mask |= UART01x_RSR_OE;
0436     }
0437
0438     /*
0439      * Ignore all characters if CREAD is not set.
0440      */
0441     if ((termios->c_cflag & CREAD) == 0)
0442         port->ignore_status_mask |= UART_DUMMY_RSR_RX;
0443
0444     old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
0445
0446     if (UART_ENABLE_MS(port, termios->c_cflag))
0447         old_cr |= UART010_CR_MSIE;
0448
0449     /* Set baud rate */
0450     quot -= 1;
0451     writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
0452     writel(quot & 0xff, port->membase + UART010_LCRL);
0453
0454     /*
0455      * ----------v----------v----------v----------v-----
0456      * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
0457      * ----------^----------^----------^----------^-----
0458      */
0459     writel(lcr_h, port->membase + UART010_LCRH);
0460     writel(old_cr, port->membase + UART010_CR);
0461
0462     spin_unlock_irqrestore(&port->lock, flags);
0463 }
0464
0465 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
0466 {
0467     if (termios->c_line == N_PPS) {
0468         port->flags |= UPF_HARDPPS_CD;
0469         spin_lock_irq(&port->lock);
0470         pl010_enable_ms(port);
0471         spin_unlock_irq(&port->lock);
0472     } else {
0473         port->flags &= ~UPF_HARDPPS_CD;
0474         if (!UART_ENABLE_MS(port, termios->c_cflag)) {
0475             spin_lock_irq(&port->lock);
0476             pl010_disable_ms(port);
0477             spin_unlock_irq(&port->lock);
0478         }
0479     }
0480 }
0481
0482 static const char *pl010_type(struct uart_port *port)
0483 {
0484     return port->type == PORT_AMBA ? "AMBA" : NULL;
0485 }
0486
0487 /*
0488  * Release the memory region(s) being used by 'port'
0489  */
0490 static void pl010_release_port(struct uart_port *port)
0491 {
0492     release_mem_region(port->mapbase, UART_PORT_SIZE);
0493 }
0494
0495 /*
0496  * Request the memory region(s) being used by 'port'
0497  */
0498 static int pl010_request_port(struct uart_port *port)
0499 {
0500     return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
0501             != NULL ? 0 : -EBUSY;
0502 }
0503
0504 /*
0505  * Configure/autoconfigure the port.
0506  */
0507 static void pl010_config_port(struct uart_port *port, int flags)
0508 {
0509     if (flags & UART_CONFIG_TYPE) {
0510         port->type = PORT_AMBA;
0511         pl010_request_port(port);
0512     }
0513 }
0514
0515 /*
0516  * verify the new serial_struct (for TIOCSSERIAL).
0517  */
0518 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
0519 {
0520     int ret = 0;
0521     if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
0522         ret = -EINVAL;
0523     if (ser->irq < 0 || ser->irq >= nr_irqs)
0524         ret = -EINVAL;
0525     if (ser->baud_base < 9600)
0526         ret = -EINVAL;
0527     return ret;
0528 }
0529
0530 static const struct uart_ops amba_pl010_pops = {
0531     .tx_empty   = pl010_tx_empty,
0532     .set_mctrl  = pl010_set_mctrl,
0533     .get_mctrl  = pl010_get_mctrl,
0534     .stop_tx    = pl010_stop_tx,
0535     .start_tx   = pl010_start_tx,
0536     .stop_rx    = pl010_stop_rx,
0537     .enable_ms  = pl010_enable_ms,
0538     .break_ctl  = pl010_break_ctl,
0539     .startup    = pl010_startup,
0540     .shutdown   = pl010_shutdown,
0541     .set_termios    = pl010_set_termios,
0542     .set_ldisc  = pl010_set_ldisc,
0543     .type       = pl010_type,
0544     .release_port   = pl010_release_port,
0545     .request_port   = pl010_request_port,
0546     .config_port    = pl010_config_port,
0547     .verify_port    = pl010_verify_port,
0548 };
0549
0550 static struct uart_amba_port *amba_ports[UART_NR];
0551
0552 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
0553
0554 static void pl010_console_putchar(struct uart_port *port, unsigned char ch)
0555 {
0556     unsigned int status;
0557
0558     do {
0559         status = readb(port->membase + UART01x_FR);
0560         barrier();
0561     } while (!UART_TX_READY(status));
0562     writel(ch, port->membase + UART01x_DR);
0563 }
0564
0565 static void
0566 pl010_console_write(struct console *co, const char *s, unsigned int count)
0567 {
0568     struct uart_amba_port *uap = amba_ports[co->index];
0569     struct uart_port *port = &uap->port;
0570     unsigned int status, old_cr;
0571
0572     clk_enable(uap->clk);
0573
0574     /*
0575      *  First save the CR then disable the interrupts
0576      */
0577     old_cr = readb(port->membase + UART010_CR);
0578     writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
0579
0580     uart_console_write(port, s, count, pl010_console_putchar);
0581
0582     /*
0583      *  Finally, wait for transmitter to become empty
0584      *  and restore the TCR
0585      */
0586     do {
0587         status = readb(port->membase + UART01x_FR);
0588         barrier();
0589     } while (status & UART01x_FR_BUSY);
0590     writel(old_cr, port->membase + UART010_CR);
0591
0592     clk_disable(uap->clk);
0593 }
0594
0595 static void __init
0596 pl010_console_get_options(struct uart_amba_port *uap, int *baud,
0597                  int *parity, int *bits)
0598 {
0599     if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
0600         unsigned int lcr_h, quot;
0601         lcr_h = readb(uap->port.membase + UART010_LCRH);
0602
0603         *parity = 'n';
0604         if (lcr_h & UART01x_LCRH_PEN) {
0605             if (lcr_h & UART01x_LCRH_EPS)
0606                 *parity = 'e';
0607             else
0608                 *parity = 'o';
0609         }
0610
0611         if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
0612             *bits = 7;
0613         else
0614             *bits = 8;
0615
0616         quot = readb(uap->port.membase + UART010_LCRL) |
0617                readb(uap->port.membase + UART010_LCRM) << 8;
0618         *baud = uap->port.uartclk / (16 * (quot + 1));
0619     }
0620 }
0621
0622 static int __init pl010_console_setup(struct console *co, char *options)
0623 {
0624     struct uart_amba_port *uap;
0625     int baud = 38400;
0626     int bits = 8;
0627     int parity = 'n';
0628     int flow = 'n';
0629     int ret;
0630
0631     /*
0632      * Check whether an invalid uart number has been specified, and
0633      * if so, search for the first available port that does have
0634      * console support.
0635      */
0636     if (co->index >= UART_NR)
0637         co->index = 0;
0638     uap = amba_ports[co->index];
0639     if (!uap)
0640         return -ENODEV;
0641
0642     ret = clk_prepare(uap->clk);
0643     if (ret)
0644         return ret;
0645
0646     uap->port.uartclk = clk_get_rate(uap->clk);
0647
0648     if (options)
0649         uart_parse_options(options, &baud, &parity, &bits, &flow);
0650     else
0651         pl010_console_get_options(uap, &baud, &parity, &bits);
0652
0653     return uart_set_options(&uap->port, co, baud, parity, bits, flow);
0654 }
0655
0656 static struct uart_driver amba_reg;
0657 static struct console amba_console = {
0658     .name       = "ttyAM",
0659     .write      = pl010_console_write,
0660     .device     = uart_console_device,
0661     .setup      = pl010_console_setup,
0662     .flags      = CON_PRINTBUFFER,
0663     .index      = -1,
0664     .data       = &amba_reg,
0665 };
0666
0667 #define AMBA_CONSOLE    &amba_console
0668 #else
0669 #define AMBA_CONSOLE    NULL
0670 #endif
0671
0672 static DEFINE_MUTEX(amba_reg_lock);
0673 static struct uart_driver amba_reg = {
0674     .owner          = THIS_MODULE,
0675     .driver_name        = "ttyAM",
0676     .dev_name       = "ttyAM",
0677     .major          = SERIAL_AMBA_MAJOR,
0678     .minor          = SERIAL_AMBA_MINOR,
0679     .nr         = UART_NR,
0680     .cons           = AMBA_CONSOLE,
0681 };
0682
0683 static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
0684 {
0685     struct uart_amba_port *uap;
0686     void __iomem *base;
0687     int i, ret;
0688
0689     for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
0690         if (amba_ports[i] == NULL)
0691             break;
0692
0693     if (i == ARRAY_SIZE(amba_ports))
0694         return -EBUSY;
0695
0696     uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
0697                GFP_KERNEL);
0698     if (!uap)
0699         return -ENOMEM;
0700
0701     base = devm_ioremap(&dev->dev, dev->res.start,
0702                 resource_size(&dev->res));
0703     if (!base)
0704         return -ENOMEM;
0705
0706     uap->clk = devm_clk_get(&dev->dev, NULL);
0707     if (IS_ERR(uap->clk))
0708         return PTR_ERR(uap->clk);
0709
0710     uap->port.dev = &dev->dev;
0711     uap->port.mapbase = dev->res.start;
0712     uap->port.membase = base;
0713     uap->port.iotype = UPIO_MEM;
0714     uap->port.irq = dev->irq[0];
0715     uap->port.fifosize = 16;
0716     uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL010_CONSOLE);
0717     uap->port.ops = &amba_pl010_pops;
0718     uap->port.flags = UPF_BOOT_AUTOCONF;
0719     uap->port.line = i;
0720     uap->dev = dev;
0721     uap->data = dev_get_platdata(&dev->dev);
0722
0723     amba_ports[i] = uap;
0724
0725     amba_set_drvdata(dev, uap);
0726
0727     mutex_lock(&amba_reg_lock);
0728     if (!amba_reg.state) {
0729         ret = uart_register_driver(&amba_reg);
0730         if (ret < 0) {
0731             mutex_unlock(&amba_reg_lock);
0732             dev_err(uap->port.dev,
0733                 "Failed to register AMBA-PL010 driver\n");
0734             return ret;
0735         }
0736     }
0737     mutex_unlock(&amba_reg_lock);
0738
0739     ret = uart_add_one_port(&amba_reg, &uap->port);
0740     if (ret)
0741         amba_ports[i] = NULL;
0742
0743     return ret;
0744 }
0745
0746 static void pl010_remove(struct amba_device *dev)
0747 {
0748     struct uart_amba_port *uap = amba_get_drvdata(dev);
0749     int i;
0750     bool busy = false;
0751
0752     uart_remove_one_port(&amba_reg, &uap->port);
0753
0754     for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
0755         if (amba_ports[i] == uap)
0756             amba_ports[i] = NULL;
0757         else if (amba_ports[i])
0758             busy = true;
0759
0760     if (!busy)
0761         uart_unregister_driver(&amba_reg);
0762 }
0763
0764 #ifdef CONFIG_PM_SLEEP
0765 static int pl010_suspend(struct device *dev)
0766 {
0767     struct uart_amba_port *uap = dev_get_drvdata(dev);
0768
0769     if (uap)
0770         uart_suspend_port(&amba_reg, &uap->port);
0771
0772     return 0;
0773 }
0774
0775 static int pl010_resume(struct device *dev)
0776 {
0777     struct uart_amba_port *uap = dev_get_drvdata(dev);
0778
0779     if (uap)
0780         uart_resume_port(&amba_reg, &uap->port);
0781
0782     return 0;
0783 }
0784 #endif
0785
0786 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume);
0787
0788 static const struct amba_id pl010_ids[] = {
0789     {
0790         .id = 0x00041010,
0791         .mask   = 0x000fffff,
0792     },
0793     { 0, 0 },
0794 };
0795
0796 MODULE_DEVICE_TABLE(amba, pl010_ids);
0797
0798 static struct amba_driver pl010_driver = {
0799     .drv = {
0800         .name   = "uart-pl010",
0801         .pm = &pl010_dev_pm_ops,
0802     },
0803     .id_table   = pl010_ids,
0804     .probe      = pl010_probe,
0805     .remove     = pl010_remove,
0806 };
0807
0808 static int __init pl010_init(void)
0809 {
0810     printk(KERN_INFO "Serial: AMBA driver\n");
0811
0812     return  amba_driver_register(&pl010_driver);
0813 }
0814
0815 static void __exit pl010_exit(void)
0816 {
0817     amba_driver_unregister(&pl010_driver);
0818 }
0819
0820 module_init(pl010_init);
0821 module_exit(pl010_exit);
0822
0823 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
0824 MODULE_DESCRIPTION("ARM AMBA serial port driver");
0825 MODULE_LICENSE("GPL");