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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * 8250-core based driver for the OMAP internal UART
0004  *
0005  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
0006  *
0007  * Copyright (C) 2014 Sebastian Andrzej Siewior
0008  *
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/device.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/serial_8250.h>
0016 #include <linux/serial_reg.h>
0017 #include <linux/tty_flip.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/slab.h>
0020 #include <linux/of.h>
0021 #include <linux/of_device.h>
0022 #include <linux/of_gpio.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/delay.h>
0025 #include <linux/pm_runtime.h>
0026 #include <linux/console.h>
0027 #include <linux/pm_qos.h>
0028 #include <linux/pm_wakeirq.h>
0029 #include <linux/dma-mapping.h>
0030 #include <linux/sys_soc.h>
0031 
0032 #include "8250.h"
0033 
0034 #define DEFAULT_CLK_SPEED   48000000
0035 
0036 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
0037 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
0038 #define OMAP_DMA_TX_KICK        (1 << 2)
0039 /*
0040  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
0041  * The same errata is applicable to AM335x and DRA7x processors too.
0042  */
0043 #define UART_ERRATA_CLOCK_DISABLE   (1 << 3)
0044 #define UART_HAS_EFR2           BIT(4)
0045 #define UART_HAS_RHR_IT_DIS     BIT(5)
0046 #define UART_RX_TIMEOUT_QUIRK       BIT(6)
0047 
0048 #define OMAP_UART_FCR_RX_TRIG       6
0049 #define OMAP_UART_FCR_TX_TRIG       4
0050 
0051 /* SCR register bitmasks */
0052 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK   (1 << 7)
0053 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK   (1 << 6)
0054 #define OMAP_UART_SCR_TX_EMPTY          (1 << 3)
0055 #define OMAP_UART_SCR_DMAMODE_MASK      (3 << 1)
0056 #define OMAP_UART_SCR_DMAMODE_1         (1 << 1)
0057 #define OMAP_UART_SCR_DMAMODE_CTL       (1 << 0)
0058 
0059 /* MVR register bitmasks */
0060 #define OMAP_UART_MVR_SCHEME_SHIFT  30
0061 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
0062 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
0063 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
0064 #define OMAP_UART_MVR_MAJ_MASK      0x700
0065 #define OMAP_UART_MVR_MAJ_SHIFT     8
0066 #define OMAP_UART_MVR_MIN_MASK      0x3f
0067 
0068 /* SYSC register bitmasks */
0069 #define OMAP_UART_SYSC_SOFTRESET    (1 << 1)
0070 
0071 /* SYSS register bitmasks */
0072 #define OMAP_UART_SYSS_RESETDONE    (1 << 0)
0073 
0074 #define UART_TI752_TLR_TX   0
0075 #define UART_TI752_TLR_RX   4
0076 
0077 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
0078 #define TRIGGER_FCR_MASK(x) (x & 3)
0079 
0080 /* Enable XON/XOFF flow control on output */
0081 #define OMAP_UART_SW_TX     0x08
0082 /* Enable XON/XOFF flow control on input */
0083 #define OMAP_UART_SW_RX     0x02
0084 
0085 #define OMAP_UART_WER_MOD_WKUP  0x7f
0086 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
0087 
0088 #define TX_TRIGGER  1
0089 #define RX_TRIGGER  48
0090 
0091 #define OMAP_UART_TCR_RESTORE(x)    ((x / 4) << 4)
0092 #define OMAP_UART_TCR_HALT(x)       ((x / 4) << 0)
0093 
0094 #define UART_BUILD_REVISION(x, y)   (((x) << 8) | (y))
0095 
0096 #define OMAP_UART_REV_46 0x0406
0097 #define OMAP_UART_REV_52 0x0502
0098 #define OMAP_UART_REV_63 0x0603
0099 
0100 /* Interrupt Enable Register 2 */
0101 #define UART_OMAP_IER2          0x1B
0102 #define UART_OMAP_IER2_RHR_IT_DIS   BIT(2)
0103 
0104 /* Enhanced features register 2 */
0105 #define UART_OMAP_EFR2          0x23
0106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE   BIT(6)
0107 
0108 /* RX FIFO occupancy indicator */
0109 #define UART_OMAP_RX_LVL        0x19
0110 
0111 struct omap8250_priv {
0112     int line;
0113     u8 habit;
0114     u8 mdr1;
0115     u8 efr;
0116     u8 scr;
0117     u8 wer;
0118     u8 xon;
0119     u8 xoff;
0120     u8 delayed_restore;
0121     u16 quot;
0122 
0123     u8 tx_trigger;
0124     u8 rx_trigger;
0125     bool is_suspending;
0126     int wakeirq;
0127     int wakeups_enabled;
0128     u32 latency;
0129     u32 calc_latency;
0130     struct pm_qos_request pm_qos_request;
0131     struct work_struct qos_work;
0132     struct uart_8250_dma omap8250_dma;
0133     spinlock_t rx_dma_lock;
0134     bool rx_dma_broken;
0135     bool throttled;
0136 };
0137 
0138 struct omap8250_dma_params {
0139     u32 rx_size;
0140     u8 rx_trigger;
0141     u8 tx_trigger;
0142 };
0143 
0144 struct omap8250_platdata {
0145     struct omap8250_dma_params *dma_params;
0146     u8 habit;
0147 };
0148 
0149 #ifdef CONFIG_SERIAL_8250_DMA
0150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
0151 #else
0152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
0153 #endif
0154 
0155 static u32 uart_read(struct uart_8250_port *up, u32 reg)
0156 {
0157     return readl(up->port.membase + (reg << up->port.regshift));
0158 }
0159 
0160 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
0161 {
0162     struct uart_8250_port *up = up_to_u8250p(port);
0163     struct omap8250_priv *priv = up->port.private_data;
0164     u8 lcr;
0165 
0166     serial8250_do_set_mctrl(port, mctrl);
0167 
0168     if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
0169         /*
0170          * Turn off autoRTS if RTS is lowered and restore autoRTS
0171          * setting if RTS is raised
0172          */
0173         lcr = serial_in(up, UART_LCR);
0174         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0175         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
0176             priv->efr |= UART_EFR_RTS;
0177         else
0178             priv->efr &= ~UART_EFR_RTS;
0179         serial_out(up, UART_EFR, priv->efr);
0180         serial_out(up, UART_LCR, lcr);
0181     }
0182 }
0183 
0184 /*
0185  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
0186  * The access to uart register after MDR1 Access
0187  * causes UART to corrupt data.
0188  *
0189  * Need a delay =
0190  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
0191  * give 10 times as much
0192  */
0193 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
0194                      struct omap8250_priv *priv)
0195 {
0196     u8 timeout = 255;
0197 
0198     serial_out(up, UART_OMAP_MDR1, priv->mdr1);
0199     udelay(2);
0200     serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
0201             UART_FCR_CLEAR_RCVR);
0202     /*
0203      * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
0204      * TX_FIFO_E bit is 1.
0205      */
0206     while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
0207                 (UART_LSR_THRE | UART_LSR_DR))) {
0208         timeout--;
0209         if (!timeout) {
0210             /* Should *never* happen. we warn and carry on */
0211             dev_crit(up->port.dev, "Errata i202: timedout %x\n",
0212                  serial_in(up, UART_LSR));
0213             break;
0214         }
0215         udelay(1);
0216     }
0217 }
0218 
0219 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
0220                   struct omap8250_priv *priv)
0221 {
0222     unsigned int uartclk = port->uartclk;
0223     unsigned int div_13, div_16;
0224     unsigned int abs_d13, abs_d16;
0225 
0226     /*
0227      * Old custom speed handling.
0228      */
0229     if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
0230         priv->quot = port->custom_divisor & UART_DIV_MAX;
0231         /*
0232          * I assume that nobody is using this. But hey, if somebody
0233          * would like to specify the divisor _and_ the mode then the
0234          * driver is ready and waiting for it.
0235          */
0236         if (port->custom_divisor & (1 << 16))
0237             priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
0238         else
0239             priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
0240         return;
0241     }
0242     div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
0243     div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
0244 
0245     if (!div_13)
0246         div_13 = 1;
0247     if (!div_16)
0248         div_16 = 1;
0249 
0250     abs_d13 = abs(baud - uartclk / 13 / div_13);
0251     abs_d16 = abs(baud - uartclk / 16 / div_16);
0252 
0253     if (abs_d13 >= abs_d16) {
0254         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
0255         priv->quot = div_16;
0256     } else {
0257         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
0258         priv->quot = div_13;
0259     }
0260 }
0261 
0262 static void omap8250_update_scr(struct uart_8250_port *up,
0263                 struct omap8250_priv *priv)
0264 {
0265     u8 old_scr;
0266 
0267     old_scr = serial_in(up, UART_OMAP_SCR);
0268     if (old_scr == priv->scr)
0269         return;
0270 
0271     /*
0272      * The manual recommends not to enable the DMA mode selector in the SCR
0273      * (instead of the FCR) register _and_ selecting the DMA mode as one
0274      * register write because this may lead to malfunction.
0275      */
0276     if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
0277         serial_out(up, UART_OMAP_SCR,
0278                priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
0279     serial_out(up, UART_OMAP_SCR, priv->scr);
0280 }
0281 
0282 static void omap8250_update_mdr1(struct uart_8250_port *up,
0283                  struct omap8250_priv *priv)
0284 {
0285     if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
0286         omap_8250_mdr1_errataset(up, priv);
0287     else
0288         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
0289 }
0290 
0291 static void omap8250_restore_regs(struct uart_8250_port *up)
0292 {
0293     struct omap8250_priv *priv = up->port.private_data;
0294     struct uart_8250_dma    *dma = up->dma;
0295 
0296     if (dma && dma->tx_running) {
0297         /*
0298          * TCSANOW requests the change to occur immediately however if
0299          * we have a TX-DMA operation in progress then it has been
0300          * observed that it might stall and never complete. Therefore we
0301          * delay DMA completes to prevent this hang from happen.
0302          */
0303         priv->delayed_restore = 1;
0304         return;
0305     }
0306 
0307     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0308     serial_out(up, UART_EFR, UART_EFR_ECB);
0309 
0310     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
0311     serial8250_out_MCR(up, UART_MCR_TCRTLR);
0312     serial_out(up, UART_FCR, up->fcr);
0313 
0314     omap8250_update_scr(up, priv);
0315 
0316     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0317 
0318     serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
0319             OMAP_UART_TCR_HALT(52));
0320     serial_out(up, UART_TI752_TLR,
0321            TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
0322            TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
0323 
0324     serial_out(up, UART_LCR, 0);
0325 
0326     /* drop TCR + TLR access, we setup XON/XOFF later */
0327     serial8250_out_MCR(up, up->mcr);
0328     serial_out(up, UART_IER, up->ier);
0329 
0330     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0331     serial_dl_write(up, priv->quot);
0332 
0333     serial_out(up, UART_EFR, priv->efr);
0334 
0335     /* Configure flow control */
0336     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0337     serial_out(up, UART_XON1, priv->xon);
0338     serial_out(up, UART_XOFF1, priv->xoff);
0339 
0340     serial_out(up, UART_LCR, up->lcr);
0341 
0342     omap8250_update_mdr1(up, priv);
0343 
0344     up->port.ops->set_mctrl(&up->port, up->port.mctrl);
0345 }
0346 
0347 /*
0348  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
0349  * some differences in how we want to handle flow control.
0350  */
0351 static void omap_8250_set_termios(struct uart_port *port,
0352                   struct ktermios *termios,
0353                   struct ktermios *old)
0354 {
0355     struct uart_8250_port *up = up_to_u8250p(port);
0356     struct omap8250_priv *priv = up->port.private_data;
0357     unsigned char cval = 0;
0358     unsigned int baud;
0359 
0360     cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
0361 
0362     if (termios->c_cflag & CSTOPB)
0363         cval |= UART_LCR_STOP;
0364     if (termios->c_cflag & PARENB)
0365         cval |= UART_LCR_PARITY;
0366     if (!(termios->c_cflag & PARODD))
0367         cval |= UART_LCR_EPAR;
0368     if (termios->c_cflag & CMSPAR)
0369         cval |= UART_LCR_SPAR;
0370 
0371     /*
0372      * Ask the core to calculate the divisor for us.
0373      */
0374     baud = uart_get_baud_rate(port, termios, old,
0375                   port->uartclk / 16 / UART_DIV_MAX,
0376                   port->uartclk / 13);
0377     omap_8250_get_divisor(port, baud, priv);
0378 
0379     /*
0380      * Ok, we're now changing the port state. Do it with
0381      * interrupts disabled.
0382      */
0383     pm_runtime_get_sync(port->dev);
0384     spin_lock_irq(&port->lock);
0385 
0386     /*
0387      * Update the per-port timeout.
0388      */
0389     uart_update_timeout(port, termios->c_cflag, baud);
0390 
0391     up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
0392     if (termios->c_iflag & INPCK)
0393         up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
0394     if (termios->c_iflag & (IGNBRK | PARMRK))
0395         up->port.read_status_mask |= UART_LSR_BI;
0396 
0397     /*
0398      * Characters to ignore
0399      */
0400     up->port.ignore_status_mask = 0;
0401     if (termios->c_iflag & IGNPAR)
0402         up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
0403     if (termios->c_iflag & IGNBRK) {
0404         up->port.ignore_status_mask |= UART_LSR_BI;
0405         /*
0406          * If we're ignoring parity and break indicators,
0407          * ignore overruns too (for real raw support).
0408          */
0409         if (termios->c_iflag & IGNPAR)
0410             up->port.ignore_status_mask |= UART_LSR_OE;
0411     }
0412 
0413     /*
0414      * ignore all characters if CREAD is not set
0415      */
0416     if ((termios->c_cflag & CREAD) == 0)
0417         up->port.ignore_status_mask |= UART_LSR_DR;
0418 
0419     /*
0420      * Modem status interrupts
0421      */
0422     up->ier &= ~UART_IER_MSI;
0423     if (UART_ENABLE_MS(&up->port, termios->c_cflag))
0424         up->ier |= UART_IER_MSI;
0425 
0426     up->lcr = cval;
0427     /* Up to here it was mostly serial8250_do_set_termios() */
0428 
0429     /*
0430      * We enable TRIG_GRANU for RX and TX and additionally we set
0431      * SCR_TX_EMPTY bit. The result is the following:
0432      * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
0433      * - less than RX_TRIGGER number of bytes will also cause an interrupt
0434      *   once the UART decides that there no new bytes arriving.
0435      * - Once THRE is enabled, the interrupt will be fired once the FIFO is
0436      *   empty - the trigger level is ignored here.
0437      *
0438      * Once DMA is enabled:
0439      * - UART will assert the TX DMA line once there is room for TX_TRIGGER
0440      *   bytes in the TX FIFO. On each assert the DMA engine will move
0441      *   TX_TRIGGER bytes into the FIFO.
0442      * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
0443      *   the FIFO and move RX_TRIGGER bytes.
0444      * This is because threshold and trigger values are the same.
0445      */
0446     up->fcr = UART_FCR_ENABLE_FIFO;
0447     up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
0448     up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
0449 
0450     priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
0451         OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
0452 
0453     if (up->dma)
0454         priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
0455             OMAP_UART_SCR_DMAMODE_CTL;
0456 
0457     priv->xon = termios->c_cc[VSTART];
0458     priv->xoff = termios->c_cc[VSTOP];
0459 
0460     priv->efr = 0;
0461     up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
0462 
0463     if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
0464         !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
0465         !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
0466         /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
0467         up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
0468         priv->efr |= UART_EFR_CTS;
0469     } else  if (up->port.flags & UPF_SOFT_FLOW) {
0470         /*
0471          * OMAP rx s/w flow control is borked; the transmitter remains
0472          * stuck off even if rx flow control is subsequently disabled
0473          */
0474 
0475         /*
0476          * IXOFF Flag:
0477          * Enable XON/XOFF flow control on output.
0478          * Transmit XON1, XOFF1
0479          */
0480         if (termios->c_iflag & IXOFF) {
0481             up->port.status |= UPSTAT_AUTOXOFF;
0482             priv->efr |= OMAP_UART_SW_TX;
0483         }
0484     }
0485     omap8250_restore_regs(up);
0486 
0487     spin_unlock_irq(&up->port.lock);
0488     pm_runtime_mark_last_busy(port->dev);
0489     pm_runtime_put_autosuspend(port->dev);
0490 
0491     /* calculate wakeup latency constraint */
0492     priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
0493     priv->latency = priv->calc_latency;
0494 
0495     schedule_work(&priv->qos_work);
0496 
0497     /* Don't rewrite B0 */
0498     if (tty_termios_baud_rate(termios))
0499         tty_termios_encode_baud_rate(termios, baud, baud);
0500 }
0501 
0502 /* same as 8250 except that we may have extra flow bits set in EFR */
0503 static void omap_8250_pm(struct uart_port *port, unsigned int state,
0504              unsigned int oldstate)
0505 {
0506     struct uart_8250_port *up = up_to_u8250p(port);
0507     u8 efr;
0508 
0509     pm_runtime_get_sync(port->dev);
0510     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0511     efr = serial_in(up, UART_EFR);
0512     serial_out(up, UART_EFR, efr | UART_EFR_ECB);
0513     serial_out(up, UART_LCR, 0);
0514 
0515     serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
0516     serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
0517     serial_out(up, UART_EFR, efr);
0518     serial_out(up, UART_LCR, 0);
0519 
0520     pm_runtime_mark_last_busy(port->dev);
0521     pm_runtime_put_autosuspend(port->dev);
0522 }
0523 
0524 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
0525                           struct omap8250_priv *priv)
0526 {
0527     static const struct soc_device_attribute k3_soc_devices[] = {
0528         { .family = "AM65X",  },
0529         { .family = "J721E", .revision = "SR1.0" },
0530         { /* sentinel */ }
0531     };
0532     u32 mvr, scheme;
0533     u16 revision, major, minor;
0534 
0535     mvr = uart_read(up, UART_OMAP_MVER);
0536 
0537     /* Check revision register scheme */
0538     scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
0539 
0540     switch (scheme) {
0541     case 0: /* Legacy Scheme: OMAP2/3 */
0542         /* MINOR_REV[0:4], MAJOR_REV[4:7] */
0543         major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
0544             OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
0545         minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
0546         break;
0547     case 1:
0548         /* New Scheme: OMAP4+ */
0549         /* MINOR_REV[0:5], MAJOR_REV[8:10] */
0550         major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
0551             OMAP_UART_MVR_MAJ_SHIFT;
0552         minor = (mvr & OMAP_UART_MVR_MIN_MASK);
0553         break;
0554     default:
0555         dev_warn(up->port.dev,
0556              "Unknown revision, defaulting to highest\n");
0557         /* highest possible revision */
0558         major = 0xff;
0559         minor = 0xff;
0560     }
0561     /* normalize revision for the driver */
0562     revision = UART_BUILD_REVISION(major, minor);
0563 
0564     switch (revision) {
0565     case OMAP_UART_REV_46:
0566         priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
0567         break;
0568     case OMAP_UART_REV_52:
0569         priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
0570                 OMAP_UART_WER_HAS_TX_WAKEUP;
0571         break;
0572     case OMAP_UART_REV_63:
0573         priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
0574             OMAP_UART_WER_HAS_TX_WAKEUP;
0575         break;
0576     default:
0577         break;
0578     }
0579 
0580     /*
0581      * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
0582      * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
0583      * to enable errata workaround.
0584      */
0585     if (soc_device_match(k3_soc_devices))
0586         priv->habit &= ~UART_HAS_RHR_IT_DIS;
0587 }
0588 
0589 static void omap8250_uart_qos_work(struct work_struct *work)
0590 {
0591     struct omap8250_priv *priv;
0592 
0593     priv = container_of(work, struct omap8250_priv, qos_work);
0594     cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
0595 }
0596 
0597 #ifdef CONFIG_SERIAL_8250_DMA
0598 static int omap_8250_dma_handle_irq(struct uart_port *port);
0599 #endif
0600 
0601 static irqreturn_t omap8250_irq(int irq, void *dev_id)
0602 {
0603     struct uart_port *port = dev_id;
0604     struct omap8250_priv *priv = port->private_data;
0605     struct uart_8250_port *up = up_to_u8250p(port);
0606     unsigned int iir, lsr;
0607     int ret;
0608 
0609 #ifdef CONFIG_SERIAL_8250_DMA
0610     if (up->dma) {
0611         ret = omap_8250_dma_handle_irq(port);
0612         return IRQ_RETVAL(ret);
0613     }
0614 #endif
0615 
0616     serial8250_rpm_get(up);
0617     lsr = serial_port_in(port, UART_LSR);
0618     iir = serial_port_in(port, UART_IIR);
0619     ret = serial8250_handle_irq(port, iir);
0620 
0621     /*
0622      * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
0623      * FIFO has been drained, in which case a dummy read of RX FIFO
0624      * is required to clear RX TIMEOUT condition.
0625      */
0626     if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
0627         (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
0628         serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
0629         serial_port_in(port, UART_RX);
0630     }
0631 
0632     /* Stop processing interrupts on input overrun */
0633     if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
0634         unsigned long delay;
0635 
0636         up->ier = port->serial_in(port, UART_IER);
0637         if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
0638             port->ops->stop_rx(port);
0639         } else {
0640             /* Keep restarting the timer until
0641              * the input overrun subsides.
0642              */
0643             cancel_delayed_work(&up->overrun_backoff);
0644         }
0645 
0646         delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
0647         schedule_delayed_work(&up->overrun_backoff, delay);
0648     }
0649 
0650     serial8250_rpm_put(up);
0651 
0652     return IRQ_RETVAL(ret);
0653 }
0654 
0655 static int omap_8250_startup(struct uart_port *port)
0656 {
0657     struct uart_8250_port *up = up_to_u8250p(port);
0658     struct omap8250_priv *priv = port->private_data;
0659     int ret;
0660 
0661     if (priv->wakeirq) {
0662         ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
0663         if (ret)
0664             return ret;
0665     }
0666 
0667     pm_runtime_get_sync(port->dev);
0668 
0669     up->mcr = 0;
0670     serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0671 
0672     serial_out(up, UART_LCR, UART_LCR_WLEN8);
0673 
0674     up->lsr_saved_flags = 0;
0675     up->msr_saved_flags = 0;
0676 
0677     /* Disable DMA for console UART */
0678     if (uart_console(port))
0679         up->dma = NULL;
0680 
0681     if (up->dma) {
0682         ret = serial8250_request_dma(up);
0683         if (ret) {
0684             dev_warn_ratelimited(port->dev,
0685                          "failed to request DMA\n");
0686             up->dma = NULL;
0687         }
0688     }
0689 
0690     ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
0691               dev_name(port->dev), port);
0692     if (ret < 0)
0693         goto err;
0694 
0695     up->ier = UART_IER_RLSI | UART_IER_RDI;
0696     serial_out(up, UART_IER, up->ier);
0697 
0698 #ifdef CONFIG_PM
0699     up->capabilities |= UART_CAP_RPM;
0700 #endif
0701 
0702     /* Enable module level wake up */
0703     priv->wer = OMAP_UART_WER_MOD_WKUP;
0704     if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
0705         priv->wer |= OMAP_UART_TX_WAKEUP_EN;
0706     serial_out(up, UART_OMAP_WER, priv->wer);
0707 
0708     if (up->dma && !(priv->habit & UART_HAS_EFR2))
0709         up->dma->rx_dma(up);
0710 
0711     pm_runtime_mark_last_busy(port->dev);
0712     pm_runtime_put_autosuspend(port->dev);
0713     return 0;
0714 err:
0715     pm_runtime_mark_last_busy(port->dev);
0716     pm_runtime_put_autosuspend(port->dev);
0717     dev_pm_clear_wake_irq(port->dev);
0718     return ret;
0719 }
0720 
0721 static void omap_8250_shutdown(struct uart_port *port)
0722 {
0723     struct uart_8250_port *up = up_to_u8250p(port);
0724     struct omap8250_priv *priv = port->private_data;
0725 
0726     flush_work(&priv->qos_work);
0727     if (up->dma)
0728         omap_8250_rx_dma_flush(up);
0729 
0730     pm_runtime_get_sync(port->dev);
0731 
0732     serial_out(up, UART_OMAP_WER, 0);
0733     if (priv->habit & UART_HAS_EFR2)
0734         serial_out(up, UART_OMAP_EFR2, 0x0);
0735 
0736     up->ier = 0;
0737     serial_out(up, UART_IER, 0);
0738 
0739     if (up->dma)
0740         serial8250_release_dma(up);
0741 
0742     /*
0743      * Disable break condition and FIFOs
0744      */
0745     if (up->lcr & UART_LCR_SBC)
0746         serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
0747     serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0748 
0749     pm_runtime_mark_last_busy(port->dev);
0750     pm_runtime_put_autosuspend(port->dev);
0751     free_irq(port->irq, port);
0752     dev_pm_clear_wake_irq(port->dev);
0753 }
0754 
0755 static void omap_8250_throttle(struct uart_port *port)
0756 {
0757     struct omap8250_priv *priv = port->private_data;
0758     unsigned long flags;
0759 
0760     pm_runtime_get_sync(port->dev);
0761 
0762     spin_lock_irqsave(&port->lock, flags);
0763     port->ops->stop_rx(port);
0764     priv->throttled = true;
0765     spin_unlock_irqrestore(&port->lock, flags);
0766 
0767     pm_runtime_mark_last_busy(port->dev);
0768     pm_runtime_put_autosuspend(port->dev);
0769 }
0770 
0771 static void omap_8250_unthrottle(struct uart_port *port)
0772 {
0773     struct omap8250_priv *priv = port->private_data;
0774     struct uart_8250_port *up = up_to_u8250p(port);
0775     unsigned long flags;
0776 
0777     pm_runtime_get_sync(port->dev);
0778 
0779     spin_lock_irqsave(&port->lock, flags);
0780     priv->throttled = false;
0781     if (up->dma)
0782         up->dma->rx_dma(up);
0783     up->ier |= UART_IER_RLSI | UART_IER_RDI;
0784     port->read_status_mask |= UART_LSR_DR;
0785     serial_out(up, UART_IER, up->ier);
0786     spin_unlock_irqrestore(&port->lock, flags);
0787 
0788     pm_runtime_mark_last_busy(port->dev);
0789     pm_runtime_put_autosuspend(port->dev);
0790 }
0791 
0792 #ifdef CONFIG_SERIAL_8250_DMA
0793 static int omap_8250_rx_dma(struct uart_8250_port *p);
0794 
0795 /* Must be called while priv->rx_dma_lock is held */
0796 static void __dma_rx_do_complete(struct uart_8250_port *p)
0797 {
0798     struct uart_8250_dma    *dma = p->dma;
0799     struct tty_port         *tty_port = &p->port.state->port;
0800     struct omap8250_priv    *priv = p->port.private_data;
0801     struct dma_chan     *rxchan = dma->rxchan;
0802     dma_cookie_t        cookie;
0803     struct dma_tx_state     state;
0804     int                     count;
0805     int         ret;
0806     u32         reg;
0807 
0808     if (!dma->rx_running)
0809         goto out;
0810 
0811     cookie = dma->rx_cookie;
0812     dma->rx_running = 0;
0813 
0814     /* Re-enable RX FIFO interrupt now that transfer is complete */
0815     if (priv->habit & UART_HAS_RHR_IT_DIS) {
0816         reg = serial_in(p, UART_OMAP_IER2);
0817         reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
0818         serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
0819     }
0820 
0821     dmaengine_tx_status(rxchan, cookie, &state);
0822 
0823     count = dma->rx_size - state.residue + state.in_flight_bytes;
0824     if (count < dma->rx_size) {
0825         dmaengine_terminate_async(rxchan);
0826 
0827         /*
0828          * Poll for teardown to complete which guarantees in
0829          * flight data is drained.
0830          */
0831         if (state.in_flight_bytes) {
0832             int poll_count = 25;
0833 
0834             while (dmaengine_tx_status(rxchan, cookie, NULL) &&
0835                    poll_count--)
0836                 cpu_relax();
0837 
0838             if (poll_count == -1)
0839                 dev_err(p->port.dev, "teardown incomplete\n");
0840         }
0841     }
0842     if (!count)
0843         goto out;
0844     ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
0845 
0846     p->port.icount.rx += ret;
0847     p->port.icount.buf_overrun += count - ret;
0848 out:
0849 
0850     tty_flip_buffer_push(tty_port);
0851 }
0852 
0853 static void __dma_rx_complete(void *param)
0854 {
0855     struct uart_8250_port *p = param;
0856     struct omap8250_priv *priv = p->port.private_data;
0857     struct uart_8250_dma *dma = p->dma;
0858     struct dma_tx_state     state;
0859     unsigned long flags;
0860 
0861     spin_lock_irqsave(&p->port.lock, flags);
0862 
0863     /*
0864      * If the tx status is not DMA_COMPLETE, then this is a delayed
0865      * completion callback. A previous RX timeout flush would have
0866      * already pushed the data, so exit.
0867      */
0868     if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
0869             DMA_COMPLETE) {
0870         spin_unlock_irqrestore(&p->port.lock, flags);
0871         return;
0872     }
0873     __dma_rx_do_complete(p);
0874     if (!priv->throttled) {
0875         p->ier |= UART_IER_RLSI | UART_IER_RDI;
0876         serial_out(p, UART_IER, p->ier);
0877         if (!(priv->habit & UART_HAS_EFR2))
0878             omap_8250_rx_dma(p);
0879     }
0880 
0881     spin_unlock_irqrestore(&p->port.lock, flags);
0882 }
0883 
0884 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
0885 {
0886     struct omap8250_priv    *priv = p->port.private_data;
0887     struct uart_8250_dma    *dma = p->dma;
0888     struct dma_tx_state     state;
0889     unsigned long       flags;
0890     int ret;
0891 
0892     spin_lock_irqsave(&priv->rx_dma_lock, flags);
0893 
0894     if (!dma->rx_running) {
0895         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
0896         return;
0897     }
0898 
0899     ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
0900     if (ret == DMA_IN_PROGRESS) {
0901         ret = dmaengine_pause(dma->rxchan);
0902         if (WARN_ON_ONCE(ret))
0903             priv->rx_dma_broken = true;
0904     }
0905     __dma_rx_do_complete(p);
0906     spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
0907 }
0908 
0909 static int omap_8250_rx_dma(struct uart_8250_port *p)
0910 {
0911     struct omap8250_priv        *priv = p->port.private_data;
0912     struct uart_8250_dma            *dma = p->dma;
0913     int             err = 0;
0914     struct dma_async_tx_descriptor  *desc;
0915     unsigned long           flags;
0916     u32             reg;
0917 
0918     if (priv->rx_dma_broken)
0919         return -EINVAL;
0920 
0921     spin_lock_irqsave(&priv->rx_dma_lock, flags);
0922 
0923     if (dma->rx_running) {
0924         enum dma_status state;
0925 
0926         state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
0927         if (state == DMA_COMPLETE) {
0928             /*
0929              * Disable RX interrupts to allow RX DMA completion
0930              * callback to run.
0931              */
0932             p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
0933             serial_out(p, UART_IER, p->ier);
0934         }
0935         goto out;
0936     }
0937 
0938     desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
0939                        dma->rx_size, DMA_DEV_TO_MEM,
0940                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0941     if (!desc) {
0942         err = -EBUSY;
0943         goto out;
0944     }
0945 
0946     dma->rx_running = 1;
0947     desc->callback = __dma_rx_complete;
0948     desc->callback_param = p;
0949 
0950     dma->rx_cookie = dmaengine_submit(desc);
0951 
0952     /*
0953      * Disable RX FIFO interrupt while RX DMA is enabled, else
0954      * spurious interrupt may be raised when data is in the RX FIFO
0955      * but is yet to be drained by DMA.
0956      */
0957     if (priv->habit & UART_HAS_RHR_IT_DIS) {
0958         reg = serial_in(p, UART_OMAP_IER2);
0959         reg |= UART_OMAP_IER2_RHR_IT_DIS;
0960         serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
0961     }
0962 
0963     dma_async_issue_pending(dma->rxchan);
0964 out:
0965     spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
0966     return err;
0967 }
0968 
0969 static int omap_8250_tx_dma(struct uart_8250_port *p);
0970 
0971 static void omap_8250_dma_tx_complete(void *param)
0972 {
0973     struct uart_8250_port   *p = param;
0974     struct uart_8250_dma    *dma = p->dma;
0975     struct circ_buf     *xmit = &p->port.state->xmit;
0976     unsigned long       flags;
0977     bool            en_thri = false;
0978     struct omap8250_priv    *priv = p->port.private_data;
0979 
0980     dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
0981                 UART_XMIT_SIZE, DMA_TO_DEVICE);
0982 
0983     spin_lock_irqsave(&p->port.lock, flags);
0984 
0985     dma->tx_running = 0;
0986 
0987     xmit->tail += dma->tx_size;
0988     xmit->tail &= UART_XMIT_SIZE - 1;
0989     p->port.icount.tx += dma->tx_size;
0990 
0991     if (priv->delayed_restore) {
0992         priv->delayed_restore = 0;
0993         omap8250_restore_regs(p);
0994     }
0995 
0996     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0997         uart_write_wakeup(&p->port);
0998 
0999     if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1000         int ret;
1001 
1002         ret = omap_8250_tx_dma(p);
1003         if (ret)
1004             en_thri = true;
1005     } else if (p->capabilities & UART_CAP_RPM) {
1006         en_thri = true;
1007     }
1008 
1009     if (en_thri) {
1010         dma->tx_err = 1;
1011         serial8250_set_THRI(p);
1012     }
1013 
1014     spin_unlock_irqrestore(&p->port.lock, flags);
1015 }
1016 
1017 static int omap_8250_tx_dma(struct uart_8250_port *p)
1018 {
1019     struct uart_8250_dma        *dma = p->dma;
1020     struct omap8250_priv        *priv = p->port.private_data;
1021     struct circ_buf         *xmit = &p->port.state->xmit;
1022     struct dma_async_tx_descriptor  *desc;
1023     unsigned int    skip_byte = 0;
1024     int ret;
1025 
1026     if (dma->tx_running)
1027         return 0;
1028     if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1029 
1030         /*
1031          * Even if no data, we need to return an error for the two cases
1032          * below so serial8250_tx_chars() is invoked and properly clears
1033          * THRI and/or runtime suspend.
1034          */
1035         if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1036             ret = -EBUSY;
1037             goto err;
1038         }
1039         serial8250_clear_THRI(p);
1040         return 0;
1041     }
1042 
1043     dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1044     if (priv->habit & OMAP_DMA_TX_KICK) {
1045         u8 tx_lvl;
1046 
1047         /*
1048          * We need to put the first byte into the FIFO in order to start
1049          * the DMA transfer. For transfers smaller than four bytes we
1050          * don't bother doing DMA at all. It seem not matter if there
1051          * are still bytes in the FIFO from the last transfer (in case
1052          * we got here directly from omap_8250_dma_tx_complete()). Bytes
1053          * leaving the FIFO seem not to trigger the DMA transfer. It is
1054          * really the byte that we put into the FIFO.
1055          * If the FIFO is already full then we most likely got here from
1056          * omap_8250_dma_tx_complete(). And this means the DMA engine
1057          * just completed its work. We don't have to wait the complete
1058          * 86us at 115200,8n1 but around 60us (not to mention lower
1059          * baudrates). So in that case we take the interrupt and try
1060          * again with an empty FIFO.
1061          */
1062         tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1063         if (tx_lvl == p->tx_loadsz) {
1064             ret = -EBUSY;
1065             goto err;
1066         }
1067         if (dma->tx_size < 4) {
1068             ret = -EINVAL;
1069             goto err;
1070         }
1071         skip_byte = 1;
1072     }
1073 
1074     desc = dmaengine_prep_slave_single(dma->txchan,
1075             dma->tx_addr + xmit->tail + skip_byte,
1076             dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1077             DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1078     if (!desc) {
1079         ret = -EBUSY;
1080         goto err;
1081     }
1082 
1083     dma->tx_running = 1;
1084 
1085     desc->callback = omap_8250_dma_tx_complete;
1086     desc->callback_param = p;
1087 
1088     dma->tx_cookie = dmaengine_submit(desc);
1089 
1090     dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1091                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1092 
1093     dma_async_issue_pending(dma->txchan);
1094     if (dma->tx_err)
1095         dma->tx_err = 0;
1096 
1097     serial8250_clear_THRI(p);
1098     if (skip_byte)
1099         serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1100     return 0;
1101 err:
1102     dma->tx_err = 1;
1103     return ret;
1104 }
1105 
1106 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1107 {
1108     switch (iir & 0x3f) {
1109     case UART_IIR_RLSI:
1110     case UART_IIR_RX_TIMEOUT:
1111     case UART_IIR_RDI:
1112         omap_8250_rx_dma_flush(up);
1113         return true;
1114     }
1115     return omap_8250_rx_dma(up);
1116 }
1117 
1118 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1119 {
1120     if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1121         (iir & UART_IIR_RDI)) {
1122         if (handle_rx_dma(up, iir)) {
1123             status = serial8250_rx_chars(up, status);
1124             omap_8250_rx_dma(up);
1125         }
1126     }
1127 
1128     return status;
1129 }
1130 
1131 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1132                      u16 status)
1133 {
1134     /*
1135      * Queue a new transfer if FIFO has data.
1136      */
1137     if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1138         (up->ier & UART_IER_RDI)) {
1139         omap_8250_rx_dma(up);
1140         serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1141     } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1142         /*
1143          * Disable RX timeout, read IIR to clear
1144          * current timeout condition, clear EFR2 to
1145          * periodic timeouts, re-enable interrupts.
1146          */
1147         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1148         serial_out(up, UART_IER, up->ier);
1149         omap_8250_rx_dma_flush(up);
1150         serial_in(up, UART_IIR);
1151         serial_out(up, UART_OMAP_EFR2, 0x0);
1152         up->ier |= UART_IER_RLSI | UART_IER_RDI;
1153         serial_out(up, UART_IER, up->ier);
1154     }
1155 }
1156 
1157 /*
1158  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1159  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1160  * use the default routine in the non-DMA case and this one for with DMA.
1161  */
1162 static int omap_8250_dma_handle_irq(struct uart_port *port)
1163 {
1164     struct uart_8250_port *up = up_to_u8250p(port);
1165     struct omap8250_priv *priv = up->port.private_data;
1166     u16 status;
1167     u8 iir;
1168 
1169     serial8250_rpm_get(up);
1170 
1171     iir = serial_port_in(port, UART_IIR);
1172     if (iir & UART_IIR_NO_INT) {
1173         serial8250_rpm_put(up);
1174         return IRQ_HANDLED;
1175     }
1176 
1177     spin_lock(&port->lock);
1178 
1179     status = serial_port_in(port, UART_LSR);
1180 
1181     if (priv->habit & UART_HAS_EFR2)
1182         am654_8250_handle_rx_dma(up, iir, status);
1183     else
1184         status = omap_8250_handle_rx_dma(up, iir, status);
1185 
1186     serial8250_modem_status(up);
1187     if (status & UART_LSR_THRE && up->dma->tx_err) {
1188         if (uart_tx_stopped(&up->port) ||
1189             uart_circ_empty(&up->port.state->xmit)) {
1190             up->dma->tx_err = 0;
1191             serial8250_tx_chars(up);
1192         } else  {
1193             /*
1194              * try again due to an earlier failer which
1195              * might have been resolved by now.
1196              */
1197             if (omap_8250_tx_dma(up))
1198                 serial8250_tx_chars(up);
1199         }
1200     }
1201 
1202     uart_unlock_and_check_sysrq(port);
1203 
1204     serial8250_rpm_put(up);
1205     return 1;
1206 }
1207 
1208 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1209 {
1210     return false;
1211 }
1212 
1213 #else
1214 
1215 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1216 {
1217     return -EINVAL;
1218 }
1219 #endif
1220 
1221 static int omap8250_no_handle_irq(struct uart_port *port)
1222 {
1223     /* IRQ has not been requested but handling irq? */
1224     WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1225     return 0;
1226 }
1227 
1228 static struct omap8250_dma_params am654_dma = {
1229     .rx_size = SZ_2K,
1230     .rx_trigger = 1,
1231     .tx_trigger = TX_TRIGGER,
1232 };
1233 
1234 static struct omap8250_dma_params am33xx_dma = {
1235     .rx_size = RX_TRIGGER,
1236     .rx_trigger = RX_TRIGGER,
1237     .tx_trigger = TX_TRIGGER,
1238 };
1239 
1240 static struct omap8250_platdata am654_platdata = {
1241     .dma_params = &am654_dma,
1242     .habit      = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1243               UART_RX_TIMEOUT_QUIRK,
1244 };
1245 
1246 static struct omap8250_platdata am33xx_platdata = {
1247     .dma_params = &am33xx_dma,
1248     .habit      = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1249 };
1250 
1251 static struct omap8250_platdata omap4_platdata = {
1252     .dma_params = &am33xx_dma,
1253     .habit      = UART_ERRATA_CLOCK_DISABLE,
1254 };
1255 
1256 static const struct of_device_id omap8250_dt_ids[] = {
1257     { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1258     { .compatible = "ti,omap2-uart" },
1259     { .compatible = "ti,omap3-uart" },
1260     { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1261     { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1262     { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1263     { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1264     {},
1265 };
1266 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1267 
1268 static int omap8250_probe(struct platform_device *pdev)
1269 {
1270     struct device_node *np = pdev->dev.of_node;
1271     struct omap8250_priv *priv;
1272     const struct omap8250_platdata *pdata;
1273     struct uart_8250_port up;
1274     struct resource *regs;
1275     void __iomem *membase;
1276     int irq, ret;
1277 
1278     irq = platform_get_irq(pdev, 0);
1279     if (irq < 0)
1280         return irq;
1281 
1282     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1283     if (!regs) {
1284         dev_err(&pdev->dev, "missing registers\n");
1285         return -EINVAL;
1286     }
1287 
1288     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1289     if (!priv)
1290         return -ENOMEM;
1291 
1292     membase = devm_ioremap(&pdev->dev, regs->start,
1293                        resource_size(regs));
1294     if (!membase)
1295         return -ENODEV;
1296 
1297     memset(&up, 0, sizeof(up));
1298     up.port.dev = &pdev->dev;
1299     up.port.mapbase = regs->start;
1300     up.port.membase = membase;
1301     up.port.irq = irq;
1302     /*
1303      * It claims to be 16C750 compatible however it is a little different.
1304      * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1305      * have) is enabled via EFR instead of MCR. The type is set here 8250
1306      * just to get things going. UNKNOWN does not work for a few reasons and
1307      * we don't need our own type since we don't use 8250's set_termios()
1308      * or pm callback.
1309      */
1310     up.port.type = PORT_8250;
1311     up.port.iotype = UPIO_MEM;
1312     up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1313         UPF_HARD_FLOW;
1314     up.port.private_data = priv;
1315 
1316     up.port.regshift = 2;
1317     up.port.fifosize = 64;
1318     up.tx_loadsz = 64;
1319     up.capabilities = UART_CAP_FIFO;
1320 #ifdef CONFIG_PM
1321     /*
1322      * Runtime PM is mostly transparent. However to do it right we need to a
1323      * TX empty interrupt before we can put the device to auto idle. So if
1324      * PM is not enabled we don't add that flag and can spare that one extra
1325      * interrupt in the TX path.
1326      */
1327     up.capabilities |= UART_CAP_RPM;
1328 #endif
1329     up.port.set_termios = omap_8250_set_termios;
1330     up.port.set_mctrl = omap8250_set_mctrl;
1331     up.port.pm = omap_8250_pm;
1332     up.port.startup = omap_8250_startup;
1333     up.port.shutdown = omap_8250_shutdown;
1334     up.port.throttle = omap_8250_throttle;
1335     up.port.unthrottle = omap_8250_unthrottle;
1336     up.port.rs485_config = serial8250_em485_config;
1337     up.port.rs485_supported = serial8250_em485_supported;
1338     up.rs485_start_tx = serial8250_em485_start_tx;
1339     up.rs485_stop_tx = serial8250_em485_stop_tx;
1340     up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1341 
1342     ret = of_alias_get_id(np, "serial");
1343     if (ret < 0) {
1344         dev_err(&pdev->dev, "failed to get alias\n");
1345         return ret;
1346     }
1347     up.port.line = ret;
1348 
1349     if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1350         struct clk *clk;
1351 
1352         clk = devm_clk_get(&pdev->dev, NULL);
1353         if (IS_ERR(clk)) {
1354             if (PTR_ERR(clk) == -EPROBE_DEFER)
1355                 return -EPROBE_DEFER;
1356         } else {
1357             up.port.uartclk = clk_get_rate(clk);
1358         }
1359     }
1360 
1361     if (of_property_read_u32(np, "overrun-throttle-ms",
1362                  &up.overrun_backoff_time_ms) != 0)
1363         up.overrun_backoff_time_ms = 0;
1364 
1365     priv->wakeirq = irq_of_parse_and_map(np, 1);
1366 
1367     pdata = of_device_get_match_data(&pdev->dev);
1368     if (pdata)
1369         priv->habit |= pdata->habit;
1370 
1371     if (!up.port.uartclk) {
1372         up.port.uartclk = DEFAULT_CLK_SPEED;
1373         dev_warn(&pdev->dev,
1374              "No clock speed specified: using default: %d\n",
1375              DEFAULT_CLK_SPEED);
1376     }
1377 
1378     priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1379     priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1380     cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1381     INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1382 
1383     spin_lock_init(&priv->rx_dma_lock);
1384 
1385     device_init_wakeup(&pdev->dev, true);
1386     pm_runtime_enable(&pdev->dev);
1387     pm_runtime_use_autosuspend(&pdev->dev);
1388 
1389     /*
1390      * Disable runtime PM until autosuspend delay unless specifically
1391      * enabled by the user via sysfs. This is the historic way to
1392      * prevent an unsafe default policy with lossy characters on wake-up.
1393      * For serdev devices this is not needed, the policy can be managed by
1394      * the serdev driver.
1395      */
1396     if (!of_get_available_child_count(pdev->dev.of_node))
1397         pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1398 
1399     pm_runtime_irq_safe(&pdev->dev);
1400 
1401     pm_runtime_get_sync(&pdev->dev);
1402 
1403     omap_serial_fill_features_erratas(&up, priv);
1404     up.port.handle_irq = omap8250_no_handle_irq;
1405     priv->rx_trigger = RX_TRIGGER;
1406     priv->tx_trigger = TX_TRIGGER;
1407 #ifdef CONFIG_SERIAL_8250_DMA
1408     /*
1409      * Oh DMA support. If there are no DMA properties in the DT then
1410      * we will fall back to a generic DMA channel which does not
1411      * really work here. To ensure that we do not get a generic DMA
1412      * channel assigned, we have the the_no_dma_filter_fn() here.
1413      * To avoid "failed to request DMA" messages we check for DMA
1414      * properties in DT.
1415      */
1416     ret = of_property_count_strings(np, "dma-names");
1417     if (ret == 2) {
1418         struct omap8250_dma_params *dma_params = NULL;
1419 
1420         up.dma = &priv->omap8250_dma;
1421         up.dma->fn = the_no_dma_filter_fn;
1422         up.dma->tx_dma = omap_8250_tx_dma;
1423         up.dma->rx_dma = omap_8250_rx_dma;
1424         if (pdata)
1425             dma_params = pdata->dma_params;
1426 
1427         if (dma_params) {
1428             up.dma->rx_size = dma_params->rx_size;
1429             up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1430             up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1431             priv->rx_trigger = dma_params->rx_trigger;
1432             priv->tx_trigger = dma_params->tx_trigger;
1433         } else {
1434             up.dma->rx_size = RX_TRIGGER;
1435             up.dma->rxconf.src_maxburst = RX_TRIGGER;
1436             up.dma->txconf.dst_maxburst = TX_TRIGGER;
1437         }
1438     }
1439 #endif
1440     ret = serial8250_register_8250_port(&up);
1441     if (ret < 0) {
1442         dev_err(&pdev->dev, "unable to register 8250 port\n");
1443         goto err;
1444     }
1445     priv->line = ret;
1446     platform_set_drvdata(pdev, priv);
1447     pm_runtime_mark_last_busy(&pdev->dev);
1448     pm_runtime_put_autosuspend(&pdev->dev);
1449     return 0;
1450 err:
1451     pm_runtime_dont_use_autosuspend(&pdev->dev);
1452     pm_runtime_put_sync(&pdev->dev);
1453     pm_runtime_disable(&pdev->dev);
1454     return ret;
1455 }
1456 
1457 static int omap8250_remove(struct platform_device *pdev)
1458 {
1459     struct omap8250_priv *priv = platform_get_drvdata(pdev);
1460 
1461     pm_runtime_dont_use_autosuspend(&pdev->dev);
1462     pm_runtime_put_sync(&pdev->dev);
1463     pm_runtime_disable(&pdev->dev);
1464     serial8250_unregister_port(priv->line);
1465     cpu_latency_qos_remove_request(&priv->pm_qos_request);
1466     device_init_wakeup(&pdev->dev, false);
1467     return 0;
1468 }
1469 
1470 #ifdef CONFIG_PM_SLEEP
1471 static int omap8250_prepare(struct device *dev)
1472 {
1473     struct omap8250_priv *priv = dev_get_drvdata(dev);
1474 
1475     if (!priv)
1476         return 0;
1477     priv->is_suspending = true;
1478     return 0;
1479 }
1480 
1481 static void omap8250_complete(struct device *dev)
1482 {
1483     struct omap8250_priv *priv = dev_get_drvdata(dev);
1484 
1485     if (!priv)
1486         return;
1487     priv->is_suspending = false;
1488 }
1489 
1490 static int omap8250_suspend(struct device *dev)
1491 {
1492     struct omap8250_priv *priv = dev_get_drvdata(dev);
1493     struct uart_8250_port *up = serial8250_get_port(priv->line);
1494 
1495     serial8250_suspend_port(priv->line);
1496 
1497     pm_runtime_get_sync(dev);
1498     if (!device_may_wakeup(dev))
1499         priv->wer = 0;
1500     serial_out(up, UART_OMAP_WER, priv->wer);
1501     pm_runtime_mark_last_busy(dev);
1502     pm_runtime_put_autosuspend(dev);
1503 
1504     flush_work(&priv->qos_work);
1505     return 0;
1506 }
1507 
1508 static int omap8250_resume(struct device *dev)
1509 {
1510     struct omap8250_priv *priv = dev_get_drvdata(dev);
1511 
1512     serial8250_resume_port(priv->line);
1513     return 0;
1514 }
1515 #else
1516 #define omap8250_prepare NULL
1517 #define omap8250_complete NULL
1518 #endif
1519 
1520 #ifdef CONFIG_PM
1521 static int omap8250_lost_context(struct uart_8250_port *up)
1522 {
1523     u32 val;
1524 
1525     val = serial_in(up, UART_OMAP_SCR);
1526     /*
1527      * If we lose context, then SCR is set to its reset value of zero.
1528      * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1529      * among other bits, to never set the register back to zero again.
1530      */
1531     if (!val)
1532         return 1;
1533     return 0;
1534 }
1535 
1536 /* TODO: in future, this should happen via API in drivers/reset/ */
1537 static int omap8250_soft_reset(struct device *dev)
1538 {
1539     struct omap8250_priv *priv = dev_get_drvdata(dev);
1540     struct uart_8250_port *up = serial8250_get_port(priv->line);
1541     int timeout = 100;
1542     int sysc;
1543     int syss;
1544 
1545     /*
1546      * At least on omap4, unused uarts may not idle after reset without
1547      * a basic scr dma configuration even with no dma in use. The
1548      * module clkctrl status bits will be 1 instead of 3 blocking idle
1549      * for the whole clockdomain. The softreset below will clear scr,
1550      * and we restore it on resume so this is safe to do on all SoCs
1551      * needing omap8250_soft_reset() quirk. Do it in two writes as
1552      * recommended in the comment for omap8250_update_scr().
1553      */
1554     serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1555     serial_out(up, UART_OMAP_SCR,
1556            OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1557 
1558     sysc = serial_in(up, UART_OMAP_SYSC);
1559 
1560     /* softreset the UART */
1561     sysc |= OMAP_UART_SYSC_SOFTRESET;
1562     serial_out(up, UART_OMAP_SYSC, sysc);
1563 
1564     /* By experiments, 1us enough for reset complete on AM335x */
1565     do {
1566         udelay(1);
1567         syss = serial_in(up, UART_OMAP_SYSS);
1568     } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1569 
1570     if (!timeout) {
1571         dev_err(dev, "timed out waiting for reset done\n");
1572         return -ETIMEDOUT;
1573     }
1574 
1575     return 0;
1576 }
1577 
1578 static int omap8250_runtime_suspend(struct device *dev)
1579 {
1580     struct omap8250_priv *priv = dev_get_drvdata(dev);
1581     struct uart_8250_port *up;
1582 
1583     /* In case runtime-pm tries this before we are setup */
1584     if (!priv)
1585         return 0;
1586 
1587     up = serial8250_get_port(priv->line);
1588     /*
1589      * When using 'no_console_suspend', the console UART must not be
1590      * suspended. Since driver suspend is managed by runtime suspend,
1591      * preventing runtime suspend (by returning error) will keep device
1592      * active during suspend.
1593      */
1594     if (priv->is_suspending && !console_suspend_enabled) {
1595         if (uart_console(&up->port))
1596             return -EBUSY;
1597     }
1598 
1599     if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1600         int ret;
1601 
1602         ret = omap8250_soft_reset(dev);
1603         if (ret)
1604             return ret;
1605 
1606         /* Restore to UART mode after reset (for wakeup) */
1607         omap8250_update_mdr1(up, priv);
1608         /* Restore wakeup enable register */
1609         serial_out(up, UART_OMAP_WER, priv->wer);
1610     }
1611 
1612     if (up->dma && up->dma->rxchan)
1613         omap_8250_rx_dma_flush(up);
1614 
1615     priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1616     schedule_work(&priv->qos_work);
1617 
1618     return 0;
1619 }
1620 
1621 static int omap8250_runtime_resume(struct device *dev)
1622 {
1623     struct omap8250_priv *priv = dev_get_drvdata(dev);
1624     struct uart_8250_port *up;
1625 
1626     /* In case runtime-pm tries this before we are setup */
1627     if (!priv)
1628         return 0;
1629 
1630     up = serial8250_get_port(priv->line);
1631 
1632     if (omap8250_lost_context(up))
1633         omap8250_restore_regs(up);
1634 
1635     if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1636         omap_8250_rx_dma(up);
1637 
1638     priv->latency = priv->calc_latency;
1639     schedule_work(&priv->qos_work);
1640     return 0;
1641 }
1642 #endif
1643 
1644 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1645 static int __init omap8250_console_fixup(void)
1646 {
1647     char *omap_str;
1648     char *options;
1649     u8 idx;
1650 
1651     if (strstr(boot_command_line, "console=ttyS"))
1652         /* user set a ttyS based name for the console */
1653         return 0;
1654 
1655     omap_str = strstr(boot_command_line, "console=ttyO");
1656     if (!omap_str)
1657         /* user did not set ttyO based console, so we don't care */
1658         return 0;
1659 
1660     omap_str += 12;
1661     if ('0' <= *omap_str && *omap_str <= '9')
1662         idx = *omap_str - '0';
1663     else
1664         return 0;
1665 
1666     omap_str++;
1667     if (omap_str[0] == ',') {
1668         omap_str++;
1669         options = omap_str;
1670     } else {
1671         options = NULL;
1672     }
1673 
1674     add_preferred_console("ttyS", idx, options);
1675     pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1676            idx, idx);
1677     pr_err("This ensures that you still see kernel messages. Please\n");
1678     pr_err("update your kernel commandline.\n");
1679     return 0;
1680 }
1681 console_initcall(omap8250_console_fixup);
1682 #endif
1683 
1684 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1685     SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1686     SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1687                omap8250_runtime_resume, NULL)
1688     .prepare        = omap8250_prepare,
1689     .complete       = omap8250_complete,
1690 };
1691 
1692 static struct platform_driver omap8250_platform_driver = {
1693     .driver = {
1694         .name       = "omap8250",
1695         .pm     = &omap8250_dev_pm_ops,
1696         .of_match_table = omap8250_dt_ids,
1697     },
1698     .probe          = omap8250_probe,
1699     .remove         = omap8250_remove,
1700 };
1701 module_platform_driver(omap8250_platform_driver);
1702 
1703 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1704 MODULE_DESCRIPTION("OMAP 8250 Driver");
1705 MODULE_LICENSE("GPL v2");
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