serial/8250/8250_lpc18xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Serial port driver for NXP LPC18xx/43xx UART
0004  *
0005  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0006  *
0007  * Based on 8250_mtk.c:
0008  * Copyright (c) 2014 MundoReader S.L.
0009  * Matthias Brugger <matthias.bgg@gmail.com>
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017
0018 #include "8250.h"
0019
0020 /* Additional LPC18xx/43xx 8250 registers and bits */
0021 #define LPC18XX_UART_RS485CTRL      (0x04c / sizeof(u32))
0022 #define  LPC18XX_UART_RS485CTRL_NMMEN   BIT(0)
0023 #define  LPC18XX_UART_RS485CTRL_DCTRL   BIT(4)
0024 #define  LPC18XX_UART_RS485CTRL_OINV    BIT(5)
0025 #define LPC18XX_UART_RS485DLY       (0x054 / sizeof(u32))
0026 #define LPC18XX_UART_RS485DLY_MAX   255
0027
0028 struct lpc18xx_uart_data {
0029     struct uart_8250_dma dma;
0030     struct clk *clk_uart;
0031     struct clk *clk_reg;
0032     int line;
0033 };
0034
0035 static int lpc18xx_rs485_config(struct uart_port *port, struct ktermios *termios,
0036                 struct serial_rs485 *rs485)
0037 {
0038     struct uart_8250_port *up = up_to_u8250p(port);
0039     u32 rs485_ctrl_reg = 0;
0040     u32 rs485_dly_reg = 0;
0041     unsigned baud_clk;
0042
0043     if (rs485->flags & SER_RS485_ENABLED) {
0044         rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_NMMEN |
0045                   LPC18XX_UART_RS485CTRL_DCTRL;
0046
0047         if (rs485->flags & SER_RS485_RTS_ON_SEND)
0048             rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_OINV;
0049     }
0050
0051     if (rs485->delay_rts_after_send) {
0052         baud_clk = port->uartclk / up->dl_read(up);
0053         rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send
0054                         * baud_clk, MSEC_PER_SEC);
0055
0056         if (rs485_dly_reg > LPC18XX_UART_RS485DLY_MAX)
0057             rs485_dly_reg = LPC18XX_UART_RS485DLY_MAX;
0058
0059         /* Calculate the resulting delay in ms */
0060         rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC)
0061                         / baud_clk;
0062     }
0063
0064     serial_out(up, LPC18XX_UART_RS485CTRL, rs485_ctrl_reg);
0065     serial_out(up, LPC18XX_UART_RS485DLY, rs485_dly_reg);
0066
0067     return 0;
0068 }
0069
0070 static void lpc18xx_uart_serial_out(struct uart_port *p, int offset, int value)
0071 {
0072     /*
0073      * For DMA mode one must ensure that the UART_FCR_DMA_SELECT
0074      * bit is set when FIFO is enabled. Even if DMA is not used
0075      * setting this bit doesn't seem to affect anything.
0076      */
0077     if (offset == UART_FCR && (value & UART_FCR_ENABLE_FIFO))
0078         value |= UART_FCR_DMA_SELECT;
0079
0080     offset = offset << p->regshift;
0081     writel(value, p->membase + offset);
0082 }
0083
0084 static const struct serial_rs485 lpc18xx_rs485_supported = {
0085     .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
0086     .delay_rts_after_send = 1,
0087     /* Delay RTS before send is not supported */
0088 };
0089
0090 static int lpc18xx_serial_probe(struct platform_device *pdev)
0091 {
0092     struct lpc18xx_uart_data *data;
0093     struct uart_8250_port uart;
0094     struct resource *res;
0095     int irq, ret;
0096
0097     irq = platform_get_irq(pdev, 0);
0098     if (irq < 0)
0099         return irq;
0100
0101     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0102     if (!res) {
0103         dev_err(&pdev->dev, "memory resource not found");
0104         return -EINVAL;
0105     }
0106
0107     memset(&uart, 0, sizeof(uart));
0108
0109     uart.port.membase = devm_ioremap(&pdev->dev, res->start,
0110                      resource_size(res));
0111     if (!uart.port.membase)
0112         return -ENOMEM;
0113
0114     data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
0115     if (!data)
0116         return -ENOMEM;
0117
0118     data->clk_uart = devm_clk_get(&pdev->dev, "uartclk");
0119     if (IS_ERR(data->clk_uart)) {
0120         dev_err(&pdev->dev, "uart clock not found\n");
0121         return PTR_ERR(data->clk_uart);
0122     }
0123
0124     data->clk_reg = devm_clk_get(&pdev->dev, "reg");
0125     if (IS_ERR(data->clk_reg)) {
0126         dev_err(&pdev->dev, "reg clock not found\n");
0127         return PTR_ERR(data->clk_reg);
0128     }
0129
0130     ret = clk_prepare_enable(data->clk_reg);
0131     if (ret) {
0132         dev_err(&pdev->dev, "unable to enable reg clock\n");
0133         return ret;
0134     }
0135
0136     ret = clk_prepare_enable(data->clk_uart);
0137     if (ret) {
0138         dev_err(&pdev->dev, "unable to enable uart clock\n");
0139         goto dis_clk_reg;
0140     }
0141
0142     ret = of_alias_get_id(pdev->dev.of_node, "serial");
0143     if (ret >= 0)
0144         uart.port.line = ret;
0145
0146     data->dma.rx_param = data;
0147     data->dma.tx_param = data;
0148
0149     spin_lock_init(&uart.port.lock);
0150     uart.port.dev = &pdev->dev;
0151     uart.port.irq = irq;
0152     uart.port.iotype = UPIO_MEM32;
0153     uart.port.mapbase = res->start;
0154     uart.port.regshift = 2;
0155     uart.port.type = PORT_16550A;
0156     uart.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SKIP_TEST;
0157     uart.port.uartclk = clk_get_rate(data->clk_uart);
0158     uart.port.private_data = data;
0159     uart.port.rs485_config = lpc18xx_rs485_config;
0160     uart.port.rs485_supported = lpc18xx_rs485_supported;
0161     uart.port.serial_out = lpc18xx_uart_serial_out;
0162
0163     uart.dma = &data->dma;
0164     uart.dma->rxconf.src_maxburst = 1;
0165     uart.dma->txconf.dst_maxburst = 1;
0166
0167     ret = serial8250_register_8250_port(&uart);
0168     if (ret < 0) {
0169         dev_err(&pdev->dev, "unable to register 8250 port\n");
0170         goto dis_uart_clk;
0171     }
0172
0173     data->line = ret;
0174     platform_set_drvdata(pdev, data);
0175
0176     return 0;
0177
0178 dis_uart_clk:
0179     clk_disable_unprepare(data->clk_uart);
0180 dis_clk_reg:
0181     clk_disable_unprepare(data->clk_reg);
0182     return ret;
0183 }
0184
0185 static int lpc18xx_serial_remove(struct platform_device *pdev)
0186 {
0187     struct lpc18xx_uart_data *data = platform_get_drvdata(pdev);
0188
0189     serial8250_unregister_port(data->line);
0190     clk_disable_unprepare(data->clk_uart);
0191     clk_disable_unprepare(data->clk_reg);
0192
0193     return 0;
0194 }
0195
0196 static const struct of_device_id lpc18xx_serial_match[] = {
0197     { .compatible = "nxp,lpc1850-uart" },
0198     { },
0199 };
0200 MODULE_DEVICE_TABLE(of, lpc18xx_serial_match);
0201
0202 static struct platform_driver lpc18xx_serial_driver = {
0203     .probe  = lpc18xx_serial_probe,
0204     .remove = lpc18xx_serial_remove,
0205     .driver = {
0206         .name = "lpc18xx-uart",
0207         .of_match_table = lpc18xx_serial_match,
0208     },
0209 };
0210 module_platform_driver(lpc18xx_serial_driver);
0211
0212 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
0213 MODULE_DESCRIPTION("Serial port driver NXP LPC18xx/43xx devices");
0214 MODULE_LICENSE("GPL v2");