serial/8250/8250_ingenic.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
0004  * Copyright (C) 2015 Imagination Technologies
0005  *
0006  * Ingenic SoC UART support
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/console.h>
0011 #include <linux/io.h>
0012 #include <linux/libfdt.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_fdt.h>
0016 #include <linux/of_device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/serial_8250.h>
0019 #include <linux/serial_core.h>
0020 #include <linux/serial_reg.h>
0021
0022 #include "8250.h"
0023
0024 /** ingenic_uart_config: SOC specific config data. */
0025 struct ingenic_uart_config {
0026     int tx_loadsz;
0027     int fifosize;
0028 };
0029
0030 struct ingenic_uart_data {
0031     struct clk  *clk_module;
0032     struct clk  *clk_baud;
0033     int     line;
0034 };
0035
0036 static const struct of_device_id of_match[];
0037
0038 #define UART_FCR_UME    BIT(4)
0039
0040 #define UART_MCR_MDCE   BIT(7)
0041 #define UART_MCR_FCM    BIT(6)
0042
0043 static struct earlycon_device *early_device;
0044
0045 static uint8_t early_in(struct uart_port *port, int offset)
0046 {
0047     return readl(port->membase + (offset << 2));
0048 }
0049
0050 static void early_out(struct uart_port *port, int offset, uint8_t value)
0051 {
0052     writel(value, port->membase + (offset << 2));
0053 }
0054
0055 static void ingenic_early_console_putc(struct uart_port *port, unsigned char c)
0056 {
0057     u16 lsr;
0058
0059     do {
0060         lsr = early_in(port, UART_LSR);
0061     } while ((lsr & UART_LSR_TEMT) == 0);
0062
0063     early_out(port, UART_TX, c);
0064 }
0065
0066 static void ingenic_early_console_write(struct console *console,
0067                           const char *s, unsigned int count)
0068 {
0069     uart_console_write(&early_device->port, s, count,
0070                ingenic_early_console_putc);
0071 }
0072
0073 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
0074 {
0075     void *fdt = initial_boot_params;
0076     const __be32 *prop;
0077     int offset;
0078
0079     offset = fdt_path_offset(fdt, "/ext");
0080     if (offset < 0)
0081         return;
0082
0083     prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
0084     if (!prop)
0085         return;
0086
0087     dev->port.uartclk = be32_to_cpup(prop);
0088 }
0089
0090 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
0091                           const char *opt)
0092 {
0093     struct uart_port *port = &dev->port;
0094     unsigned int divisor;
0095     int baud = 115200;
0096
0097     if (!dev->port.membase)
0098         return -ENODEV;
0099
0100     if (opt) {
0101         unsigned int parity, bits, flow; /* unused for now */
0102
0103         uart_parse_options(opt, &baud, &parity, &bits, &flow);
0104     }
0105
0106     ingenic_early_console_setup_clock(dev);
0107
0108     if (dev->baud)
0109         baud = dev->baud;
0110     divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
0111
0112     early_out(port, UART_IER, 0);
0113     early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
0114     early_out(port, UART_DLL, 0);
0115     early_out(port, UART_DLM, 0);
0116     early_out(port, UART_LCR, UART_LCR_WLEN8);
0117     early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
0118             UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
0119     early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
0120
0121     early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
0122     early_out(port, UART_DLL, divisor & 0xff);
0123     early_out(port, UART_DLM, (divisor >> 8) & 0xff);
0124     early_out(port, UART_LCR, UART_LCR_WLEN8);
0125
0126     early_device = dev;
0127     dev->con->write = ingenic_early_console_write;
0128
0129     return 0;
0130 }
0131
0132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
0133             ingenic_early_console_setup);
0134
0135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
0136             ingenic_early_console_setup);
0137
0138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
0139             ingenic_early_console_setup);
0140
0141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
0142             ingenic_early_console_setup);
0143
0144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
0145             ingenic_early_console_setup);
0146
0147 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
0148 {
0149     int ier;
0150
0151     switch (offset) {
0152     case UART_FCR:
0153         /* UART module enable */
0154         value |= UART_FCR_UME;
0155         break;
0156
0157     case UART_IER:
0158         /*
0159          * Enable receive timeout interrupt with the receive line
0160          * status interrupt.
0161          */
0162         value |= (value & 0x4) << 2;
0163         break;
0164
0165     case UART_MCR:
0166         /*
0167          * If we have enabled modem status IRQs we should enable
0168          * modem mode.
0169          */
0170         ier = p->serial_in(p, UART_IER);
0171
0172         if (ier & UART_IER_MSI)
0173             value |= UART_MCR_MDCE | UART_MCR_FCM;
0174         else
0175             value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
0176         break;
0177
0178     default:
0179         break;
0180     }
0181
0182     writeb(value, p->membase + (offset << p->regshift));
0183 }
0184
0185 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
0186 {
0187     unsigned int value;
0188
0189     value = readb(p->membase + (offset << p->regshift));
0190
0191     /* Hide non-16550 compliant bits from higher levels */
0192     switch (offset) {
0193     case UART_FCR:
0194         value &= ~UART_FCR_UME;
0195         break;
0196
0197     case UART_MCR:
0198         value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
0199         break;
0200
0201     default:
0202         break;
0203     }
0204     return value;
0205 }
0206
0207 static int ingenic_uart_probe(struct platform_device *pdev)
0208 {
0209     struct uart_8250_port uart = {};
0210     struct ingenic_uart_data *data;
0211     const struct ingenic_uart_config *cdata;
0212     struct resource *regs;
0213     int irq, err, line;
0214
0215     cdata = of_device_get_match_data(&pdev->dev);
0216     if (!cdata) {
0217         dev_err(&pdev->dev, "Error: No device match found\n");
0218         return -ENODEV;
0219     }
0220
0221     irq = platform_get_irq(pdev, 0);
0222     if (irq < 0)
0223         return irq;
0224
0225     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0226     if (!regs) {
0227         dev_err(&pdev->dev, "no registers defined\n");
0228         return -EINVAL;
0229     }
0230
0231     data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
0232     if (!data)
0233         return -ENOMEM;
0234
0235     spin_lock_init(&uart.port.lock);
0236     uart.port.type = PORT_16550A;
0237     uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
0238     uart.port.iotype = UPIO_MEM;
0239     uart.port.mapbase = regs->start;
0240     uart.port.regshift = 2;
0241     uart.port.serial_out = ingenic_uart_serial_out;
0242     uart.port.serial_in = ingenic_uart_serial_in;
0243     uart.port.irq = irq;
0244     uart.port.dev = &pdev->dev;
0245     uart.port.fifosize = cdata->fifosize;
0246     uart.tx_loadsz = cdata->tx_loadsz;
0247     uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
0248
0249     /* Check for a fixed line number */
0250     line = of_alias_get_id(pdev->dev.of_node, "serial");
0251     if (line >= 0)
0252         uart.port.line = line;
0253
0254     uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
0255                      resource_size(regs));
0256     if (!uart.port.membase)
0257         return -ENOMEM;
0258
0259     data->clk_module = devm_clk_get(&pdev->dev, "module");
0260     if (IS_ERR(data->clk_module))
0261         return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
0262                      "unable to get module clock\n");
0263
0264     data->clk_baud = devm_clk_get(&pdev->dev, "baud");
0265     if (IS_ERR(data->clk_baud))
0266         return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
0267                      "unable to get baud clock\n");
0268
0269     err = clk_prepare_enable(data->clk_module);
0270     if (err) {
0271         dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
0272         goto out;
0273     }
0274
0275     err = clk_prepare_enable(data->clk_baud);
0276     if (err) {
0277         dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
0278         goto out_disable_moduleclk;
0279     }
0280     uart.port.uartclk = clk_get_rate(data->clk_baud);
0281
0282     data->line = serial8250_register_8250_port(&uart);
0283     if (data->line < 0) {
0284         err = data->line;
0285         goto out_disable_baudclk;
0286     }
0287
0288     platform_set_drvdata(pdev, data);
0289     return 0;
0290
0291 out_disable_baudclk:
0292     clk_disable_unprepare(data->clk_baud);
0293 out_disable_moduleclk:
0294     clk_disable_unprepare(data->clk_module);
0295 out:
0296     return err;
0297 }
0298
0299 static int ingenic_uart_remove(struct platform_device *pdev)
0300 {
0301     struct ingenic_uart_data *data = platform_get_drvdata(pdev);
0302
0303     serial8250_unregister_port(data->line);
0304     clk_disable_unprepare(data->clk_module);
0305     clk_disable_unprepare(data->clk_baud);
0306     return 0;
0307 }
0308
0309 static const struct ingenic_uart_config jz4740_uart_config = {
0310     .tx_loadsz = 8,
0311     .fifosize = 16,
0312 };
0313
0314 static const struct ingenic_uart_config jz4760_uart_config = {
0315     .tx_loadsz = 16,
0316     .fifosize = 32,
0317 };
0318
0319 static const struct ingenic_uart_config jz4780_uart_config = {
0320     .tx_loadsz = 32,
0321     .fifosize = 64,
0322 };
0323
0324 static const struct ingenic_uart_config x1000_uart_config = {
0325     .tx_loadsz = 32,
0326     .fifosize = 64,
0327 };
0328
0329 static const struct of_device_id of_match[] = {
0330     { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
0331     { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
0332     { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
0333     { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
0334     { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
0335     { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
0336     { /* sentinel */ }
0337 };
0338 MODULE_DEVICE_TABLE(of, of_match);
0339
0340 static struct platform_driver ingenic_uart_platform_driver = {
0341     .driver = {
0342         .name       = "ingenic-uart",
0343         .of_match_table = of_match,
0344     },
0345     .probe          = ingenic_uart_probe,
0346     .remove         = ingenic_uart_remove,
0347 };
0348
0349 module_platform_driver(ingenic_uart_platform_driver);
0350
0351 MODULE_AUTHOR("Paul Burton");
0352 MODULE_LICENSE("GPL");
0353 MODULE_DESCRIPTION("Ingenic SoC UART driver");