serial/8250/8250_fintek.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Probe for F81216A LPC to 4 UART
0004  *
0005  *  Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
0006  */
0007 #include <linux/module.h>
0008 #include <linux/pci.h>
0009 #include <linux/pnp.h>
0010 #include <linux/kernel.h>
0011 #include <linux/serial_core.h>
0012 #include <linux/irq.h>
0013 #include  "8250.h"
0014
0015 #define ADDR_PORT 0
0016 #define DATA_PORT 1
0017 #define EXIT_KEY 0xAA
0018 #define CHIP_ID1  0x20
0019 #define CHIP_ID2  0x21
0020 #define CHIP_ID_F81865 0x0407
0021 #define CHIP_ID_F81866 0x1010
0022 #define CHIP_ID_F81966 0x0215
0023 #define CHIP_ID_F81216AD 0x1602
0024 #define CHIP_ID_F81216H 0x0501
0025 #define CHIP_ID_F81216 0x0802
0026 #define VENDOR_ID1 0x23
0027 #define VENDOR_ID1_VAL 0x19
0028 #define VENDOR_ID2 0x24
0029 #define VENDOR_ID2_VAL 0x34
0030 #define IO_ADDR1 0x61
0031 #define IO_ADDR2 0x60
0032 #define LDN 0x7
0033
0034 #define FINTEK_IRQ_MODE 0x70
0035 #define IRQ_SHARE   BIT(4)
0036 #define IRQ_MODE_MASK   (BIT(6) | BIT(5))
0037 #define IRQ_LEVEL_LOW   0
0038 #define IRQ_EDGE_HIGH   BIT(5)
0039
0040 /*
0041  * F81216H clock source register, the value and mask is the same with F81866,
0042  * but it's on F0h.
0043  *
0044  * Clock speeds for UART (register F0h)
0045  * 00: 1.8432MHz.
0046  * 01: 18.432MHz.
0047  * 10: 24MHz.
0048  * 11: 14.769MHz.
0049  */
0050 #define RS485  0xF0
0051 #define RTS_INVERT BIT(5)
0052 #define RS485_URA BIT(4)
0053 #define RXW4C_IRA BIT(3)
0054 #define TXW4C_IRA BIT(2)
0055
0056 #define FIFO_CTRL       0xF6
0057 #define FIFO_MODE_MASK      (BIT(1) | BIT(0))
0058 #define FIFO_MODE_128       (BIT(1) | BIT(0))
0059 #define RXFTHR_MODE_MASK    (BIT(5) | BIT(4))
0060 #define RXFTHR_MODE_4X      BIT(5)
0061
0062 #define F81216_LDN_LOW  0x0
0063 #define F81216_LDN_HIGH 0x4
0064
0065 /*
0066  * F81866/966 registers
0067  *
0068  * The IRQ setting mode of F81866/966 is not the same with F81216 series.
0069  *  Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
0070  *  Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
0071  *
0072  * Clock speeds for UART (register F2h)
0073  * 00: 1.8432MHz.
0074  * 01: 18.432MHz.
0075  * 10: 24MHz.
0076  * 11: 14.769MHz.
0077  */
0078 #define F81866_IRQ_MODE     0xf0
0079 #define F81866_IRQ_SHARE    BIT(0)
0080 #define F81866_IRQ_MODE0    BIT(1)
0081
0082 #define F81866_FIFO_CTRL    FIFO_CTRL
0083 #define F81866_IRQ_MODE1    BIT(3)
0084
0085 #define F81866_LDN_LOW      0x10
0086 #define F81866_LDN_HIGH     0x16
0087
0088 #define F81866_UART_CLK 0xF2
0089 #define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
0090 #define F81866_UART_CLK_1_8432MHZ 0
0091 #define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
0092 #define F81866_UART_CLK_18_432MHZ BIT(0)
0093 #define F81866_UART_CLK_24MHZ BIT(1)
0094
0095 struct fintek_8250 {
0096     u16 pid;
0097     u16 base_port;
0098     u8 index;
0099     u8 key;
0100 };
0101
0102 static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
0103 {
0104     outb(reg, pdata->base_port + ADDR_PORT);
0105     return inb(pdata->base_port + DATA_PORT);
0106 }
0107
0108 static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
0109 {
0110     outb(reg, pdata->base_port + ADDR_PORT);
0111     outb(data, pdata->base_port + DATA_PORT);
0112 }
0113
0114 static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
0115                    u8 data)
0116 {
0117     u8 tmp;
0118
0119     tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
0120     sio_write_reg(pdata, reg, tmp);
0121 }
0122
0123 static int fintek_8250_enter_key(u16 base_port, u8 key)
0124 {
0125     if (!request_muxed_region(base_port, 2, "8250_fintek"))
0126         return -EBUSY;
0127
0128     /* Force to deactive all SuperIO in this base_port */
0129     outb(EXIT_KEY, base_port + ADDR_PORT);
0130
0131     outb(key, base_port + ADDR_PORT);
0132     outb(key, base_port + ADDR_PORT);
0133     return 0;
0134 }
0135
0136 static void fintek_8250_exit_key(u16 base_port)
0137 {
0138
0139     outb(EXIT_KEY, base_port + ADDR_PORT);
0140     release_region(base_port + ADDR_PORT, 2);
0141 }
0142
0143 static int fintek_8250_check_id(struct fintek_8250 *pdata)
0144 {
0145     u16 chip;
0146
0147     if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
0148         return -ENODEV;
0149
0150     if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
0151         return -ENODEV;
0152
0153     chip = sio_read_reg(pdata, CHIP_ID1);
0154     chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
0155
0156     switch (chip) {
0157     case CHIP_ID_F81865:
0158     case CHIP_ID_F81866:
0159     case CHIP_ID_F81966:
0160     case CHIP_ID_F81216AD:
0161     case CHIP_ID_F81216H:
0162     case CHIP_ID_F81216:
0163         break;
0164     default:
0165         return -ENODEV;
0166     }
0167
0168     pdata->pid = chip;
0169     return 0;
0170 }
0171
0172 static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
0173                      int *max)
0174 {
0175     switch (pdata->pid) {
0176     case CHIP_ID_F81966:
0177     case CHIP_ID_F81865:
0178     case CHIP_ID_F81866:
0179         *min = F81866_LDN_LOW;
0180         *max = F81866_LDN_HIGH;
0181         return 0;
0182
0183     case CHIP_ID_F81216AD:
0184     case CHIP_ID_F81216H:
0185     case CHIP_ID_F81216:
0186         *min = F81216_LDN_LOW;
0187         *max = F81216_LDN_HIGH;
0188         return 0;
0189     }
0190
0191     return -ENODEV;
0192 }
0193
0194 static int fintek_8250_rs485_config(struct uart_port *port, struct ktermios *termios,
0195                   struct serial_rs485 *rs485)
0196 {
0197     uint8_t config = 0;
0198     struct fintek_8250 *pdata = port->private_data;
0199
0200     if (!pdata)
0201         return -EINVAL;
0202
0203
0204     if (rs485->flags & SER_RS485_ENABLED) {
0205         /* Hardware do not support same RTS level on send and receive */
0206         if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
0207             !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
0208             return -EINVAL;
0209         config |= RS485_URA;
0210     }
0211
0212     if (rs485->delay_rts_before_send) {
0213         rs485->delay_rts_before_send = 1;
0214         config |= TXW4C_IRA;
0215     }
0216
0217     if (rs485->delay_rts_after_send) {
0218         rs485->delay_rts_after_send = 1;
0219         config |= RXW4C_IRA;
0220     }
0221
0222     if (rs485->flags & SER_RS485_RTS_ON_SEND)
0223         config |= RTS_INVERT;
0224
0225     if (fintek_8250_enter_key(pdata->base_port, pdata->key))
0226         return -EBUSY;
0227
0228     sio_write_reg(pdata, LDN, pdata->index);
0229     sio_write_reg(pdata, RS485, config);
0230     fintek_8250_exit_key(pdata->base_port);
0231
0232     return 0;
0233 }
0234
0235 static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
0236 {
0237     sio_write_reg(pdata, LDN, pdata->index);
0238
0239     switch (pdata->pid) {
0240     case CHIP_ID_F81966:
0241     case CHIP_ID_F81866:
0242         sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
0243                    0);
0244         fallthrough;
0245     case CHIP_ID_F81865:
0246         sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
0247                    F81866_IRQ_SHARE);
0248         sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
0249                    is_level ? 0 : F81866_IRQ_MODE0);
0250         break;
0251
0252     case CHIP_ID_F81216AD:
0253     case CHIP_ID_F81216H:
0254     case CHIP_ID_F81216:
0255         sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
0256                    IRQ_SHARE);
0257         sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
0258                    is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
0259         break;
0260     }
0261 }
0262
0263 static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
0264 {
0265     switch (pdata->pid) {
0266     case CHIP_ID_F81216H: /* 128Bytes FIFO */
0267     case CHIP_ID_F81966:
0268     case CHIP_ID_F81866:
0269         sio_write_mask_reg(pdata, FIFO_CTRL,
0270                    FIFO_MODE_MASK | RXFTHR_MODE_MASK,
0271                    FIFO_MODE_128 | RXFTHR_MODE_4X);
0272         break;
0273
0274     default: /* Default 16Bytes FIFO */
0275         break;
0276     }
0277 }
0278
0279 static void fintek_8250_set_termios(struct uart_port *port,
0280                     struct ktermios *termios,
0281                     struct ktermios *old)
0282 {
0283     struct fintek_8250 *pdata = port->private_data;
0284     unsigned int baud = tty_termios_baud_rate(termios);
0285     int i;
0286     u8 reg;
0287     static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
0288     static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
0289             F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
0290             F81866_UART_CLK_24MHZ };
0291
0292     /*
0293      * We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
0294      * crash on baudrate_table[i] % baud with "division by zero".
0295      */
0296     if (!baud)
0297         goto exit;
0298
0299     switch (pdata->pid) {
0300     case CHIP_ID_F81216H:
0301         reg = RS485;
0302         break;
0303     case CHIP_ID_F81966:
0304     case CHIP_ID_F81866:
0305         reg = F81866_UART_CLK;
0306         break;
0307     default:
0308         /* Don't change clocksource with unknown PID */
0309         dev_warn(port->dev,
0310             "%s: pid: %x Not support. use default set_termios.\n",
0311             __func__, pdata->pid);
0312         goto exit;
0313     }
0314
0315     for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
0316         if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
0317             continue;
0318
0319         if (port->uartclk == baudrate_table[i] * 16)
0320             break;
0321
0322         if (fintek_8250_enter_key(pdata->base_port, pdata->key))
0323             continue;
0324
0325         port->uartclk = baudrate_table[i] * 16;
0326
0327         sio_write_reg(pdata, LDN, pdata->index);
0328         sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
0329                 clock_table[i]);
0330
0331         fintek_8250_exit_key(pdata->base_port);
0332         break;
0333     }
0334
0335     if (i == ARRAY_SIZE(baudrate_table)) {
0336         baud = tty_termios_baud_rate(old);
0337         tty_termios_encode_baud_rate(termios, baud, baud);
0338     }
0339
0340 exit:
0341     serial8250_do_set_termios(port, termios, old);
0342 }
0343
0344 static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
0345 {
0346     struct fintek_8250 *pdata = uart->port.private_data;
0347
0348     switch (pdata->pid) {
0349     case CHIP_ID_F81216H:
0350     case CHIP_ID_F81966:
0351     case CHIP_ID_F81866:
0352         uart->port.set_termios = fintek_8250_set_termios;
0353         break;
0354
0355     default:
0356         break;
0357     }
0358 }
0359
0360 static int probe_setup_port(struct fintek_8250 *pdata,
0361                     struct uart_8250_port *uart)
0362 {
0363     static const u16 addr[] = {0x4e, 0x2e};
0364     static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
0365     struct irq_data *irq_data;
0366     bool level_mode = false;
0367     int i, j, k, min, max;
0368
0369     for (i = 0; i < ARRAY_SIZE(addr); i++) {
0370         for (j = 0; j < ARRAY_SIZE(keys); j++) {
0371             pdata->base_port = addr[i];
0372             pdata->key = keys[j];
0373
0374             if (fintek_8250_enter_key(addr[i], keys[j]))
0375                 continue;
0376             if (fintek_8250_check_id(pdata) ||
0377                 fintek_8250_get_ldn_range(pdata, &min, &max)) {
0378                 fintek_8250_exit_key(addr[i]);
0379                 continue;
0380             }
0381
0382             for (k = min; k < max; k++) {
0383                 u16 aux;
0384
0385                 sio_write_reg(pdata, LDN, k);
0386                 aux = sio_read_reg(pdata, IO_ADDR1);
0387                 aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
0388                 if (aux != uart->port.iobase)
0389                     continue;
0390
0391                 pdata->index = k;
0392
0393                 irq_data = irq_get_irq_data(uart->port.irq);
0394                 if (irq_data)
0395                     level_mode =
0396                         irqd_is_level_type(irq_data);
0397
0398                 fintek_8250_set_irq_mode(pdata, level_mode);
0399                 fintek_8250_set_max_fifo(pdata);
0400
0401                 fintek_8250_exit_key(addr[i]);
0402
0403                 return 0;
0404             }
0405
0406             fintek_8250_exit_key(addr[i]);
0407         }
0408     }
0409
0410     return -ENODEV;
0411 }
0412
0413 /* Only the first port supports delays */
0414 static const struct serial_rs485 fintek_8250_rs485_supported_port0 = {
0415     .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
0416     .delay_rts_before_send = 1,
0417     .delay_rts_after_send = 1,
0418 };
0419
0420 static const struct serial_rs485 fintek_8250_rs485_supported = {
0421     .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
0422 };
0423
0424 static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
0425 {
0426     struct fintek_8250 *pdata = uart->port.private_data;
0427
0428     switch (pdata->pid) {
0429     case CHIP_ID_F81216AD:
0430     case CHIP_ID_F81216H:
0431     case CHIP_ID_F81966:
0432     case CHIP_ID_F81866:
0433     case CHIP_ID_F81865:
0434         uart->port.rs485_config = fintek_8250_rs485_config;
0435         if (!pdata->index)
0436             uart->port.rs485_supported = fintek_8250_rs485_supported_port0;
0437         else
0438             uart->port.rs485_supported = fintek_8250_rs485_supported;
0439         break;
0440
0441     default: /* No RS485 Auto direction functional */
0442         break;
0443     }
0444 }
0445
0446 int fintek_8250_probe(struct uart_8250_port *uart)
0447 {
0448     struct fintek_8250 *pdata;
0449     struct fintek_8250 probe_data;
0450
0451     if (probe_setup_port(&probe_data, uart))
0452         return -ENODEV;
0453
0454     pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
0455     if (!pdata)
0456         return -ENOMEM;
0457
0458     memcpy(pdata, &probe_data, sizeof(probe_data));
0459     uart->port.private_data = pdata;
0460     fintek_8250_set_rs485_handler(uart);
0461     fintek_8250_set_termios_handler(uart);
0462
0463     return 0;
0464 }