serial/8250/8250_dwlib.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Synopsys DesignWare 8250 library. */
0003
0004 #include <linux/bitops.h>
0005 #include <linux/bitfield.h>
0006 #include <linux/delay.h>
0007 #include <linux/device.h>
0008 #include <linux/kernel.h>
0009 #include <linux/math.h>
0010 #include <linux/property.h>
0011 #include <linux/serial_8250.h>
0012 #include <linux/serial_core.h>
0013
0014 #include "8250_dwlib.h"
0015
0016 /* Offsets for the DesignWare specific registers */
0017 #define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
0018 #define DW_UART_DE_EN   0xb0 /* Driver Output Enable Register */
0019 #define DW_UART_RE_EN   0xb4 /* Receiver Output Enable Register */
0020 #define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
0021 #define DW_UART_RAR 0xc4 /* Receive Address Register */
0022 #define DW_UART_TAR 0xc8 /* Transmit Address Register */
0023 #define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
0024 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
0025 #define DW_UART_UCV 0xf8 /* UART Component Version */
0026
0027 /* Receive / Transmit Address Register bits */
0028 #define DW_UART_ADDR_MASK       GENMASK(7, 0)
0029
0030 /* Line Status Register bits */
0031 #define DW_UART_LSR_ADDR_RCVD       BIT(8)
0032
0033 /* Transceiver Control Register bits */
0034 #define DW_UART_TCR_RS485_EN        BIT(0)
0035 #define DW_UART_TCR_RE_POL      BIT(1)
0036 #define DW_UART_TCR_DE_POL      BIT(2)
0037 #define DW_UART_TCR_XFER_MODE       GENMASK(4, 3)
0038 #define DW_UART_TCR_XFER_MODE_DE_DURING_RE  FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
0039 #define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE   FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
0040 #define DW_UART_TCR_XFER_MODE_DE_OR_RE      FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
0041
0042 /* Line Extended Control Register bits */
0043 #define DW_UART_LCR_EXT_DLS_E       BIT(0)
0044 #define DW_UART_LCR_EXT_ADDR_MATCH  BIT(1)
0045 #define DW_UART_LCR_EXT_SEND_ADDR   BIT(2)
0046 #define DW_UART_LCR_EXT_TRANSMIT_MODE   BIT(3)
0047
0048 /* Component Parameter Register bits */
0049 #define DW_UART_CPR_ABP_DATA_WIDTH  GENMASK(1, 0)
0050 #define DW_UART_CPR_AFCE_MODE       BIT(4)
0051 #define DW_UART_CPR_THRE_MODE       BIT(5)
0052 #define DW_UART_CPR_SIR_MODE        BIT(6)
0053 #define DW_UART_CPR_SIR_LP_MODE     BIT(7)
0054 #define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
0055 #define DW_UART_CPR_FIFO_ACCESS     BIT(9)
0056 #define DW_UART_CPR_FIFO_STAT       BIT(10)
0057 #define DW_UART_CPR_SHADOW      BIT(11)
0058 #define DW_UART_CPR_ENCODED_PARMS   BIT(12)
0059 #define DW_UART_CPR_DMA_EXTRA       BIT(13)
0060 #define DW_UART_CPR_FIFO_MODE       GENMASK(23, 16)
0061
0062 /* Helper for FIFO size calculation */
0063 #define DW_UART_CPR_FIFO_SIZE(a)    (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
0064
0065 /*
0066  * divisor = div(I) + div(F)
0067  * "I" means integer, "F" means fractional
0068  * quot = div(I) = clk / (16 * baud)
0069  * frac = div(F) * 2^dlf_size
0070  *
0071  * let rem = clk % (16 * baud)
0072  * we have: div(F) * (16 * baud) = rem
0073  * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
0074  */
0075 static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud,
0076                        unsigned int *frac)
0077 {
0078     unsigned int quot, rem, base_baud = baud * 16;
0079     struct dw8250_port_data *d = p->private_data;
0080
0081     quot = p->uartclk / base_baud;
0082     rem = p->uartclk % base_baud;
0083     *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
0084
0085     return quot;
0086 }
0087
0088 static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
0089                    unsigned int quot, unsigned int quot_frac)
0090 {
0091     dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
0092     serial8250_do_set_divisor(p, baud, quot, quot_frac);
0093 }
0094
0095 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old)
0096 {
0097     p->status &= ~UPSTAT_AUTOCTS;
0098     if (termios->c_cflag & CRTSCTS)
0099         p->status |= UPSTAT_AUTOCTS;
0100
0101     serial8250_do_set_termios(p, termios, old);
0102
0103     /* Filter addresses which have 9th bit set */
0104     p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD;
0105     p->read_status_mask |= DW_UART_LSR_ADDR_RCVD;
0106 }
0107 EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
0108
0109 /*
0110  * Wait until re is de-asserted for sure. An ongoing receive will keep
0111  * re asserted until end of frame. Without BUSY indication available,
0112  * only available course of action is to wait for the time it takes to
0113  * receive one frame (there might nothing to receive but w/o BUSY the
0114  * driver cannot know).
0115  */
0116 static void dw8250_wait_re_deassert(struct uart_port *p)
0117 {
0118     ndelay(p->frame_time);
0119 }
0120
0121 static void dw8250_update_rar(struct uart_port *p, u32 addr)
0122 {
0123     u32 re_en = dw8250_readl_ext(p, DW_UART_RE_EN);
0124
0125     /*
0126      * RAR shouldn't be changed while receiving. Thus, de-assert RE_EN
0127      * if asserted and wait.
0128      */
0129     if (re_en)
0130         dw8250_writel_ext(p, DW_UART_RE_EN, 0);
0131     dw8250_wait_re_deassert(p);
0132     dw8250_writel_ext(p, DW_UART_RAR, addr);
0133     if (re_en)
0134         dw8250_writel_ext(p, DW_UART_RE_EN, re_en);
0135 }
0136
0137 static void dw8250_rs485_set_addr(struct uart_port *p, struct serial_rs485 *rs485,
0138                   struct ktermios *termios)
0139 {
0140     u32 lcr = dw8250_readl_ext(p, DW_UART_LCR_EXT);
0141
0142     if (rs485->flags & SER_RS485_ADDRB) {
0143         lcr |= DW_UART_LCR_EXT_DLS_E;
0144         if (termios)
0145             termios->c_cflag |= ADDRB;
0146
0147         if (rs485->flags & SER_RS485_ADDR_RECV) {
0148             u32 delta = p->rs485.flags ^ rs485->flags;
0149
0150             /*
0151              * rs485 (param) is equal to uart_port's rs485 only during init
0152              * (during init, delta is not yet applicable).
0153              */
0154             if (unlikely(&p->rs485 == rs485))
0155                 delta = rs485->flags;
0156
0157             if ((delta & SER_RS485_ADDR_RECV) ||
0158                 (p->rs485.addr_recv != rs485->addr_recv))
0159                 dw8250_update_rar(p, rs485->addr_recv);
0160             lcr |= DW_UART_LCR_EXT_ADDR_MATCH;
0161         } else {
0162             lcr &= ~DW_UART_LCR_EXT_ADDR_MATCH;
0163         }
0164         if (rs485->flags & SER_RS485_ADDR_DEST) {
0165             /*
0166              * Don't skip writes here as another endpoint could
0167              * have changed communication line's destination
0168              * address in between.
0169              */
0170             dw8250_writel_ext(p, DW_UART_TAR, rs485->addr_dest);
0171             lcr |= DW_UART_LCR_EXT_SEND_ADDR;
0172         }
0173     } else {
0174         lcr = 0;
0175     }
0176     dw8250_writel_ext(p, DW_UART_LCR_EXT, lcr);
0177 }
0178
0179 static int dw8250_rs485_config(struct uart_port *p, struct ktermios *termios,
0180                    struct serial_rs485 *rs485)
0181 {
0182     u32 tcr;
0183
0184     tcr = dw8250_readl_ext(p, DW_UART_TCR);
0185     tcr &= ~DW_UART_TCR_XFER_MODE;
0186
0187     if (rs485->flags & SER_RS485_ENABLED) {
0188         tcr |= DW_UART_TCR_RS485_EN;
0189
0190         if (rs485->flags & SER_RS485_RX_DURING_TX)
0191             tcr |= DW_UART_TCR_XFER_MODE_DE_DURING_RE;
0192         else
0193             tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE;
0194         dw8250_writel_ext(p, DW_UART_DE_EN, 1);
0195         dw8250_writel_ext(p, DW_UART_RE_EN, 1);
0196     } else {
0197         if (termios)
0198             termios->c_cflag &= ~ADDRB;
0199
0200         tcr &= ~DW_UART_TCR_RS485_EN;
0201     }
0202
0203     /* Reset to default polarity */
0204     tcr |= DW_UART_TCR_DE_POL;
0205     tcr &= ~DW_UART_TCR_RE_POL;
0206
0207     if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
0208         tcr &= ~DW_UART_TCR_DE_POL;
0209     if (device_property_read_bool(p->dev, "rs485-rx-active-high"))
0210         tcr |= DW_UART_TCR_RE_POL;
0211
0212     dw8250_writel_ext(p, DW_UART_TCR, tcr);
0213
0214     /* Addressing mode can only be set up after TCR */
0215     if (rs485->flags & SER_RS485_ENABLED)
0216         dw8250_rs485_set_addr(p, rs485, termios);
0217
0218     return 0;
0219 }
0220
0221 /*
0222  * Tests if RE_EN register can have non-zero value to see if RS-485 HW support
0223  * is present.
0224  */
0225 static bool dw8250_detect_rs485_hw(struct uart_port *p)
0226 {
0227     u32 reg;
0228
0229     dw8250_writel_ext(p, DW_UART_RE_EN, 1);
0230     reg = dw8250_readl_ext(p, DW_UART_RE_EN);
0231     dw8250_writel_ext(p, DW_UART_RE_EN, 0);
0232     return reg;
0233 }
0234
0235 static const struct serial_rs485 dw8250_rs485_supported = {
0236     .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_RTS_ON_SEND |
0237          SER_RS485_RTS_AFTER_SEND | SER_RS485_ADDRB | SER_RS485_ADDR_RECV |
0238          SER_RS485_ADDR_DEST,
0239 };
0240
0241 void dw8250_setup_port(struct uart_port *p)
0242 {
0243     struct dw8250_port_data *pd = p->private_data;
0244     struct dw8250_data *data = to_dw8250_data(pd);
0245     struct uart_8250_port *up = up_to_u8250p(p);
0246     u32 reg;
0247
0248     pd->hw_rs485_support = dw8250_detect_rs485_hw(p);
0249     if (pd->hw_rs485_support) {
0250         p->rs485_config = dw8250_rs485_config;
0251         up->lsr_save_mask = LSR_SAVE_FLAGS | DW_UART_LSR_ADDR_RCVD;
0252         p->rs485_supported = dw8250_rs485_supported;
0253     } else {
0254         p->rs485_config = serial8250_em485_config;
0255         p->rs485_supported = serial8250_em485_supported;
0256         up->rs485_start_tx = serial8250_em485_start_tx;
0257         up->rs485_stop_tx = serial8250_em485_stop_tx;
0258     }
0259     up->capabilities |= UART_CAP_NOTEMT;
0260
0261     /*
0262      * If the Component Version Register returns zero, we know that
0263      * ADDITIONAL_FEATURES are not enabled. No need to go any further.
0264      */
0265     reg = dw8250_readl_ext(p, DW_UART_UCV);
0266     if (!reg)
0267         return;
0268
0269     dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
0270         (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
0271
0272     dw8250_writel_ext(p, DW_UART_DLF, ~0U);
0273     reg = dw8250_readl_ext(p, DW_UART_DLF);
0274     dw8250_writel_ext(p, DW_UART_DLF, 0);
0275
0276     if (reg) {
0277         pd->dlf_size = fls(reg);
0278         p->get_divisor = dw8250_get_divisor;
0279         p->set_divisor = dw8250_set_divisor;
0280     }
0281
0282     reg = dw8250_readl_ext(p, DW_UART_CPR);
0283     if (!reg) {
0284         reg = data->pdata->cpr_val;
0285         dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
0286     }
0287     if (!reg)
0288         return;
0289
0290     /* Select the type based on FIFO */
0291     if (reg & DW_UART_CPR_FIFO_MODE) {
0292         p->type = PORT_16550A;
0293         p->flags |= UPF_FIXED_TYPE;
0294         p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
0295         up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;
0296     }
0297
0298     if (reg & DW_UART_CPR_AFCE_MODE)
0299         up->capabilities |= UART_CAP_AFE;
0300
0301     if (reg & DW_UART_CPR_SIR_MODE)
0302         up->capabilities |= UART_CAP_IRDA;
0303 }
0304 EXPORT_SYMBOL_GPL(dw8250_setup_port);