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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Synopsys DesignWare 8250 driver.
0004  *
0005  * Copyright 2011 Picochip, Jamie Iles.
0006  * Copyright 2013 Intel Corporation
0007  *
0008  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
0009  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
0010  * raised, the LCR needs to be rewritten and the uart status register read.
0011  */
0012 #include <linux/acpi.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/device.h>
0016 #include <linux/io.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/module.h>
0019 #include <linux/notifier.h>
0020 #include <linux/of.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/property.h>
0024 #include <linux/reset.h>
0025 #include <linux/slab.h>
0026 #include <linux/workqueue.h>
0027 
0028 #include <asm/byteorder.h>
0029 
0030 #include <linux/serial_8250.h>
0031 #include <linux/serial_reg.h>
0032 
0033 #include "8250_dwlib.h"
0034 
0035 /* Offsets for the DesignWare specific registers */
0036 #define DW_UART_USR 0x1f /* UART Status Register */
0037 #define DW_UART_DMASA   0xa8 /* DMA Software Ack */
0038 
0039 #define OCTEON_UART_USR 0x27 /* UART Status Register */
0040 
0041 #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
0042 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
0043 
0044 /* DesignWare specific register fields */
0045 #define DW_UART_MCR_SIRE        BIT(6)
0046 
0047 /* Renesas specific register fields */
0048 #define RZN1_UART_xDMACR_DMA_EN     BIT(0)
0049 #define RZN1_UART_xDMACR_1_WORD_BURST   (0 << 1)
0050 #define RZN1_UART_xDMACR_4_WORD_BURST   (1 << 1)
0051 #define RZN1_UART_xDMACR_8_WORD_BURST   (2 << 1)
0052 #define RZN1_UART_xDMACR_BLK_SZ(x)  ((x) << 3)
0053 
0054 /* Quirks */
0055 #define DW_UART_QUIRK_OCTEON        BIT(0)
0056 #define DW_UART_QUIRK_ARMADA_38X    BIT(1)
0057 #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
0058 #define DW_UART_QUIRK_IS_DMA_FC     BIT(3)
0059 
0060 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
0061 {
0062     return container_of(nb, struct dw8250_data, clk_notifier);
0063 }
0064 
0065 static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
0066 {
0067     return container_of(work, struct dw8250_data, clk_work);
0068 }
0069 
0070 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
0071 {
0072     struct dw8250_data *d = to_dw8250_data(p->private_data);
0073 
0074     /* Override any modem control signals if needed */
0075     if (offset == UART_MSR) {
0076         value |= d->msr_mask_on;
0077         value &= ~d->msr_mask_off;
0078     }
0079 
0080     return value;
0081 }
0082 
0083 static void dw8250_force_idle(struct uart_port *p)
0084 {
0085     struct uart_8250_port *up = up_to_u8250p(p);
0086     unsigned int lsr;
0087 
0088     serial8250_clear_and_reinit_fifos(up);
0089 
0090     /*
0091      * With PSLVERR_RESP_EN parameter set to 1, the device generates an
0092      * error response when an attempt to read an empty RBR with FIFO
0093      * enabled.
0094      */
0095     if (up->fcr & UART_FCR_ENABLE_FIFO) {
0096         lsr = p->serial_in(p, UART_LSR);
0097         if (!(lsr & UART_LSR_DR))
0098             return;
0099     }
0100 
0101     (void)p->serial_in(p, UART_RX);
0102 }
0103 
0104 static void dw8250_check_lcr(struct uart_port *p, int value)
0105 {
0106     void __iomem *offset = p->membase + (UART_LCR << p->regshift);
0107     int tries = 1000;
0108 
0109     /* Make sure LCR write wasn't ignored */
0110     while (tries--) {
0111         unsigned int lcr = p->serial_in(p, UART_LCR);
0112 
0113         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
0114             return;
0115 
0116         dw8250_force_idle(p);
0117 
0118 #ifdef CONFIG_64BIT
0119         if (p->type == PORT_OCTEON)
0120             __raw_writeq(value & 0xff, offset);
0121         else
0122 #endif
0123         if (p->iotype == UPIO_MEM32)
0124             writel(value, offset);
0125         else if (p->iotype == UPIO_MEM32BE)
0126             iowrite32be(value, offset);
0127         else
0128             writeb(value, offset);
0129     }
0130     /*
0131      * FIXME: this deadlocks if port->lock is already held
0132      * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
0133      */
0134 }
0135 
0136 /* Returns once the transmitter is empty or we run out of retries */
0137 static void dw8250_tx_wait_empty(struct uart_port *p)
0138 {
0139     struct uart_8250_port *up = up_to_u8250p(p);
0140     unsigned int tries = 20000;
0141     unsigned int delay_threshold = tries - 1000;
0142     unsigned int lsr;
0143 
0144     while (tries--) {
0145         lsr = readb (p->membase + (UART_LSR << p->regshift));
0146         up->lsr_saved_flags |= lsr & up->lsr_save_mask;
0147 
0148         if (lsr & UART_LSR_TEMT)
0149             break;
0150 
0151         /* The device is first given a chance to empty without delay,
0152          * to avoid slowdowns at high bitrates. If after 1000 tries
0153          * the buffer has still not emptied, allow more time for low-
0154          * speed links. */
0155         if (tries < delay_threshold)
0156             udelay (1);
0157     }
0158 }
0159 
0160 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
0161 {
0162     struct dw8250_data *d = to_dw8250_data(p->private_data);
0163 
0164     writeb(value, p->membase + (offset << p->regshift));
0165 
0166     if (offset == UART_LCR && !d->uart_16550_compatible)
0167         dw8250_check_lcr(p, value);
0168 }
0169 
0170 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
0171 {
0172     /* Allow the TX to drain before we reconfigure */
0173     if (offset == UART_LCR)
0174         dw8250_tx_wait_empty(p);
0175 
0176     dw8250_serial_out(p, offset, value);
0177 }
0178 
0179 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
0180 {
0181     unsigned int value = readb(p->membase + (offset << p->regshift));
0182 
0183     return dw8250_modify_msr(p, offset, value);
0184 }
0185 
0186 #ifdef CONFIG_64BIT
0187 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
0188 {
0189     unsigned int value;
0190 
0191     value = (u8)__raw_readq(p->membase + (offset << p->regshift));
0192 
0193     return dw8250_modify_msr(p, offset, value);
0194 }
0195 
0196 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
0197 {
0198     struct dw8250_data *d = to_dw8250_data(p->private_data);
0199 
0200     value &= 0xff;
0201     __raw_writeq(value, p->membase + (offset << p->regshift));
0202     /* Read back to ensure register write ordering. */
0203     __raw_readq(p->membase + (UART_LCR << p->regshift));
0204 
0205     if (offset == UART_LCR && !d->uart_16550_compatible)
0206         dw8250_check_lcr(p, value);
0207 }
0208 #endif /* CONFIG_64BIT */
0209 
0210 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
0211 {
0212     struct dw8250_data *d = to_dw8250_data(p->private_data);
0213 
0214     writel(value, p->membase + (offset << p->regshift));
0215 
0216     if (offset == UART_LCR && !d->uart_16550_compatible)
0217         dw8250_check_lcr(p, value);
0218 }
0219 
0220 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
0221 {
0222     unsigned int value = readl(p->membase + (offset << p->regshift));
0223 
0224     return dw8250_modify_msr(p, offset, value);
0225 }
0226 
0227 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
0228 {
0229     struct dw8250_data *d = to_dw8250_data(p->private_data);
0230 
0231     iowrite32be(value, p->membase + (offset << p->regshift));
0232 
0233     if (offset == UART_LCR && !d->uart_16550_compatible)
0234         dw8250_check_lcr(p, value);
0235 }
0236 
0237 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
0238 {
0239        unsigned int value = ioread32be(p->membase + (offset << p->regshift));
0240 
0241        return dw8250_modify_msr(p, offset, value);
0242 }
0243 
0244 
0245 static int dw8250_handle_irq(struct uart_port *p)
0246 {
0247     struct uart_8250_port *up = up_to_u8250p(p);
0248     struct dw8250_data *d = to_dw8250_data(p->private_data);
0249     unsigned int iir = p->serial_in(p, UART_IIR);
0250     bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
0251     unsigned int quirks = d->pdata->quirks;
0252     unsigned int status;
0253     unsigned long flags;
0254 
0255     /*
0256      * There are ways to get Designware-based UARTs into a state where
0257      * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
0258      * data available.  If we see such a case then we'll do a bogus
0259      * read.  If we don't do this then the "RX TIMEOUT" interrupt will
0260      * fire forever.
0261      *
0262      * This problem has only been observed so far when not in DMA mode
0263      * so we limit the workaround only to non-DMA mode.
0264      */
0265     if (!up->dma && rx_timeout) {
0266         spin_lock_irqsave(&p->lock, flags);
0267         status = serial_lsr_in(up);
0268 
0269         if (!(status & (UART_LSR_DR | UART_LSR_BI)))
0270             (void) p->serial_in(p, UART_RX);
0271 
0272         spin_unlock_irqrestore(&p->lock, flags);
0273     }
0274 
0275     /* Manually stop the Rx DMA transfer when acting as flow controller */
0276     if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
0277         spin_lock_irqsave(&p->lock, flags);
0278         status = serial_lsr_in(up);
0279         spin_unlock_irqrestore(&p->lock, flags);
0280 
0281         if (status & (UART_LSR_DR | UART_LSR_BI)) {
0282             dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
0283             dw8250_writel_ext(p, DW_UART_DMASA, 1);
0284         }
0285     }
0286 
0287     if (serial8250_handle_irq(p, iir))
0288         return 1;
0289 
0290     if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
0291         /* Clear the USR */
0292         (void)p->serial_in(p, d->pdata->usr_reg);
0293 
0294         return 1;
0295     }
0296 
0297     return 0;
0298 }
0299 
0300 static void dw8250_clk_work_cb(struct work_struct *work)
0301 {
0302     struct dw8250_data *d = work_to_dw8250_data(work);
0303     struct uart_8250_port *up;
0304     unsigned long rate;
0305 
0306     rate = clk_get_rate(d->clk);
0307     if (rate <= 0)
0308         return;
0309 
0310     up = serial8250_get_port(d->data.line);
0311 
0312     serial8250_update_uartclk(&up->port, rate);
0313 }
0314 
0315 static int dw8250_clk_notifier_cb(struct notifier_block *nb,
0316                   unsigned long event, void *data)
0317 {
0318     struct dw8250_data *d = clk_to_dw8250_data(nb);
0319 
0320     /*
0321      * We have no choice but to defer the uartclk update due to two
0322      * deadlocks. First one is caused by a recursive mutex lock which
0323      * happens when clk_set_rate() is called from dw8250_set_termios().
0324      * Second deadlock is more tricky and is caused by an inverted order of
0325      * the clk and tty-port mutexes lock. It happens if clock rate change
0326      * is requested asynchronously while set_termios() is executed between
0327      * tty-port mutex lock and clk_set_rate() function invocation and
0328      * vise-versa. Anyway if we didn't have the reference clock alteration
0329      * in the dw8250_set_termios() method we wouldn't have needed this
0330      * deferred event handling complication.
0331      */
0332     if (event == POST_RATE_CHANGE) {
0333         queue_work(system_unbound_wq, &d->clk_work);
0334         return NOTIFY_OK;
0335     }
0336 
0337     return NOTIFY_DONE;
0338 }
0339 
0340 static void
0341 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
0342 {
0343     if (!state)
0344         pm_runtime_get_sync(port->dev);
0345 
0346     serial8250_do_pm(port, state, old);
0347 
0348     if (state)
0349         pm_runtime_put_sync_suspend(port->dev);
0350 }
0351 
0352 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
0353                    struct ktermios *old)
0354 {
0355     unsigned long newrate = tty_termios_baud_rate(termios) * 16;
0356     struct dw8250_data *d = to_dw8250_data(p->private_data);
0357     long rate;
0358     int ret;
0359 
0360     clk_disable_unprepare(d->clk);
0361     rate = clk_round_rate(d->clk, newrate);
0362     if (rate > 0) {
0363         /*
0364          * Note that any clock-notifer worker will block in
0365          * serial8250_update_uartclk() until we are done.
0366          */
0367         ret = clk_set_rate(d->clk, newrate);
0368         if (!ret)
0369             p->uartclk = rate;
0370     }
0371     clk_prepare_enable(d->clk);
0372 
0373     dw8250_do_set_termios(p, termios, old);
0374 }
0375 
0376 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
0377 {
0378     struct uart_8250_port *up = up_to_u8250p(p);
0379     unsigned int mcr = p->serial_in(p, UART_MCR);
0380 
0381     if (up->capabilities & UART_CAP_IRDA) {
0382         if (termios->c_line == N_IRDA)
0383             mcr |= DW_UART_MCR_SIRE;
0384         else
0385             mcr &= ~DW_UART_MCR_SIRE;
0386 
0387         p->serial_out(p, UART_MCR, mcr);
0388     }
0389     serial8250_do_set_ldisc(p, termios);
0390 }
0391 
0392 /*
0393  * dw8250_fallback_dma_filter will prevent the UART from getting just any free
0394  * channel on platforms that have DMA engines, but don't have any channels
0395  * assigned to the UART.
0396  *
0397  * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
0398  * core problem is fixed, this function is no longer needed.
0399  */
0400 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
0401 {
0402     return false;
0403 }
0404 
0405 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
0406 {
0407     return param == chan->device->dev;
0408 }
0409 
0410 static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
0411 {
0412     if (max_burst >= 8)
0413         return RZN1_UART_xDMACR_8_WORD_BURST;
0414     else if (max_burst >= 4)
0415         return RZN1_UART_xDMACR_4_WORD_BURST;
0416     else
0417         return RZN1_UART_xDMACR_1_WORD_BURST;
0418 }
0419 
0420 static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
0421 {
0422     struct uart_port *up = &p->port;
0423     struct uart_8250_dma *dma = p->dma;
0424     u32 val;
0425 
0426     dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
0427     val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
0428           RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
0429           RZN1_UART_xDMACR_DMA_EN;
0430     dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
0431 }
0432 
0433 static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
0434 {
0435     struct uart_port *up = &p->port;
0436     struct uart_8250_dma *dma = p->dma;
0437     u32 val;
0438 
0439     dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
0440     val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
0441           RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
0442           RZN1_UART_xDMACR_DMA_EN;
0443     dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
0444 }
0445 
0446 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
0447 {
0448     struct device_node *np = p->dev->of_node;
0449 
0450     if (np) {
0451         unsigned int quirks = data->pdata->quirks;
0452         int id;
0453 
0454         /* get index of serial line, if found in DT aliases */
0455         id = of_alias_get_id(np, "serial");
0456         if (id >= 0)
0457             p->line = id;
0458 #ifdef CONFIG_64BIT
0459         if (quirks & DW_UART_QUIRK_OCTEON) {
0460             p->serial_in = dw8250_serial_inq;
0461             p->serial_out = dw8250_serial_outq;
0462             p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
0463             p->type = PORT_OCTEON;
0464             data->skip_autocfg = true;
0465         }
0466 #endif
0467 
0468         if (of_device_is_big_endian(np)) {
0469             p->iotype = UPIO_MEM32BE;
0470             p->serial_in = dw8250_serial_in32be;
0471             p->serial_out = dw8250_serial_out32be;
0472         }
0473 
0474         if (quirks & DW_UART_QUIRK_ARMADA_38X)
0475             p->serial_out = dw8250_serial_out38x;
0476         if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
0477             p->set_termios = dw8250_do_set_termios;
0478         if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
0479             data->data.dma.txconf.device_fc = 1;
0480             data->data.dma.rxconf.device_fc = 1;
0481             data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
0482             data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
0483         }
0484 
0485     } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
0486         p->iotype = UPIO_MEM32;
0487         p->regshift = 2;
0488         p->serial_in = dw8250_serial_in32;
0489         data->uart_16550_compatible = true;
0490     }
0491 
0492     /* Platforms with iDMA 64-bit */
0493     if (platform_get_resource_byname(to_platform_device(p->dev),
0494                      IORESOURCE_MEM, "lpss_priv")) {
0495         data->data.dma.rx_param = p->dev->parent;
0496         data->data.dma.tx_param = p->dev->parent;
0497         data->data.dma.fn = dw8250_idma_filter;
0498     }
0499 }
0500 
0501 static void dw8250_clk_disable_unprepare(void *data)
0502 {
0503     clk_disable_unprepare(data);
0504 }
0505 
0506 static void dw8250_reset_control_assert(void *data)
0507 {
0508     reset_control_assert(data);
0509 }
0510 
0511 static int dw8250_probe(struct platform_device *pdev)
0512 {
0513     struct uart_8250_port uart = {}, *up = &uart;
0514     struct uart_port *p = &up->port;
0515     struct device *dev = &pdev->dev;
0516     struct dw8250_data *data;
0517     struct resource *regs;
0518     int irq;
0519     int err;
0520     u32 val;
0521 
0522     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0523     if (!regs)
0524         return dev_err_probe(dev, -EINVAL, "no registers defined\n");
0525 
0526     irq = platform_get_irq(pdev, 0);
0527     if (irq < 0)
0528         return irq;
0529 
0530     spin_lock_init(&p->lock);
0531     p->mapbase  = regs->start;
0532     p->irq      = irq;
0533     p->handle_irq   = dw8250_handle_irq;
0534     p->pm       = dw8250_do_pm;
0535     p->type     = PORT_8250;
0536     p->flags    = UPF_SHARE_IRQ | UPF_FIXED_PORT;
0537     p->dev      = dev;
0538     p->iotype   = UPIO_MEM;
0539     p->serial_in    = dw8250_serial_in;
0540     p->serial_out   = dw8250_serial_out;
0541     p->set_ldisc    = dw8250_set_ldisc;
0542     p->set_termios  = dw8250_set_termios;
0543 
0544     p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
0545     if (!p->membase)
0546         return -ENOMEM;
0547 
0548     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0549     if (!data)
0550         return -ENOMEM;
0551 
0552     data->data.dma.fn = dw8250_fallback_dma_filter;
0553     data->pdata = device_get_match_data(p->dev);
0554     p->private_data = &data->data;
0555 
0556     data->uart_16550_compatible = device_property_read_bool(dev,
0557                         "snps,uart-16550-compatible");
0558 
0559     err = device_property_read_u32(dev, "reg-shift", &val);
0560     if (!err)
0561         p->regshift = val;
0562 
0563     err = device_property_read_u32(dev, "reg-io-width", &val);
0564     if (!err && val == 4) {
0565         p->iotype = UPIO_MEM32;
0566         p->serial_in = dw8250_serial_in32;
0567         p->serial_out = dw8250_serial_out32;
0568     }
0569 
0570     if (device_property_read_bool(dev, "dcd-override")) {
0571         /* Always report DCD as active */
0572         data->msr_mask_on |= UART_MSR_DCD;
0573         data->msr_mask_off |= UART_MSR_DDCD;
0574     }
0575 
0576     if (device_property_read_bool(dev, "dsr-override")) {
0577         /* Always report DSR as active */
0578         data->msr_mask_on |= UART_MSR_DSR;
0579         data->msr_mask_off |= UART_MSR_DDSR;
0580     }
0581 
0582     if (device_property_read_bool(dev, "cts-override")) {
0583         /* Always report CTS as active */
0584         data->msr_mask_on |= UART_MSR_CTS;
0585         data->msr_mask_off |= UART_MSR_DCTS;
0586     }
0587 
0588     if (device_property_read_bool(dev, "ri-override")) {
0589         /* Always report Ring indicator as inactive */
0590         data->msr_mask_off |= UART_MSR_RI;
0591         data->msr_mask_off |= UART_MSR_TERI;
0592     }
0593 
0594     /* Always ask for fixed clock rate from a property. */
0595     device_property_read_u32(dev, "clock-frequency", &p->uartclk);
0596 
0597     /* If there is separate baudclk, get the rate from it. */
0598     data->clk = devm_clk_get_optional(dev, "baudclk");
0599     if (data->clk == NULL)
0600         data->clk = devm_clk_get_optional(dev, NULL);
0601     if (IS_ERR(data->clk))
0602         return PTR_ERR(data->clk);
0603 
0604     INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
0605     data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
0606 
0607     err = clk_prepare_enable(data->clk);
0608     if (err)
0609         return dev_err_probe(dev, err, "could not enable optional baudclk\n");
0610 
0611     err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
0612     if (err)
0613         return err;
0614 
0615     if (data->clk)
0616         p->uartclk = clk_get_rate(data->clk);
0617 
0618     /* If no clock rate is defined, fail. */
0619     if (!p->uartclk)
0620         return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
0621 
0622     data->pclk = devm_clk_get_optional(dev, "apb_pclk");
0623     if (IS_ERR(data->pclk))
0624         return PTR_ERR(data->pclk);
0625 
0626     err = clk_prepare_enable(data->pclk);
0627     if (err)
0628         return dev_err_probe(dev, err, "could not enable apb_pclk\n");
0629 
0630     err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
0631     if (err)
0632         return err;
0633 
0634     data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
0635     if (IS_ERR(data->rst))
0636         return PTR_ERR(data->rst);
0637 
0638     reset_control_deassert(data->rst);
0639 
0640     err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
0641     if (err)
0642         return err;
0643 
0644     dw8250_quirks(p, data);
0645 
0646     /* If the Busy Functionality is not implemented, don't handle it */
0647     if (data->uart_16550_compatible)
0648         p->handle_irq = NULL;
0649 
0650     if (!data->skip_autocfg)
0651         dw8250_setup_port(p);
0652 
0653     /* If we have a valid fifosize, try hooking up DMA */
0654     if (p->fifosize) {
0655         data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
0656         data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
0657         up->dma = &data->data.dma;
0658     }
0659 
0660     data->data.line = serial8250_register_8250_port(up);
0661     if (data->data.line < 0)
0662         return data->data.line;
0663 
0664     /*
0665      * Some platforms may provide a reference clock shared between several
0666      * devices. In this case any clock state change must be known to the
0667      * UART port at least post factum.
0668      */
0669     if (data->clk) {
0670         err = clk_notifier_register(data->clk, &data->clk_notifier);
0671         if (err)
0672             return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
0673         queue_work(system_unbound_wq, &data->clk_work);
0674     }
0675 
0676     platform_set_drvdata(pdev, data);
0677 
0678     pm_runtime_set_active(dev);
0679     pm_runtime_enable(dev);
0680 
0681     return 0;
0682 }
0683 
0684 static int dw8250_remove(struct platform_device *pdev)
0685 {
0686     struct dw8250_data *data = platform_get_drvdata(pdev);
0687     struct device *dev = &pdev->dev;
0688 
0689     pm_runtime_get_sync(dev);
0690 
0691     if (data->clk) {
0692         clk_notifier_unregister(data->clk, &data->clk_notifier);
0693 
0694         flush_work(&data->clk_work);
0695     }
0696 
0697     serial8250_unregister_port(data->data.line);
0698 
0699     pm_runtime_disable(dev);
0700     pm_runtime_put_noidle(dev);
0701 
0702     return 0;
0703 }
0704 
0705 static int dw8250_suspend(struct device *dev)
0706 {
0707     struct dw8250_data *data = dev_get_drvdata(dev);
0708 
0709     serial8250_suspend_port(data->data.line);
0710 
0711     return 0;
0712 }
0713 
0714 static int dw8250_resume(struct device *dev)
0715 {
0716     struct dw8250_data *data = dev_get_drvdata(dev);
0717 
0718     serial8250_resume_port(data->data.line);
0719 
0720     return 0;
0721 }
0722 
0723 static int dw8250_runtime_suspend(struct device *dev)
0724 {
0725     struct dw8250_data *data = dev_get_drvdata(dev);
0726 
0727     clk_disable_unprepare(data->clk);
0728 
0729     clk_disable_unprepare(data->pclk);
0730 
0731     return 0;
0732 }
0733 
0734 static int dw8250_runtime_resume(struct device *dev)
0735 {
0736     struct dw8250_data *data = dev_get_drvdata(dev);
0737 
0738     clk_prepare_enable(data->pclk);
0739 
0740     clk_prepare_enable(data->clk);
0741 
0742     return 0;
0743 }
0744 
0745 static const struct dev_pm_ops dw8250_pm_ops = {
0746     SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
0747     RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
0748 };
0749 
0750 static const struct dw8250_platform_data dw8250_dw_apb = {
0751     .usr_reg = DW_UART_USR,
0752 };
0753 
0754 static const struct dw8250_platform_data dw8250_octeon_3860_data = {
0755     .usr_reg = OCTEON_UART_USR,
0756     .quirks = DW_UART_QUIRK_OCTEON,
0757 };
0758 
0759 static const struct dw8250_platform_data dw8250_armada_38x_data = {
0760     .usr_reg = DW_UART_USR,
0761     .quirks = DW_UART_QUIRK_ARMADA_38X,
0762 };
0763 
0764 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
0765     .usr_reg = DW_UART_USR,
0766     .cpr_val = 0x00012f32,
0767     .quirks = DW_UART_QUIRK_IS_DMA_FC,
0768 };
0769 
0770 static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
0771     .usr_reg = DW_UART_USR,
0772     .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
0773 };
0774 
0775 static const struct of_device_id dw8250_of_match[] = {
0776     { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
0777     { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
0778     { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
0779     { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
0780     { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
0781     { /* Sentinel */ }
0782 };
0783 MODULE_DEVICE_TABLE(of, dw8250_of_match);
0784 
0785 static const struct acpi_device_id dw8250_acpi_match[] = {
0786     { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
0787     { "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
0788     { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
0789     { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
0790     { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
0791     { "APMC0D08", (kernel_ulong_t)&dw8250_dw_apb},
0792     { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
0793     { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
0794     { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
0795     { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
0796     { "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
0797     { "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
0798     { },
0799 };
0800 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
0801 
0802 static struct platform_driver dw8250_platform_driver = {
0803     .driver = {
0804         .name       = "dw-apb-uart",
0805         .pm     = pm_ptr(&dw8250_pm_ops),
0806         .of_match_table = dw8250_of_match,
0807         .acpi_match_table = dw8250_acpi_match,
0808     },
0809     .probe          = dw8250_probe,
0810     .remove         = dw8250_remove,
0811 };
0812 
0813 module_platform_driver(dw8250_platform_driver);
0814 
0815 MODULE_AUTHOR("Jamie Iles");
0816 MODULE_LICENSE("GPL");
0817 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
0818 MODULE_ALIAS("platform:dw-apb-uart");
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