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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2020, Broadcom */
0003 /*
0004  * 8250-core based driver for Broadcom ns16550a UARTs
0005  *
0006  * This driver uses the standard 8250 driver core but adds additional
0007  * optional features including the ability to use a baud rate clock
0008  * mux for more accurate high speed baud rate selection and also
0009  * an optional DMA engine.
0010  *
0011  */
0012 
0013 #include <linux/module.h>
0014 #include <linux/types.h>
0015 #include <linux/tty.h>
0016 #include <linux/errno.h>
0017 #include <linux/device.h>
0018 #include <linux/io.h>
0019 #include <linux/of.h>
0020 #include <linux/dma-mapping.h>
0021 #include <linux/tty_flip.h>
0022 #include <linux/delay.h>
0023 #include <linux/clk.h>
0024 #include <linux/debugfs.h>
0025 
0026 #include "8250.h"
0027 
0028 /* Register definitions for UART DMA block. Version 1.1 or later. */
0029 #define UDMA_ARB_RX     0x00
0030 #define UDMA_ARB_TX     0x04
0031 #define     UDMA_ARB_REQ                0x00000001
0032 #define     UDMA_ARB_GRANT              0x00000002
0033 
0034 #define UDMA_RX_REVISION    0x00
0035 #define UDMA_RX_REVISION_REQUIRED           0x00000101
0036 #define UDMA_RX_CTRL        0x04
0037 #define     UDMA_RX_CTRL_BUF_CLOSE_MODE     0x00010000
0038 #define     UDMA_RX_CTRL_MASK_WR_DONE       0x00008000
0039 #define     UDMA_RX_CTRL_ENDIAN_OVERRIDE        0x00004000
0040 #define     UDMA_RX_CTRL_ENDIAN         0x00002000
0041 #define     UDMA_RX_CTRL_OE_IS_ERR          0x00001000
0042 #define     UDMA_RX_CTRL_PE_IS_ERR          0x00000800
0043 #define     UDMA_RX_CTRL_FE_IS_ERR          0x00000400
0044 #define     UDMA_RX_CTRL_NUM_BUF_USED_MASK      0x000003c0
0045 #define     UDMA_RX_CTRL_NUM_BUF_USED_SHIFT 6
0046 #define     UDMA_RX_CTRL_BUF_CLOSE_CLK_SEL_SYS  0x00000020
0047 #define     UDMA_RX_CTRL_BUF_CLOSE_ENA      0x00000010
0048 #define     UDMA_RX_CTRL_TIMEOUT_CLK_SEL_SYS    0x00000008
0049 #define     UDMA_RX_CTRL_TIMEOUT_ENA        0x00000004
0050 #define     UDMA_RX_CTRL_ABORT          0x00000002
0051 #define     UDMA_RX_CTRL_ENA            0x00000001
0052 #define UDMA_RX_STATUS      0x08
0053 #define     UDMA_RX_STATUS_ACTIVE_BUF_MASK      0x0000000f
0054 #define UDMA_RX_TRANSFER_LEN    0x0c
0055 #define UDMA_RX_TRANSFER_TOTAL  0x10
0056 #define UDMA_RX_BUFFER_SIZE 0x14
0057 #define UDMA_RX_SRC_ADDR    0x18
0058 #define UDMA_RX_TIMEOUT     0x1c
0059 #define UDMA_RX_BUFFER_CLOSE    0x20
0060 #define UDMA_RX_BLOCKOUT_COUNTER 0x24
0061 #define UDMA_RX_BUF0_PTR_LO 0x28
0062 #define UDMA_RX_BUF0_PTR_HI 0x2c
0063 #define UDMA_RX_BUF0_STATUS 0x30
0064 #define     UDMA_RX_BUFX_STATUS_OVERRUN_ERR     0x00000010
0065 #define     UDMA_RX_BUFX_STATUS_FRAME_ERR       0x00000008
0066 #define     UDMA_RX_BUFX_STATUS_PARITY_ERR      0x00000004
0067 #define     UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED   0x00000002
0068 #define     UDMA_RX_BUFX_STATUS_DATA_RDY        0x00000001
0069 #define UDMA_RX_BUF0_DATA_LEN   0x34
0070 #define UDMA_RX_BUF1_PTR_LO 0x38
0071 #define UDMA_RX_BUF1_PTR_HI 0x3c
0072 #define UDMA_RX_BUF1_STATUS 0x40
0073 #define UDMA_RX_BUF1_DATA_LEN   0x44
0074 
0075 #define UDMA_TX_REVISION    0x00
0076 #define UDMA_TX_REVISION_REQUIRED           0x00000101
0077 #define UDMA_TX_CTRL        0x04
0078 #define     UDMA_TX_CTRL_ENDIAN_OVERRIDE        0x00000080
0079 #define     UDMA_TX_CTRL_ENDIAN         0x00000040
0080 #define     UDMA_TX_CTRL_NUM_BUF_USED_MASK      0x00000030
0081 #define     UDMA_TX_CTRL_NUM_BUF_USED_1     0x00000010
0082 #define     UDMA_TX_CTRL_ABORT          0x00000002
0083 #define     UDMA_TX_CTRL_ENA            0x00000001
0084 #define UDMA_TX_DST_ADDR    0x08
0085 #define UDMA_TX_BLOCKOUT_COUNTER 0x10
0086 #define UDMA_TX_TRANSFER_LEN    0x14
0087 #define UDMA_TX_TRANSFER_TOTAL  0x18
0088 #define UDMA_TX_STATUS      0x20
0089 #define UDMA_TX_BUF0_PTR_LO 0x24
0090 #define UDMA_TX_BUF0_PTR_HI 0x28
0091 #define UDMA_TX_BUF0_STATUS 0x2c
0092 #define     UDMA_TX_BUFX_LAST           0x00000002
0093 #define     UDMA_TX_BUFX_EMPTY          0x00000001
0094 #define UDMA_TX_BUF0_DATA_LEN   0x30
0095 #define UDMA_TX_BUF0_DATA_SENT  0x34
0096 #define UDMA_TX_BUF1_PTR_LO 0x38
0097 
0098 #define UDMA_INTR_STATUS    0x00
0099 #define     UDMA_INTR_ARB_TX_GRANT          0x00040000
0100 #define     UDMA_INTR_ARB_RX_GRANT          0x00020000
0101 #define     UDMA_INTR_TX_ALL_EMPTY          0x00010000
0102 #define     UDMA_INTR_TX_EMPTY_BUF1         0x00008000
0103 #define     UDMA_INTR_TX_EMPTY_BUF0         0x00004000
0104 #define     UDMA_INTR_TX_ABORT          0x00002000
0105 #define     UDMA_INTR_TX_DONE           0x00001000
0106 #define     UDMA_INTR_RX_ERROR          0x00000800
0107 #define     UDMA_INTR_RX_TIMEOUT            0x00000400
0108 #define     UDMA_INTR_RX_READY_BUF7         0x00000200
0109 #define     UDMA_INTR_RX_READY_BUF6         0x00000100
0110 #define     UDMA_INTR_RX_READY_BUF5         0x00000080
0111 #define     UDMA_INTR_RX_READY_BUF4         0x00000040
0112 #define     UDMA_INTR_RX_READY_BUF3         0x00000020
0113 #define     UDMA_INTR_RX_READY_BUF2         0x00000010
0114 #define     UDMA_INTR_RX_READY_BUF1         0x00000008
0115 #define     UDMA_INTR_RX_READY_BUF0         0x00000004
0116 #define     UDMA_INTR_RX_READY_MASK         0x000003fc
0117 #define     UDMA_INTR_RX_READY_SHIFT        2
0118 #define     UDMA_INTR_RX_ABORT          0x00000002
0119 #define     UDMA_INTR_RX_DONE           0x00000001
0120 #define UDMA_INTR_SET       0x04
0121 #define UDMA_INTR_CLEAR     0x08
0122 #define UDMA_INTR_MASK_STATUS   0x0c
0123 #define UDMA_INTR_MASK_SET  0x10
0124 #define UDMA_INTR_MASK_CLEAR    0x14
0125 
0126 
0127 #define UDMA_RX_INTERRUPTS ( \
0128     UDMA_INTR_RX_ERROR | \
0129     UDMA_INTR_RX_TIMEOUT | \
0130     UDMA_INTR_RX_READY_BUF0 | \
0131     UDMA_INTR_RX_READY_BUF1 | \
0132     UDMA_INTR_RX_READY_BUF2 | \
0133     UDMA_INTR_RX_READY_BUF3 | \
0134     UDMA_INTR_RX_READY_BUF4 | \
0135     UDMA_INTR_RX_READY_BUF5 | \
0136     UDMA_INTR_RX_READY_BUF6 | \
0137     UDMA_INTR_RX_READY_BUF7 | \
0138     UDMA_INTR_RX_ABORT | \
0139     UDMA_INTR_RX_DONE)
0140 
0141 #define UDMA_RX_ERR_INTERRUPTS ( \
0142     UDMA_INTR_RX_ERROR | \
0143     UDMA_INTR_RX_TIMEOUT | \
0144     UDMA_INTR_RX_ABORT | \
0145     UDMA_INTR_RX_DONE)
0146 
0147 #define UDMA_TX_INTERRUPTS ( \
0148     UDMA_INTR_TX_ABORT | \
0149     UDMA_INTR_TX_DONE)
0150 
0151 #define UDMA_IS_RX_INTERRUPT(status) ((status) & UDMA_RX_INTERRUPTS)
0152 #define UDMA_IS_TX_INTERRUPT(status) ((status) & UDMA_TX_INTERRUPTS)
0153 
0154 
0155 /* Current devices have 8 sets of RX buffer registers */
0156 #define UDMA_RX_BUFS_COUNT  8
0157 #define UDMA_RX_BUFS_REG_OFFSET (UDMA_RX_BUF1_PTR_LO - UDMA_RX_BUF0_PTR_LO)
0158 #define UDMA_RX_BUFx_PTR_LO(x)  (UDMA_RX_BUF0_PTR_LO + \
0159                  ((x) * UDMA_RX_BUFS_REG_OFFSET))
0160 #define UDMA_RX_BUFx_PTR_HI(x)  (UDMA_RX_BUF0_PTR_HI + \
0161                  ((x) * UDMA_RX_BUFS_REG_OFFSET))
0162 #define UDMA_RX_BUFx_STATUS(x)  (UDMA_RX_BUF0_STATUS + \
0163                  ((x) * UDMA_RX_BUFS_REG_OFFSET))
0164 #define UDMA_RX_BUFx_DATA_LEN(x) (UDMA_RX_BUF0_DATA_LEN + \
0165                   ((x) * UDMA_RX_BUFS_REG_OFFSET))
0166 
0167 /* Current devices have 2 sets of TX buffer registers */
0168 #define UDMA_TX_BUFS_COUNT  2
0169 #define UDMA_TX_BUFS_REG_OFFSET (UDMA_TX_BUF1_PTR_LO - UDMA_TX_BUF0_PTR_LO)
0170 #define UDMA_TX_BUFx_PTR_LO(x)  (UDMA_TX_BUF0_PTR_LO + \
0171                  ((x) * UDMA_TX_BUFS_REG_OFFSET))
0172 #define UDMA_TX_BUFx_PTR_HI(x)  (UDMA_TX_BUF0_PTR_HI + \
0173                  ((x) * UDMA_TX_BUFS_REG_OFFSET))
0174 #define UDMA_TX_BUFx_STATUS(x)  (UDMA_TX_BUF0_STATUS + \
0175                  ((x) * UDMA_TX_BUFS_REG_OFFSET))
0176 #define UDMA_TX_BUFx_DATA_LEN(x) (UDMA_TX_BUF0_DATA_LEN + \
0177                   ((x) * UDMA_TX_BUFS_REG_OFFSET))
0178 #define UDMA_TX_BUFx_DATA_SENT(x) (UDMA_TX_BUF0_DATA_SENT + \
0179                    ((x) * UDMA_TX_BUFS_REG_OFFSET))
0180 #define REGS_8250 0
0181 #define REGS_DMA_RX 1
0182 #define REGS_DMA_TX 2
0183 #define REGS_DMA_ISR 3
0184 #define REGS_DMA_ARB 4
0185 #define REGS_MAX 5
0186 
0187 #define TX_BUF_SIZE 4096
0188 #define RX_BUF_SIZE 4096
0189 #define RX_BUFS_COUNT 2
0190 #define KHZ    1000
0191 #define MHZ(x) ((x) * KHZ * KHZ)
0192 
0193 static const u32 brcmstb_rate_table[] = {
0194     MHZ(81),
0195     MHZ(108),
0196     MHZ(64),        /* Actually 64285715 for some chips */
0197     MHZ(48),
0198 };
0199 
0200 static const u32 brcmstb_rate_table_7278[] = {
0201     MHZ(81),
0202     MHZ(108),
0203     0,
0204     MHZ(48),
0205 };
0206 
0207 struct brcmuart_priv {
0208     int     line;
0209     struct clk  *baud_mux_clk;
0210     unsigned long   default_mux_rate;
0211     u32     real_rates[ARRAY_SIZE(brcmstb_rate_table)];
0212     const u32   *rate_table;
0213     ktime_t     char_wait;
0214     struct uart_port *up;
0215     struct hrtimer  hrt;
0216     bool        shutdown;
0217     bool        dma_enabled;
0218     struct uart_8250_dma dma;
0219     void __iomem    *regs[REGS_MAX];
0220     dma_addr_t  rx_addr;
0221     void        *rx_bufs;
0222     size_t      rx_size;
0223     int     rx_next_buf;
0224     dma_addr_t  tx_addr;
0225     void        *tx_buf;
0226     size_t      tx_size;
0227     bool        tx_running;
0228     bool        rx_running;
0229     struct dentry   *debugfs_dir;
0230 
0231     /* stats exposed through debugfs */
0232     u64     dma_rx_partial_buf;
0233     u64     dma_rx_full_buf;
0234     u32     rx_bad_timeout_late_char;
0235     u32     rx_bad_timeout_no_char;
0236     u32     rx_missing_close_timeout;
0237     u32     rx_err;
0238     u32     rx_timeout;
0239     u32     rx_abort;
0240     u32     saved_mctrl;
0241 };
0242 
0243 static struct dentry *brcmuart_debugfs_root;
0244 
0245 /*
0246  * Register access routines
0247  */
0248 static u32 udma_readl(struct brcmuart_priv *priv,
0249         int reg_type, int offset)
0250 {
0251     return readl(priv->regs[reg_type] + offset);
0252 }
0253 
0254 static void udma_writel(struct brcmuart_priv *priv,
0255             int reg_type, int offset, u32 value)
0256 {
0257     writel(value, priv->regs[reg_type] + offset);
0258 }
0259 
0260 static void udma_set(struct brcmuart_priv *priv,
0261         int reg_type, int offset, u32 bits)
0262 {
0263     void __iomem *reg = priv->regs[reg_type] + offset;
0264     u32 value;
0265 
0266     value = readl(reg);
0267     value |= bits;
0268     writel(value, reg);
0269 }
0270 
0271 static void udma_unset(struct brcmuart_priv *priv,
0272         int reg_type, int offset, u32 bits)
0273 {
0274     void __iomem *reg = priv->regs[reg_type] + offset;
0275     u32 value;
0276 
0277     value = readl(reg);
0278     value &= ~bits;
0279     writel(value, reg);
0280 }
0281 
0282 /*
0283  * The UART DMA engine hardware can be used by multiple UARTS, but
0284  * only one at a time. Sharing is not currently supported so
0285  * the first UART to request the DMA engine will get it and any
0286  * subsequent requests by other UARTS will fail.
0287  */
0288 static int brcmuart_arbitration(struct brcmuart_priv *priv, bool acquire)
0289 {
0290     u32 rx_grant;
0291     u32 tx_grant;
0292     int waits;
0293     int ret = 0;
0294 
0295     if (acquire) {
0296         udma_set(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ);
0297         udma_set(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ);
0298 
0299         waits = 1;
0300         while (1) {
0301             rx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_RX);
0302             tx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_TX);
0303             if (rx_grant & tx_grant & UDMA_ARB_GRANT)
0304                 return 0;
0305             if (waits-- == 0)
0306                 break;
0307             msleep(1);
0308         }
0309         ret = 1;
0310     }
0311 
0312     udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ);
0313     udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ);
0314     return ret;
0315 }
0316 
0317 static void brcmuart_init_dma_hardware(struct brcmuart_priv *priv)
0318 {
0319     u32 daddr;
0320     u32 value;
0321     int x;
0322 
0323     /* Start with all interrupts disabled */
0324     udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, 0xffffffff);
0325 
0326     udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_SIZE, RX_BUF_SIZE);
0327 
0328     /*
0329      * Setup buffer close to happen when 32 character times have
0330      * elapsed since the last character was received.
0331      */
0332     udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_CLOSE, 16*10*32);
0333     value = (RX_BUFS_COUNT << UDMA_RX_CTRL_NUM_BUF_USED_SHIFT)
0334         | UDMA_RX_CTRL_BUF_CLOSE_MODE
0335         | UDMA_RX_CTRL_BUF_CLOSE_ENA;
0336     udma_writel(priv, REGS_DMA_RX, UDMA_RX_CTRL, value);
0337 
0338     udma_writel(priv, REGS_DMA_RX, UDMA_RX_BLOCKOUT_COUNTER, 0);
0339     daddr = priv->rx_addr;
0340     for (x = 0; x < RX_BUFS_COUNT; x++) {
0341 
0342         /* Set RX transfer length to 0 for unknown */
0343         udma_writel(priv, REGS_DMA_RX, UDMA_RX_TRANSFER_LEN, 0);
0344 
0345         udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_LO(x),
0346                 lower_32_bits(daddr));
0347         udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_HI(x),
0348                 upper_32_bits(daddr));
0349         daddr += RX_BUF_SIZE;
0350     }
0351 
0352     daddr = priv->tx_addr;
0353     udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_LO(0),
0354             lower_32_bits(daddr));
0355     udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_HI(0),
0356             upper_32_bits(daddr));
0357     udma_writel(priv, REGS_DMA_TX, UDMA_TX_CTRL,
0358             UDMA_TX_CTRL_NUM_BUF_USED_1);
0359 
0360     /* clear all interrupts then enable them */
0361     udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, 0xffffffff);
0362     udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,
0363         UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);
0364 
0365 }
0366 
0367 static void start_rx_dma(struct uart_8250_port *p)
0368 {
0369     struct brcmuart_priv *priv = p->port.private_data;
0370     int x;
0371 
0372     udma_unset(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA);
0373 
0374     /* Clear the RX ready bit for all buffers */
0375     for (x = 0; x < RX_BUFS_COUNT; x++)
0376         udma_unset(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(x),
0377             UDMA_RX_BUFX_STATUS_DATA_RDY);
0378 
0379     /* always start with buffer 0 */
0380     udma_unset(priv, REGS_DMA_RX, UDMA_RX_STATUS,
0381            UDMA_RX_STATUS_ACTIVE_BUF_MASK);
0382     priv->rx_next_buf = 0;
0383 
0384     udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA);
0385     priv->rx_running = true;
0386 }
0387 
0388 static void stop_rx_dma(struct uart_8250_port *p)
0389 {
0390     struct brcmuart_priv *priv = p->port.private_data;
0391 
0392     /* If RX is running, set the RX ABORT */
0393     if (priv->rx_running)
0394         udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ABORT);
0395 }
0396 
0397 static int stop_tx_dma(struct uart_8250_port *p)
0398 {
0399     struct brcmuart_priv *priv = p->port.private_data;
0400     u32 value;
0401 
0402     /* If TX is running, set the TX ABORT */
0403     value = udma_readl(priv, REGS_DMA_TX, UDMA_TX_CTRL);
0404     if (value & UDMA_TX_CTRL_ENA)
0405         udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ABORT);
0406     priv->tx_running = false;
0407     return 0;
0408 }
0409 
0410 /*
0411  * NOTE: printk's in this routine will hang the system if this is
0412  * the console tty
0413  */
0414 static int brcmuart_tx_dma(struct uart_8250_port *p)
0415 {
0416     struct brcmuart_priv *priv = p->port.private_data;
0417     struct circ_buf *xmit = &p->port.state->xmit;
0418     u32 tx_size;
0419 
0420     if (uart_tx_stopped(&p->port) || priv->tx_running ||
0421         uart_circ_empty(xmit)) {
0422         return 0;
0423     }
0424     tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
0425 
0426     priv->dma.tx_err = 0;
0427     memcpy(priv->tx_buf, &xmit->buf[xmit->tail], tx_size);
0428     xmit->tail += tx_size;
0429     xmit->tail &= UART_XMIT_SIZE - 1;
0430     p->port.icount.tx += tx_size;
0431 
0432     if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
0433         uart_write_wakeup(&p->port);
0434 
0435     udma_writel(priv, REGS_DMA_TX, UDMA_TX_TRANSFER_LEN, tx_size);
0436     udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUF0_DATA_LEN, tx_size);
0437     udma_unset(priv, REGS_DMA_TX, UDMA_TX_BUF0_STATUS, UDMA_TX_BUFX_EMPTY);
0438     udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ENA);
0439     priv->tx_running = true;
0440 
0441     return 0;
0442 }
0443 
0444 static void brcmuart_rx_buf_done_isr(struct uart_port *up, int index)
0445 {
0446     struct brcmuart_priv *priv = up->private_data;
0447     struct tty_port *tty_port = &up->state->port;
0448     u32 status;
0449     u32 length;
0450     u32 copied;
0451 
0452     /* Make sure we're still in sync with the hardware */
0453     status = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(index));
0454     length = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_DATA_LEN(index));
0455 
0456     if ((status & UDMA_RX_BUFX_STATUS_DATA_RDY) == 0) {
0457         dev_err(up->dev, "RX done interrupt but DATA_RDY not found\n");
0458         return;
0459     }
0460     if (status & (UDMA_RX_BUFX_STATUS_OVERRUN_ERR |
0461               UDMA_RX_BUFX_STATUS_FRAME_ERR |
0462               UDMA_RX_BUFX_STATUS_PARITY_ERR)) {
0463         if (status & UDMA_RX_BUFX_STATUS_OVERRUN_ERR) {
0464             up->icount.overrun++;
0465             dev_warn(up->dev, "RX OVERRUN Error\n");
0466         }
0467         if (status & UDMA_RX_BUFX_STATUS_FRAME_ERR) {
0468             up->icount.frame++;
0469             dev_warn(up->dev, "RX FRAMING Error\n");
0470         }
0471         if (status & UDMA_RX_BUFX_STATUS_PARITY_ERR) {
0472             up->icount.parity++;
0473             dev_warn(up->dev, "RX PARITY Error\n");
0474         }
0475     }
0476     copied = (u32)tty_insert_flip_string(
0477         tty_port,
0478         priv->rx_bufs + (index * RX_BUF_SIZE),
0479         length);
0480     if (copied != length) {
0481         dev_warn(up->dev, "Flip buffer overrun of %d bytes\n",
0482              length - copied);
0483         up->icount.overrun += length - copied;
0484     }
0485     up->icount.rx += length;
0486     if (status & UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED)
0487         priv->dma_rx_partial_buf++;
0488     else if (length != RX_BUF_SIZE)
0489         /*
0490          * This is a bug in the controller that doesn't cause
0491          * any problems but will be fixed in the future.
0492          */
0493         priv->rx_missing_close_timeout++;
0494     else
0495         priv->dma_rx_full_buf++;
0496 
0497     tty_flip_buffer_push(tty_port);
0498 }
0499 
0500 static void brcmuart_rx_isr(struct uart_port *up, u32 rx_isr)
0501 {
0502     struct brcmuart_priv *priv = up->private_data;
0503     struct device *dev = up->dev;
0504     u32 rx_done_isr;
0505     u32 check_isr;
0506 
0507     rx_done_isr = (rx_isr & UDMA_INTR_RX_READY_MASK);
0508     while (rx_done_isr) {
0509         check_isr = UDMA_INTR_RX_READY_BUF0 << priv->rx_next_buf;
0510         if (check_isr & rx_done_isr) {
0511             brcmuart_rx_buf_done_isr(up, priv->rx_next_buf);
0512         } else {
0513             dev_err(dev,
0514                 "RX buffer ready out of sequence, restarting RX DMA\n");
0515             start_rx_dma(up_to_u8250p(up));
0516             break;
0517         }
0518         if (rx_isr & UDMA_RX_ERR_INTERRUPTS) {
0519             if (rx_isr & UDMA_INTR_RX_ERROR)
0520                 priv->rx_err++;
0521             if (rx_isr & UDMA_INTR_RX_TIMEOUT) {
0522                 priv->rx_timeout++;
0523                 dev_err(dev, "RX TIMEOUT Error\n");
0524             }
0525             if (rx_isr & UDMA_INTR_RX_ABORT)
0526                 priv->rx_abort++;
0527             priv->rx_running = false;
0528         }
0529         /* If not ABORT, re-enable RX buffer */
0530         if (!(rx_isr & UDMA_INTR_RX_ABORT))
0531             udma_unset(priv, REGS_DMA_RX,
0532                    UDMA_RX_BUFx_STATUS(priv->rx_next_buf),
0533                    UDMA_RX_BUFX_STATUS_DATA_RDY);
0534         rx_done_isr &= ~check_isr;
0535         priv->rx_next_buf++;
0536         if (priv->rx_next_buf == RX_BUFS_COUNT)
0537             priv->rx_next_buf = 0;
0538     }
0539 }
0540 
0541 static void brcmuart_tx_isr(struct uart_port *up, u32 isr)
0542 {
0543     struct brcmuart_priv *priv = up->private_data;
0544     struct device *dev = up->dev;
0545     struct uart_8250_port *port_8250 = up_to_u8250p(up);
0546     struct circ_buf *xmit = &port_8250->port.state->xmit;
0547 
0548     if (isr & UDMA_INTR_TX_ABORT) {
0549         if (priv->tx_running)
0550             dev_err(dev, "Unexpected TX_ABORT interrupt\n");
0551         return;
0552     }
0553     priv->tx_running = false;
0554     if (!uart_circ_empty(xmit) && !uart_tx_stopped(up))
0555         brcmuart_tx_dma(port_8250);
0556 }
0557 
0558 static irqreturn_t brcmuart_isr(int irq, void *dev_id)
0559 {
0560     struct uart_port *up = dev_id;
0561     struct device *dev = up->dev;
0562     struct brcmuart_priv *priv = up->private_data;
0563     unsigned long flags;
0564     u32 interrupts;
0565     u32 rval;
0566     u32 tval;
0567 
0568     interrupts = udma_readl(priv, REGS_DMA_ISR, UDMA_INTR_STATUS);
0569     if (interrupts == 0)
0570         return IRQ_NONE;
0571 
0572     spin_lock_irqsave(&up->lock, flags);
0573 
0574     /* Clear all interrupts */
0575     udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, interrupts);
0576 
0577     rval = UDMA_IS_RX_INTERRUPT(interrupts);
0578     if (rval)
0579         brcmuart_rx_isr(up, rval);
0580     tval = UDMA_IS_TX_INTERRUPT(interrupts);
0581     if (tval)
0582         brcmuart_tx_isr(up, tval);
0583     if ((rval | tval) == 0)
0584         dev_warn(dev, "Spurious interrupt: 0x%x\n", interrupts);
0585 
0586     spin_unlock_irqrestore(&up->lock, flags);
0587     return IRQ_HANDLED;
0588 }
0589 
0590 static int brcmuart_startup(struct uart_port *port)
0591 {
0592     int res;
0593     struct uart_8250_port *up = up_to_u8250p(port);
0594     struct brcmuart_priv *priv = up->port.private_data;
0595 
0596     priv->shutdown = false;
0597 
0598     /*
0599      * prevent serial8250_do_startup() from allocating non-existent
0600      * DMA resources
0601      */
0602     up->dma = NULL;
0603 
0604     res = serial8250_do_startup(port);
0605     if (!priv->dma_enabled)
0606         return res;
0607     /*
0608      * Disable the Receive Data Interrupt because the DMA engine
0609      * will handle this.
0610      */
0611     up->ier &= ~UART_IER_RDI;
0612     serial_port_out(port, UART_IER, up->ier);
0613 
0614     priv->tx_running = false;
0615     priv->dma.rx_dma = NULL;
0616     priv->dma.tx_dma = brcmuart_tx_dma;
0617     up->dma = &priv->dma;
0618 
0619     brcmuart_init_dma_hardware(priv);
0620     start_rx_dma(up);
0621     return res;
0622 }
0623 
0624 static void brcmuart_shutdown(struct uart_port *port)
0625 {
0626     struct uart_8250_port *up = up_to_u8250p(port);
0627     struct brcmuart_priv *priv = up->port.private_data;
0628     unsigned long flags;
0629 
0630     spin_lock_irqsave(&port->lock, flags);
0631     priv->shutdown = true;
0632     if (priv->dma_enabled) {
0633         stop_rx_dma(up);
0634         stop_tx_dma(up);
0635         /* disable all interrupts */
0636         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET,
0637             UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);
0638     }
0639 
0640     /*
0641      * prevent serial8250_do_shutdown() from trying to free
0642      * DMA resources that we never alloc'd for this driver.
0643      */
0644     up->dma = NULL;
0645 
0646     spin_unlock_irqrestore(&port->lock, flags);
0647     serial8250_do_shutdown(port);
0648 }
0649 
0650 /*
0651  * Not all clocks run at the exact specified rate, so set each requested
0652  * rate and then get the actual rate.
0653  */
0654 static void init_real_clk_rates(struct device *dev, struct brcmuart_priv *priv)
0655 {
0656     int x;
0657     int rc;
0658 
0659     priv->default_mux_rate = clk_get_rate(priv->baud_mux_clk);
0660     for (x = 0; x < ARRAY_SIZE(priv->real_rates); x++) {
0661         if (priv->rate_table[x] == 0) {
0662             priv->real_rates[x] = 0;
0663             continue;
0664         }
0665         rc = clk_set_rate(priv->baud_mux_clk, priv->rate_table[x]);
0666         if (rc) {
0667             dev_err(dev, "Error selecting BAUD MUX clock for %u\n",
0668                 priv->rate_table[x]);
0669             priv->real_rates[x] = priv->rate_table[x];
0670         } else {
0671             priv->real_rates[x] = clk_get_rate(priv->baud_mux_clk);
0672         }
0673     }
0674     clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate);
0675 }
0676 
0677 static void set_clock_mux(struct uart_port *up, struct brcmuart_priv *priv,
0678             u32 baud)
0679 {
0680     u32 percent;
0681     u32 best_percent = UINT_MAX;
0682     u32 quot;
0683     u32 best_quot = 1;
0684     u32 rate;
0685     int best_index = -1;
0686     u64 hires_rate;
0687     u64 hires_baud;
0688     u64 hires_err;
0689     int rc;
0690     int i;
0691     int real_baud;
0692 
0693     /* If the Baud Mux Clock was not specified, just return */
0694     if (priv->baud_mux_clk == NULL)
0695         return;
0696 
0697     /* Find the closest match for specified baud */
0698     for (i = 0; i < ARRAY_SIZE(priv->real_rates); i++) {
0699         if (priv->real_rates[i] == 0)
0700             continue;
0701         rate = priv->real_rates[i] / 16;
0702         quot = DIV_ROUND_CLOSEST(rate, baud);
0703         if (!quot)
0704             continue;
0705 
0706         /* increase resolution to get xx.xx percent */
0707         hires_rate = (u64)rate * 10000;
0708         hires_baud = (u64)baud * 10000;
0709 
0710         hires_err = div_u64(hires_rate, (u64)quot);
0711 
0712         /* get the delta */
0713         if (hires_err > hires_baud)
0714             hires_err = (hires_err - hires_baud);
0715         else
0716             hires_err = (hires_baud - hires_err);
0717 
0718         percent = (unsigned long)DIV_ROUND_CLOSEST_ULL(hires_err, baud);
0719         dev_dbg(up->dev,
0720             "Baud rate: %u, MUX Clk: %u, Error: %u.%u%%\n",
0721             baud, priv->real_rates[i], percent / 100,
0722             percent % 100);
0723         if (percent < best_percent) {
0724             best_percent = percent;
0725             best_index = i;
0726             best_quot = quot;
0727         }
0728     }
0729     if (best_index == -1) {
0730         dev_err(up->dev, "Error, %d BAUD rate is too fast.\n", baud);
0731         return;
0732     }
0733     rate = priv->real_rates[best_index];
0734     rc = clk_set_rate(priv->baud_mux_clk, rate);
0735     if (rc)
0736         dev_err(up->dev, "Error selecting BAUD MUX clock\n");
0737 
0738     /* Error over 3 percent will cause data errors */
0739     if (best_percent > 300)
0740         dev_err(up->dev, "Error, baud: %d has %u.%u%% error\n",
0741             baud, percent / 100, percent % 100);
0742 
0743     real_baud = rate / 16 / best_quot;
0744     dev_dbg(up->dev, "Selecting BAUD MUX rate: %u\n", rate);
0745     dev_dbg(up->dev, "Requested baud: %u, Actual baud: %u\n",
0746         baud, real_baud);
0747 
0748     /* calc nanoseconds for 1.5 characters time at the given baud rate */
0749     i = NSEC_PER_SEC / real_baud / 10;
0750     i += (i / 2);
0751     priv->char_wait = ns_to_ktime(i);
0752 
0753     up->uartclk = rate;
0754 }
0755 
0756 static void brcmstb_set_termios(struct uart_port *up,
0757                 struct ktermios *termios,
0758                 struct ktermios *old)
0759 {
0760     struct uart_8250_port *p8250 = up_to_u8250p(up);
0761     struct brcmuart_priv *priv = up->private_data;
0762 
0763     if (priv->dma_enabled)
0764         stop_rx_dma(p8250);
0765     set_clock_mux(up, priv, tty_termios_baud_rate(termios));
0766     serial8250_do_set_termios(up, termios, old);
0767     if (p8250->mcr & UART_MCR_AFE)
0768         p8250->port.status |= UPSTAT_AUTOCTS;
0769     if (priv->dma_enabled)
0770         start_rx_dma(p8250);
0771 }
0772 
0773 static int brcmuart_handle_irq(struct uart_port *p)
0774 {
0775     unsigned int iir = serial_port_in(p, UART_IIR);
0776     struct brcmuart_priv *priv = p->private_data;
0777     struct uart_8250_port *up = up_to_u8250p(p);
0778     unsigned int status;
0779     unsigned long flags;
0780     unsigned int ier;
0781     unsigned int mcr;
0782     int handled = 0;
0783 
0784     /*
0785      * There's a bug in some 8250 cores where we get a timeout
0786      * interrupt but there is no data ready.
0787      */
0788     if (((iir & UART_IIR_ID) == UART_IIR_RX_TIMEOUT) && !(priv->shutdown)) {
0789         spin_lock_irqsave(&p->lock, flags);
0790         status = serial_port_in(p, UART_LSR);
0791         if ((status & UART_LSR_DR) == 0) {
0792 
0793             ier = serial_port_in(p, UART_IER);
0794             /*
0795              * if Receive Data Interrupt is enabled and
0796              * we're uing hardware flow control, deassert
0797              * RTS and wait for any chars in the pipline to
0798              * arrive and then check for DR again.
0799              */
0800             if ((ier & UART_IER_RDI) && (up->mcr & UART_MCR_AFE)) {
0801                 ier &= ~(UART_IER_RLSI | UART_IER_RDI);
0802                 serial_port_out(p, UART_IER, ier);
0803                 mcr = serial_port_in(p, UART_MCR);
0804                 mcr &= ~UART_MCR_RTS;
0805                 serial_port_out(p, UART_MCR, mcr);
0806                 hrtimer_start(&priv->hrt, priv->char_wait,
0807                           HRTIMER_MODE_REL);
0808             } else {
0809                 serial_port_in(p, UART_RX);
0810             }
0811 
0812             handled = 1;
0813         }
0814         spin_unlock_irqrestore(&p->lock, flags);
0815         if (handled)
0816             return 1;
0817     }
0818     return serial8250_handle_irq(p, iir);
0819 }
0820 
0821 static enum hrtimer_restart brcmuart_hrtimer_func(struct hrtimer *t)
0822 {
0823     struct brcmuart_priv *priv = container_of(t, struct brcmuart_priv, hrt);
0824     struct uart_port *p = priv->up;
0825     struct uart_8250_port *up = up_to_u8250p(p);
0826     unsigned int status;
0827     unsigned long flags;
0828 
0829     if (priv->shutdown)
0830         return HRTIMER_NORESTART;
0831 
0832     spin_lock_irqsave(&p->lock, flags);
0833     status = serial_port_in(p, UART_LSR);
0834 
0835     /*
0836      * If a character did not arrive after the timeout, clear the false
0837      * receive timeout.
0838      */
0839     if ((status & UART_LSR_DR) == 0) {
0840         serial_port_in(p, UART_RX);
0841         priv->rx_bad_timeout_no_char++;
0842     } else {
0843         priv->rx_bad_timeout_late_char++;
0844     }
0845 
0846     /* re-enable receive unless upper layer has disabled it */
0847     if ((up->ier & (UART_IER_RLSI | UART_IER_RDI)) ==
0848         (UART_IER_RLSI | UART_IER_RDI)) {
0849         status = serial_port_in(p, UART_IER);
0850         status |= (UART_IER_RLSI | UART_IER_RDI);
0851         serial_port_out(p, UART_IER, status);
0852         status = serial_port_in(p, UART_MCR);
0853         status |= UART_MCR_RTS;
0854         serial_port_out(p, UART_MCR, status);
0855     }
0856     spin_unlock_irqrestore(&p->lock, flags);
0857     return HRTIMER_NORESTART;
0858 }
0859 
0860 static const struct of_device_id brcmuart_dt_ids[] = {
0861     {
0862         .compatible = "brcm,bcm7278-uart",
0863         .data = brcmstb_rate_table_7278,
0864     },
0865     {
0866         .compatible = "brcm,bcm7271-uart",
0867         .data = brcmstb_rate_table,
0868     },
0869     {},
0870 };
0871 
0872 MODULE_DEVICE_TABLE(of, brcmuart_dt_ids);
0873 
0874 static void brcmuart_free_bufs(struct device *dev, struct brcmuart_priv *priv)
0875 {
0876     if (priv->rx_bufs)
0877         dma_free_coherent(dev, priv->rx_size, priv->rx_bufs,
0878                   priv->rx_addr);
0879     if (priv->tx_buf)
0880         dma_free_coherent(dev, priv->tx_size, priv->tx_buf,
0881                   priv->tx_addr);
0882 }
0883 
0884 static void brcmuart_throttle(struct uart_port *port)
0885 {
0886     struct brcmuart_priv *priv = port->private_data;
0887 
0888     udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, UDMA_RX_INTERRUPTS);
0889 }
0890 
0891 static void brcmuart_unthrottle(struct uart_port *port)
0892 {
0893     struct brcmuart_priv *priv = port->private_data;
0894 
0895     udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,
0896             UDMA_RX_INTERRUPTS);
0897 }
0898 
0899 static int debugfs_stats_show(struct seq_file *s, void *unused)
0900 {
0901     struct brcmuart_priv *priv = s->private;
0902 
0903     seq_printf(s, "rx_err:\t\t\t\t%u\n",
0904            priv->rx_err);
0905     seq_printf(s, "rx_timeout:\t\t\t%u\n",
0906            priv->rx_timeout);
0907     seq_printf(s, "rx_abort:\t\t\t%u\n",
0908            priv->rx_abort);
0909     seq_printf(s, "rx_bad_timeout_late_char:\t%u\n",
0910            priv->rx_bad_timeout_late_char);
0911     seq_printf(s, "rx_bad_timeout_no_char:\t\t%u\n",
0912            priv->rx_bad_timeout_no_char);
0913     seq_printf(s, "rx_missing_close_timeout:\t%u\n",
0914            priv->rx_missing_close_timeout);
0915     if (priv->dma_enabled) {
0916         seq_printf(s, "dma_rx_partial_buf:\t\t%llu\n",
0917                priv->dma_rx_partial_buf);
0918         seq_printf(s, "dma_rx_full_buf:\t\t%llu\n",
0919                priv->dma_rx_full_buf);
0920     }
0921     return 0;
0922 }
0923 DEFINE_SHOW_ATTRIBUTE(debugfs_stats);
0924 
0925 static void brcmuart_init_debugfs(struct brcmuart_priv *priv,
0926                   const char *device)
0927 {
0928     priv->debugfs_dir = debugfs_create_dir(device, brcmuart_debugfs_root);
0929     debugfs_create_file("stats", 0444, priv->debugfs_dir, priv,
0930                 &debugfs_stats_fops);
0931 }
0932 
0933 
0934 static int brcmuart_probe(struct platform_device *pdev)
0935 {
0936     struct resource *regs;
0937     struct device_node *np = pdev->dev.of_node;
0938     const struct of_device_id *of_id = NULL;
0939     struct uart_8250_port *new_port;
0940     struct device *dev = &pdev->dev;
0941     struct brcmuart_priv *priv;
0942     struct clk *baud_mux_clk;
0943     struct uart_8250_port up;
0944     int irq;
0945     void __iomem *membase = NULL;
0946     resource_size_t mapbase = 0;
0947     u32 clk_rate = 0;
0948     int ret;
0949     int x;
0950     int dma_irq;
0951     static const char * const reg_names[REGS_MAX] = {
0952         "uart", "dma_rx", "dma_tx", "dma_intr2", "dma_arb"
0953     };
0954 
0955     irq = platform_get_irq(pdev, 0);
0956     if (irq < 0)
0957         return irq;
0958     priv = devm_kzalloc(dev, sizeof(struct brcmuart_priv),
0959             GFP_KERNEL);
0960     if (!priv)
0961         return -ENOMEM;
0962 
0963     of_id = of_match_node(brcmuart_dt_ids, np);
0964     if (!of_id || !of_id->data)
0965         priv->rate_table = brcmstb_rate_table;
0966     else
0967         priv->rate_table = of_id->data;
0968 
0969     for (x = 0; x < REGS_MAX; x++) {
0970         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
0971                         reg_names[x]);
0972         if (!regs)
0973             break;
0974         priv->regs[x] = devm_ioremap(dev, regs->start,
0975                          resource_size(regs));
0976         if (!priv->regs[x])
0977             return -ENOMEM;
0978         if (x == REGS_8250) {
0979             mapbase = regs->start;
0980             membase = priv->regs[x];
0981         }
0982     }
0983 
0984     /* We should have just the uart base registers or all the registers */
0985     if (x != 1 && x != REGS_MAX) {
0986         dev_warn(dev, "%s registers not specified\n", reg_names[x]);
0987         return -EINVAL;
0988     }
0989 
0990     /* if the DMA registers were specified, try to enable DMA */
0991     if (x > REGS_DMA_RX) {
0992         if (brcmuart_arbitration(priv, 1) == 0) {
0993             u32 txrev = 0;
0994             u32 rxrev = 0;
0995 
0996             txrev = udma_readl(priv, REGS_DMA_RX, UDMA_RX_REVISION);
0997             rxrev = udma_readl(priv, REGS_DMA_TX, UDMA_TX_REVISION);
0998             if ((txrev >= UDMA_TX_REVISION_REQUIRED) &&
0999                 (rxrev >= UDMA_RX_REVISION_REQUIRED)) {
1000 
1001                 /* Enable the use of the DMA hardware */
1002                 priv->dma_enabled = true;
1003             } else {
1004                 brcmuart_arbitration(priv, 0);
1005                 dev_err(dev,
1006                     "Unsupported DMA Hardware Revision\n");
1007             }
1008         } else {
1009             dev_err(dev,
1010                 "Timeout arbitrating for UART DMA hardware\n");
1011         }
1012     }
1013 
1014     of_property_read_u32(np, "clock-frequency", &clk_rate);
1015 
1016     /* See if a Baud clock has been specified */
1017     baud_mux_clk = of_clk_get_by_name(np, "sw_baud");
1018     if (IS_ERR(baud_mux_clk)) {
1019         if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER)
1020             return -EPROBE_DEFER;
1021         dev_dbg(dev, "BAUD MUX clock not specified\n");
1022     } else {
1023         dev_dbg(dev, "BAUD MUX clock found\n");
1024         ret = clk_prepare_enable(baud_mux_clk);
1025         if (ret)
1026             return ret;
1027         priv->baud_mux_clk = baud_mux_clk;
1028         init_real_clk_rates(dev, priv);
1029         clk_rate = priv->default_mux_rate;
1030     }
1031 
1032     if (clk_rate == 0) {
1033         dev_err(dev, "clock-frequency or clk not defined\n");
1034         return -EINVAL;
1035     }
1036 
1037     dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");
1038 
1039     memset(&up, 0, sizeof(up));
1040     up.port.type = PORT_16550A;
1041     up.port.uartclk = clk_rate;
1042     up.port.dev = dev;
1043     up.port.mapbase = mapbase;
1044     up.port.membase = membase;
1045     up.port.irq = irq;
1046     up.port.handle_irq = brcmuart_handle_irq;
1047     up.port.regshift = 2;
1048     up.port.iotype = of_device_is_big_endian(np) ?
1049         UPIO_MEM32BE : UPIO_MEM32;
1050     up.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF
1051         | UPF_FIXED_PORT | UPF_FIXED_TYPE;
1052     up.port.dev = dev;
1053     up.port.private_data = priv;
1054     up.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1055     up.port.fifosize = 32;
1056 
1057     /* Check for a fixed line number */
1058     ret = of_alias_get_id(np, "serial");
1059     if (ret >= 0)
1060         up.port.line = ret;
1061 
1062     /* setup HR timer */
1063     hrtimer_init(&priv->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1064     priv->hrt.function = brcmuart_hrtimer_func;
1065 
1066     up.port.shutdown = brcmuart_shutdown;
1067     up.port.startup = brcmuart_startup;
1068     up.port.throttle = brcmuart_throttle;
1069     up.port.unthrottle = brcmuart_unthrottle;
1070     up.port.set_termios = brcmstb_set_termios;
1071 
1072     if (priv->dma_enabled) {
1073         priv->rx_size = RX_BUF_SIZE * RX_BUFS_COUNT;
1074         priv->rx_bufs = dma_alloc_coherent(dev,
1075                            priv->rx_size,
1076                            &priv->rx_addr, GFP_KERNEL);
1077         if (!priv->rx_bufs) {
1078             ret = -ENOMEM;
1079             goto err;
1080         }
1081         priv->tx_size = UART_XMIT_SIZE;
1082         priv->tx_buf = dma_alloc_coherent(dev,
1083                           priv->tx_size,
1084                           &priv->tx_addr, GFP_KERNEL);
1085         if (!priv->tx_buf) {
1086             ret = -ENOMEM;
1087             goto err;
1088         }
1089     }
1090 
1091     ret = serial8250_register_8250_port(&up);
1092     if (ret < 0) {
1093         dev_err(dev, "unable to register 8250 port\n");
1094         goto err;
1095     }
1096     priv->line = ret;
1097     new_port = serial8250_get_port(ret);
1098     priv->up = &new_port->port;
1099     if (priv->dma_enabled) {
1100         dma_irq = platform_get_irq_byname(pdev,  "dma");
1101         if (dma_irq < 0) {
1102             ret = dma_irq;
1103             dev_err(dev, "no IRQ resource info\n");
1104             goto err1;
1105         }
1106         ret = devm_request_irq(dev, dma_irq, brcmuart_isr,
1107                 IRQF_SHARED, "uart DMA irq", &new_port->port);
1108         if (ret) {
1109             dev_err(dev, "unable to register IRQ handler\n");
1110             goto err1;
1111         }
1112     }
1113     platform_set_drvdata(pdev, priv);
1114     brcmuart_init_debugfs(priv, dev_name(&pdev->dev));
1115     return 0;
1116 
1117 err1:
1118     serial8250_unregister_port(priv->line);
1119 err:
1120     brcmuart_free_bufs(dev, priv);
1121     brcmuart_arbitration(priv, 0);
1122     return ret;
1123 }
1124 
1125 static int brcmuart_remove(struct platform_device *pdev)
1126 {
1127     struct brcmuart_priv *priv = platform_get_drvdata(pdev);
1128 
1129     debugfs_remove_recursive(priv->debugfs_dir);
1130     hrtimer_cancel(&priv->hrt);
1131     serial8250_unregister_port(priv->line);
1132     brcmuart_free_bufs(&pdev->dev, priv);
1133     brcmuart_arbitration(priv, 0);
1134     return 0;
1135 }
1136 
1137 static int __maybe_unused brcmuart_suspend(struct device *dev)
1138 {
1139     struct brcmuart_priv *priv = dev_get_drvdata(dev);
1140     struct uart_8250_port *up = serial8250_get_port(priv->line);
1141     struct uart_port *port = &up->port;
1142     unsigned long flags;
1143 
1144     /*
1145      * This will prevent resume from enabling RTS before the
1146      *  baud rate has been restored.
1147      */
1148     spin_lock_irqsave(&port->lock, flags);
1149     priv->saved_mctrl = port->mctrl;
1150     port->mctrl &= ~TIOCM_RTS;
1151     spin_unlock_irqrestore(&port->lock, flags);
1152 
1153     serial8250_suspend_port(priv->line);
1154     clk_disable_unprepare(priv->baud_mux_clk);
1155 
1156     return 0;
1157 }
1158 
1159 static int __maybe_unused brcmuart_resume(struct device *dev)
1160 {
1161     struct brcmuart_priv *priv = dev_get_drvdata(dev);
1162     struct uart_8250_port *up = serial8250_get_port(priv->line);
1163     struct uart_port *port = &up->port;
1164     unsigned long flags;
1165     int ret;
1166 
1167     ret = clk_prepare_enable(priv->baud_mux_clk);
1168     if (ret)
1169         dev_err(dev, "Error enabling BAUD MUX clock\n");
1170 
1171     /*
1172      * The hardware goes back to it's default after suspend
1173      * so get the "clk" back in sync.
1174      */
1175     ret = clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate);
1176     if (ret)
1177         dev_err(dev, "Error restoring default BAUD MUX clock\n");
1178     if (priv->dma_enabled) {
1179         if (brcmuart_arbitration(priv, 1)) {
1180             dev_err(dev, "Timeout arbitrating for DMA hardware on resume\n");
1181             return(-EBUSY);
1182         }
1183         brcmuart_init_dma_hardware(priv);
1184         start_rx_dma(serial8250_get_port(priv->line));
1185     }
1186     serial8250_resume_port(priv->line);
1187 
1188     if (priv->saved_mctrl & TIOCM_RTS) {
1189         /* Restore RTS */
1190         spin_lock_irqsave(&port->lock, flags);
1191         port->mctrl |= TIOCM_RTS;
1192         port->ops->set_mctrl(port, port->mctrl);
1193         spin_unlock_irqrestore(&port->lock, flags);
1194     }
1195 
1196     return 0;
1197 }
1198 
1199 static const struct dev_pm_ops brcmuart_dev_pm_ops = {
1200     SET_SYSTEM_SLEEP_PM_OPS(brcmuart_suspend, brcmuart_resume)
1201 };
1202 
1203 static struct platform_driver brcmuart_platform_driver = {
1204     .driver = {
1205         .name   = "bcm7271-uart",
1206         .pm     = &brcmuart_dev_pm_ops,
1207         .of_match_table = brcmuart_dt_ids,
1208     },
1209     .probe      = brcmuart_probe,
1210     .remove     = brcmuart_remove,
1211 };
1212 
1213 static int __init brcmuart_init(void)
1214 {
1215     brcmuart_debugfs_root = debugfs_create_dir(
1216         brcmuart_platform_driver.driver.name, NULL);
1217     return platform_driver_register(&brcmuart_platform_driver);
1218 }
1219 module_init(brcmuart_init);
1220 
1221 static void __exit brcmuart_deinit(void)
1222 {
1223     platform_driver_unregister(&brcmuart_platform_driver);
1224     debugfs_remove_recursive(brcmuart_debugfs_root);
1225 }
1226 module_exit(brcmuart_deinit);
1227 
1228 MODULE_AUTHOR("Al Cooper");
1229 MODULE_DESCRIPTION("Broadcom NS16550A compatible serial port driver");
1230 MODULE_LICENSE("GPL v2");
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