drivers/thunderbolt/nhi_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Thunderbolt driver - NHI registers
0004  *
0005  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
0006  * Copyright (C) 2018, Intel Corporation
0007  */
0008
0009 #ifndef NHI_REGS_H_
0010 #define NHI_REGS_H_
0011
0012 #include <linux/types.h>
0013
0014 enum ring_flags {
0015     RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
0016     RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
0017     RING_FLAG_PCI_NO_SNOOP = 1 << 29,
0018     RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
0019     RING_FLAG_ENABLE = 1 << 31,
0020 };
0021
0022 /**
0023  * struct ring_desc - TX/RX ring entry
0024  *
0025  * For TX set length/eof/sof.
0026  * For RX length/eof/sof are set by the NHI.
0027  */
0028 struct ring_desc {
0029     u64 phys;
0030     u32 length:12;
0031     u32 eof:4;
0032     u32 sof:4;
0033     enum ring_desc_flags flags:12;
0034     u32 time; /* write zero */
0035 } __packed;
0036
0037 /* NHI registers in bar 0 */
0038
0039 /*
0040  * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
0041  * 00: physical pointer to an array of struct ring_desc
0042  * 08: ring tail (set by NHI)
0043  * 10: ring head (index of first non posted descriptor)
0044  * 12: descriptor count
0045  */
0046 #define REG_TX_RING_BASE    0x00000
0047
0048 /*
0049  * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
0050  * 00: physical pointer to an array of struct ring_desc
0051  * 08: ring head (index of first not posted descriptor)
0052  * 10: ring tail (set by NHI)
0053  * 12: descriptor count
0054  * 14: max frame sizes (anything larger than 0x100 has no effect)
0055  */
0056 #define REG_RX_RING_BASE    0x08000
0057
0058 /*
0059  * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
0060  * 00: enum_ring_flags
0061  * 04: isoch time stamp ?? (write 0)
0062  * ..: unknown
0063  */
0064 #define REG_TX_OPTIONS_BASE 0x19800
0065
0066 /*
0067  * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
0068  * 00: enum ring_flags
0069  *     If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
0070  *     the corresponding TX hop id.
0071  * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
0072  * ..: unknown
0073  */
0074 #define REG_RX_OPTIONS_BASE 0x29800
0075 #define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
0076 #define REG_RX_OPTIONS_E2E_HOP_SHIFT    12
0077
0078 /*
0079  * three bitfields: tx, rx, rx overflow
0080  * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
0081  * cleared on read. New interrupts are fired only after ALL registers have been
0082  * read (even those containing only disabled rings).
0083  */
0084 #define REG_RING_NOTIFY_BASE    0x37800
0085 #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
0086
0087 /*
0088  * two bitfields: rx, tx
0089  * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
0090  * enable/disable interrupts set/clear the corresponding bits.
0091  */
0092 #define REG_RING_INTERRUPT_BASE 0x38200
0093 #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
0094
0095 #define REG_INT_THROTTLING_RATE 0x38c00
0096
0097 /* Interrupt Vector Allocation */
0098 #define REG_INT_VEC_ALLOC_BASE  0x38c40
0099 #define REG_INT_VEC_ALLOC_BITS  4
0100 #define REG_INT_VEC_ALLOC_MASK  GENMASK(3, 0)
0101 #define REG_INT_VEC_ALLOC_REGS  (32 / REG_INT_VEC_ALLOC_BITS)
0102
0103 /* The last 11 bits contain the number of hops supported by the NHI port. */
0104 #define REG_HOP_COUNT       0x39640
0105
0106 #define REG_DMA_MISC            0x39864
0107 #define REG_DMA_MISC_INT_AUTO_CLEAR     BIT(2)
0108
0109 #define REG_INMAIL_DATA         0x39900
0110
0111 #define REG_INMAIL_CMD          0x39904
0112 #define REG_INMAIL_CMD_MASK     GENMASK(7, 0)
0113 #define REG_INMAIL_ERROR        BIT(30)
0114 #define REG_INMAIL_OP_REQUEST       BIT(31)
0115
0116 #define REG_OUTMAIL_CMD         0x3990c
0117 #define REG_OUTMAIL_CMD_OPMODE_SHIFT    8
0118 #define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
0119
0120 #define REG_FW_STS          0x39944
0121 #define REG_FW_STS_NVM_AUTH_DONE    BIT(31)
0122 #define REG_FW_STS_CIO_RESET_REQ    BIT(30)
0123 #define REG_FW_STS_ICM_EN_CPU       BIT(2)
0124 #define REG_FW_STS_ICM_EN_INVERT    BIT(1)
0125 #define REG_FW_STS_ICM_EN       BIT(0)
0126
0127 /* ICL NHI VSEC registers */
0128
0129 /* FW ready */
0130 #define VS_CAP_9            0xc8
0131 #define VS_CAP_9_FW_READY       BIT(31)
0132 /* UUID */
0133 #define VS_CAP_10           0xcc
0134 #define VS_CAP_11           0xd0
0135 /* LTR */
0136 #define VS_CAP_15           0xe0
0137 #define VS_CAP_16           0xe4
0138 /* TBT2PCIe */
0139 #define VS_CAP_18           0xec
0140 #define VS_CAP_18_DONE          BIT(0)
0141 /* PCIe2TBT */
0142 #define VS_CAP_19           0xf0
0143 #define VS_CAP_19_VALID         BIT(0)
0144 #define VS_CAP_19_CMD_SHIFT     1
0145 #define VS_CAP_19_CMD_MASK      GENMASK(7, 1)
0146 /* Force power */
0147 #define VS_CAP_22           0xfc
0148 #define VS_CAP_22_FORCE_POWER       BIT(1)
0149 #define VS_CAP_22_DMA_DELAY_MASK    GENMASK(31, 24)
0150 #define VS_CAP_22_DMA_DELAY_SHIFT   24
0151
0152 /**
0153  * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
0154  * @ICL_LC_GO2SX: Ask LC to enter Sx without wake
0155  * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
0156  * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
0157  */
0158 enum icl_lc_mailbox_cmd {
0159     ICL_LC_GO2SX = 0x02,
0160     ICL_LC_GO2SX_NO_WAKE = 0x03,
0161     ICL_LC_PREPARE_FOR_RESET = 0x21,
0162 };
0163
0164 #endif