drivers/thunderbolt/nhi.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Thunderbolt driver - NHI driver
0004  *
0005  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
0006  * Copyright (C) 2018, Intel Corporation
0007  */
0008
0009 #ifndef DSL3510_H_
0010 #define DSL3510_H_
0011
0012 #include <linux/thunderbolt.h>
0013
0014 enum nhi_fw_mode {
0015     NHI_FW_SAFE_MODE,
0016     NHI_FW_AUTH_MODE,
0017     NHI_FW_EP_MODE,
0018     NHI_FW_CM_MODE,
0019 };
0020
0021 enum nhi_mailbox_cmd {
0022     NHI_MAILBOX_SAVE_DEVS = 0x05,
0023     NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
0024     NHI_MAILBOX_DRV_UNLOADS = 0x07,
0025     NHI_MAILBOX_DISCONNECT_PA = 0x10,
0026     NHI_MAILBOX_DISCONNECT_PB = 0x11,
0027     NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
0028 };
0029
0030 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
0031 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
0032
0033 /**
0034  * struct tb_nhi_ops - NHI specific optional operations
0035  * @init: NHI specific initialization
0036  * @suspend_noirq: NHI specific suspend_noirq hook
0037  * @resume_noirq: NHI specific resume_noirq hook
0038  * @runtime_suspend: NHI specific runtime_suspend hook
0039  * @runtime_resume: NHI specific runtime_resume hook
0040  * @shutdown: NHI specific shutdown
0041  */
0042 struct tb_nhi_ops {
0043     int (*init)(struct tb_nhi *nhi);
0044     int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
0045     int (*resume_noirq)(struct tb_nhi *nhi);
0046     int (*runtime_suspend)(struct tb_nhi *nhi);
0047     int (*runtime_resume)(struct tb_nhi *nhi);
0048     void (*shutdown)(struct tb_nhi *nhi);
0049 };
0050
0051 extern const struct tb_nhi_ops icl_nhi_ops;
0052
0053 /*
0054  * PCI IDs used in this driver from Win Ridge forward. There is no
0055  * need for the PCI quirk anymore as we will use ICM also on Apple
0056  * hardware.
0057  */
0058 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI      0x1134
0059 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI      0x1137
0060 #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI            0x157d
0061 #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE         0x157e
0062 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI     0x15bf
0063 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE  0x15c0
0064 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI   0x15d2
0065 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE    0x15d3
0066 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI   0x15d9
0067 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE    0x15da
0068 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
0069 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI    0x15dd
0070 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI  0x15de
0071 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE   0x15e7
0072 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI      0x15e8
0073 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE   0x15ea
0074 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI      0x15eb
0075 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE   0x15ef
0076 #define PCI_DEVICE_ID_INTEL_ADL_NHI0            0x463e
0077 #define PCI_DEVICE_ID_INTEL_ADL_NHI1            0x466d
0078 #define PCI_DEVICE_ID_INTEL_ICL_NHI1            0x8a0d
0079 #define PCI_DEVICE_ID_INTEL_ICL_NHI0            0x8a17
0080 #define PCI_DEVICE_ID_INTEL_TGL_NHI0            0x9a1b
0081 #define PCI_DEVICE_ID_INTEL_TGL_NHI1            0x9a1d
0082 #define PCI_DEVICE_ID_INTEL_TGL_H_NHI0          0x9a1f
0083 #define PCI_DEVICE_ID_INTEL_TGL_H_NHI1          0x9a21
0084 #define PCI_DEVICE_ID_INTEL_RPL_NHI0            0xa73e
0085 #define PCI_DEVICE_ID_INTEL_RPL_NHI1            0xa76d
0086
0087 #define PCI_CLASS_SERIAL_USB_USB4           0x0c0340
0088
0089 #endif