Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Thunderbolt driver - eeprom access
0004  *
0005  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
0006  * Copyright (C) 2018, Intel Corporation
0007  */
0008 
0009 #include <linux/crc32.h>
0010 #include <linux/delay.h>
0011 #include <linux/property.h>
0012 #include <linux/slab.h>
0013 #include "tb.h"
0014 
0015 /*
0016  * tb_eeprom_ctl_write() - write control word
0017  */
0018 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
0019 {
0020     return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1);
0021 }
0022 
0023 /*
0024  * tb_eeprom_ctl_write() - read control word
0025  */
0026 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
0027 {
0028     return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1);
0029 }
0030 
0031 enum tb_eeprom_transfer {
0032     TB_EEPROM_IN,
0033     TB_EEPROM_OUT,
0034 };
0035 
0036 /*
0037  * tb_eeprom_active - enable rom access
0038  *
0039  * WARNING: Always disable access after usage. Otherwise the controller will
0040  * fail to reprobe.
0041  */
0042 static int tb_eeprom_active(struct tb_switch *sw, bool enable)
0043 {
0044     struct tb_eeprom_ctl ctl;
0045     int res = tb_eeprom_ctl_read(sw, &ctl);
0046     if (res)
0047         return res;
0048     if (enable) {
0049         ctl.bit_banging_enable = 1;
0050         res = tb_eeprom_ctl_write(sw, &ctl);
0051         if (res)
0052             return res;
0053         ctl.fl_cs = 0;
0054         return tb_eeprom_ctl_write(sw, &ctl);
0055     } else {
0056         ctl.fl_cs = 1;
0057         res = tb_eeprom_ctl_write(sw, &ctl);
0058         if (res)
0059             return res;
0060         ctl.bit_banging_enable = 0;
0061         return tb_eeprom_ctl_write(sw, &ctl);
0062     }
0063 }
0064 
0065 /*
0066  * tb_eeprom_transfer - transfer one bit
0067  *
0068  * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do.
0069  * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written.
0070  */
0071 static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
0072                   enum tb_eeprom_transfer direction)
0073 {
0074     int res;
0075     if (direction == TB_EEPROM_OUT) {
0076         res = tb_eeprom_ctl_write(sw, ctl);
0077         if (res)
0078             return res;
0079     }
0080     ctl->fl_sk = 1;
0081     res = tb_eeprom_ctl_write(sw, ctl);
0082     if (res)
0083         return res;
0084     if (direction == TB_EEPROM_IN) {
0085         res = tb_eeprom_ctl_read(sw, ctl);
0086         if (res)
0087             return res;
0088     }
0089     ctl->fl_sk = 0;
0090     return tb_eeprom_ctl_write(sw, ctl);
0091 }
0092 
0093 /*
0094  * tb_eeprom_out - write one byte to the bus
0095  */
0096 static int tb_eeprom_out(struct tb_switch *sw, u8 val)
0097 {
0098     struct tb_eeprom_ctl ctl;
0099     int i;
0100     int res = tb_eeprom_ctl_read(sw, &ctl);
0101     if (res)
0102         return res;
0103     for (i = 0; i < 8; i++) {
0104         ctl.fl_di = val & 0x80;
0105         res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
0106         if (res)
0107             return res;
0108         val <<= 1;
0109     }
0110     return 0;
0111 }
0112 
0113 /*
0114  * tb_eeprom_in - read one byte from the bus
0115  */
0116 static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
0117 {
0118     struct tb_eeprom_ctl ctl;
0119     int i;
0120     int res = tb_eeprom_ctl_read(sw, &ctl);
0121     if (res)
0122         return res;
0123     *val = 0;
0124     for (i = 0; i < 8; i++) {
0125         *val <<= 1;
0126         res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
0127         if (res)
0128             return res;
0129         *val |= ctl.fl_do;
0130     }
0131     return 0;
0132 }
0133 
0134 /*
0135  * tb_eeprom_get_drom_offset - get drom offset within eeprom
0136  */
0137 static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
0138 {
0139     struct tb_cap_plug_events cap;
0140     int res;
0141 
0142     if (!sw->cap_plug_events) {
0143         tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
0144         return -ENODEV;
0145     }
0146     res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
0147                  sizeof(cap) / 4);
0148     if (res)
0149         return res;
0150 
0151     if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
0152         tb_sw_warn(sw, "no NVM\n");
0153         return -ENODEV;
0154     }
0155 
0156     if (cap.drom_offset > 0xffff) {
0157         tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
0158                 cap.drom_offset);
0159         return -ENXIO;
0160     }
0161     *offset = cap.drom_offset;
0162     return 0;
0163 }
0164 
0165 /*
0166  * tb_eeprom_read_n - read count bytes from offset into val
0167  */
0168 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
0169         size_t count)
0170 {
0171     u16 drom_offset;
0172     int i, res;
0173 
0174     res = tb_eeprom_get_drom_offset(sw, &drom_offset);
0175     if (res)
0176         return res;
0177 
0178     offset += drom_offset;
0179 
0180     res = tb_eeprom_active(sw, true);
0181     if (res)
0182         return res;
0183     res = tb_eeprom_out(sw, 3);
0184     if (res)
0185         return res;
0186     res = tb_eeprom_out(sw, offset >> 8);
0187     if (res)
0188         return res;
0189     res = tb_eeprom_out(sw, offset);
0190     if (res)
0191         return res;
0192     for (i = 0; i < count; i++) {
0193         res = tb_eeprom_in(sw, val + i);
0194         if (res)
0195             return res;
0196     }
0197     return tb_eeprom_active(sw, false);
0198 }
0199 
0200 static u8 tb_crc8(u8 *data, int len)
0201 {
0202     int i, j;
0203     u8 val = 0xff;
0204     for (i = 0; i < len; i++) {
0205         val ^= data[i];
0206         for (j = 0; j < 8; j++)
0207             val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
0208     }
0209     return val;
0210 }
0211 
0212 static u32 tb_crc32(void *data, size_t len)
0213 {
0214     return ~__crc32c_le(~0, data, len);
0215 }
0216 
0217 #define TB_DROM_DATA_START      13
0218 #define TB_DROM_HEADER_SIZE     22
0219 #define USB4_DROM_HEADER_SIZE       16
0220 
0221 struct tb_drom_header {
0222     /* BYTE 0 */
0223     u8 uid_crc8; /* checksum for uid */
0224     /* BYTES 1-8 */
0225     u64 uid;
0226     /* BYTES 9-12 */
0227     u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
0228     /* BYTE 13 */
0229     u8 device_rom_revision; /* should be <= 1 */
0230     u16 data_len:12;
0231     u8 reserved:4;
0232     /* BYTES 16-21 - Only for TBT DROM, nonexistent in USB4 DROM */
0233     u16 vendor_id;
0234     u16 model_id;
0235     u8 model_rev;
0236     u8 eeprom_rev;
0237 } __packed;
0238 
0239 enum tb_drom_entry_type {
0240     /* force unsigned to prevent "one-bit signed bitfield" warning */
0241     TB_DROM_ENTRY_GENERIC = 0U,
0242     TB_DROM_ENTRY_PORT,
0243 };
0244 
0245 struct tb_drom_entry_header {
0246     u8 len;
0247     u8 index:6;
0248     bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
0249     enum tb_drom_entry_type type:1;
0250 } __packed;
0251 
0252 struct tb_drom_entry_generic {
0253     struct tb_drom_entry_header header;
0254     u8 data[];
0255 } __packed;
0256 
0257 struct tb_drom_entry_port {
0258     /* BYTES 0-1 */
0259     struct tb_drom_entry_header header;
0260     /* BYTE 2 */
0261     u8 dual_link_port_rid:4;
0262     u8 link_nr:1;
0263     u8 unknown1:2;
0264     bool has_dual_link_port:1;
0265 
0266     /* BYTE 3 */
0267     u8 dual_link_port_nr:6;
0268     u8 unknown2:2;
0269 
0270     /* BYTES 4 - 5 TODO decode */
0271     u8 micro2:4;
0272     u8 micro1:4;
0273     u8 micro3;
0274 
0275     /* BYTES 6-7, TODO: verify (find hardware that has these set) */
0276     u8 peer_port_rid:4;
0277     u8 unknown3:3;
0278     bool has_peer_port:1;
0279     u8 peer_port_nr:6;
0280     u8 unknown4:2;
0281 } __packed;
0282 
0283 /* USB4 product descriptor */
0284 struct tb_drom_entry_desc {
0285     struct tb_drom_entry_header header;
0286     u16 bcdUSBSpec;
0287     u16 idVendor;
0288     u16 idProduct;
0289     u16 bcdProductFWRevision;
0290     u32 TID;
0291     u8 productHWRevision;
0292 };
0293 
0294 /**
0295  * tb_drom_read_uid_only() - Read UID directly from DROM
0296  * @sw: Router whose UID to read
0297  * @uid: UID is placed here
0298  *
0299  * Does not use the cached copy in sw->drom. Used during resume to check switch
0300  * identity.
0301  */
0302 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
0303 {
0304     u8 data[9];
0305     u8 crc;
0306     int res;
0307 
0308     /* read uid */
0309     res = tb_eeprom_read_n(sw, 0, data, 9);
0310     if (res)
0311         return res;
0312 
0313     crc = tb_crc8(data + 1, 8);
0314     if (crc != data[0]) {
0315         tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
0316                 data[0], crc);
0317         return -EIO;
0318     }
0319 
0320     *uid = *(u64 *)(data+1);
0321     return 0;
0322 }
0323 
0324 static int tb_drom_parse_entry_generic(struct tb_switch *sw,
0325         struct tb_drom_entry_header *header)
0326 {
0327     const struct tb_drom_entry_generic *entry =
0328         (const struct tb_drom_entry_generic *)header;
0329 
0330     switch (header->index) {
0331     case 1:
0332         /* Length includes 2 bytes header so remove it before copy */
0333         sw->vendor_name = kstrndup(entry->data,
0334             header->len - sizeof(*header), GFP_KERNEL);
0335         if (!sw->vendor_name)
0336             return -ENOMEM;
0337         break;
0338 
0339     case 2:
0340         sw->device_name = kstrndup(entry->data,
0341             header->len - sizeof(*header), GFP_KERNEL);
0342         if (!sw->device_name)
0343             return -ENOMEM;
0344         break;
0345     case 9: {
0346         const struct tb_drom_entry_desc *desc =
0347             (const struct tb_drom_entry_desc *)entry;
0348 
0349         if (!sw->vendor && !sw->device) {
0350             sw->vendor = desc->idVendor;
0351             sw->device = desc->idProduct;
0352         }
0353         break;
0354     }
0355     }
0356 
0357     return 0;
0358 }
0359 
0360 static int tb_drom_parse_entry_port(struct tb_switch *sw,
0361                     struct tb_drom_entry_header *header)
0362 {
0363     struct tb_port *port;
0364     int res;
0365     enum tb_port_type type;
0366 
0367     /*
0368      * Some DROMs list more ports than the controller actually has
0369      * so we skip those but allow the parser to continue.
0370      */
0371     if (header->index > sw->config.max_port_number) {
0372         dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
0373         return 0;
0374     }
0375 
0376     port = &sw->ports[header->index];
0377     port->disabled = header->port_disabled;
0378     if (port->disabled)
0379         return 0;
0380 
0381     res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
0382     if (res)
0383         return res;
0384     type &= 0xffffff;
0385 
0386     if (type == TB_TYPE_PORT) {
0387         struct tb_drom_entry_port *entry = (void *) header;
0388         if (header->len != sizeof(*entry)) {
0389             tb_sw_warn(sw,
0390                 "port entry has size %#x (expected %#zx)\n",
0391                 header->len, sizeof(struct tb_drom_entry_port));
0392             return -EIO;
0393         }
0394         port->link_nr = entry->link_nr;
0395         if (entry->has_dual_link_port)
0396             port->dual_link_port =
0397                 &port->sw->ports[entry->dual_link_port_nr];
0398     }
0399     return 0;
0400 }
0401 
0402 /*
0403  * tb_drom_parse_entries - parse the linked list of drom entries
0404  *
0405  * Drom must have been copied to sw->drom.
0406  */
0407 static int tb_drom_parse_entries(struct tb_switch *sw, size_t header_size)
0408 {
0409     struct tb_drom_header *header = (void *) sw->drom;
0410     u16 pos = header_size;
0411     u16 drom_size = header->data_len + TB_DROM_DATA_START;
0412     int res;
0413 
0414     while (pos < drom_size) {
0415         struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
0416         if (pos + 1 == drom_size || pos + entry->len > drom_size
0417                 || !entry->len) {
0418             tb_sw_warn(sw, "DROM buffer overrun\n");
0419             return -EILSEQ;
0420         }
0421 
0422         switch (entry->type) {
0423         case TB_DROM_ENTRY_GENERIC:
0424             res = tb_drom_parse_entry_generic(sw, entry);
0425             break;
0426         case TB_DROM_ENTRY_PORT:
0427             res = tb_drom_parse_entry_port(sw, entry);
0428             break;
0429         }
0430         if (res)
0431             return res;
0432 
0433         pos += entry->len;
0434     }
0435     return 0;
0436 }
0437 
0438 /*
0439  * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
0440  */
0441 static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
0442 {
0443     struct device *dev = &sw->tb->nhi->pdev->dev;
0444     int len, res;
0445 
0446     len = device_property_count_u8(dev, "ThunderboltDROM");
0447     if (len < 0 || len < sizeof(struct tb_drom_header))
0448         return -EINVAL;
0449 
0450     sw->drom = kmalloc(len, GFP_KERNEL);
0451     if (!sw->drom)
0452         return -ENOMEM;
0453 
0454     res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
0455                                     len);
0456     if (res)
0457         goto err;
0458 
0459     *size = ((struct tb_drom_header *)sw->drom)->data_len +
0460                               TB_DROM_DATA_START;
0461     if (*size > len)
0462         goto err;
0463 
0464     return 0;
0465 
0466 err:
0467     kfree(sw->drom);
0468     sw->drom = NULL;
0469     return -EINVAL;
0470 }
0471 
0472 static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
0473 {
0474     u32 drom_offset;
0475     int ret;
0476 
0477     if (!sw->dma_port)
0478         return -ENODEV;
0479 
0480     ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
0481              sw->cap_plug_events + 12, 1);
0482     if (ret)
0483         return ret;
0484 
0485     if (!drom_offset)
0486         return -ENODEV;
0487 
0488     ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
0489                   sizeof(*size));
0490     if (ret)
0491         return ret;
0492 
0493     /* Size includes CRC8 + UID + CRC32 */
0494     *size += 1 + 8 + 4;
0495     sw->drom = kzalloc(*size, GFP_KERNEL);
0496     if (!sw->drom)
0497         return -ENOMEM;
0498 
0499     ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
0500     if (ret)
0501         goto err_free;
0502 
0503     /*
0504      * Read UID from the minimal DROM because the one in NVM is just
0505      * a placeholder.
0506      */
0507     tb_drom_read_uid_only(sw, &sw->uid);
0508     return 0;
0509 
0510 err_free:
0511     kfree(sw->drom);
0512     sw->drom = NULL;
0513     return ret;
0514 }
0515 
0516 static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size)
0517 {
0518     int ret;
0519 
0520     ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
0521     if (ret)
0522         return ret;
0523 
0524     /* Size includes CRC8 + UID + CRC32 */
0525     *size += 1 + 8 + 4;
0526     sw->drom = kzalloc(*size, GFP_KERNEL);
0527     if (!sw->drom)
0528         return -ENOMEM;
0529 
0530     ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
0531     if (ret) {
0532         kfree(sw->drom);
0533         sw->drom = NULL;
0534     }
0535 
0536     return ret;
0537 }
0538 
0539 static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
0540               size_t count)
0541 {
0542     if (tb_switch_is_usb4(sw))
0543         return usb4_switch_drom_read(sw, offset, val, count);
0544     return tb_eeprom_read_n(sw, offset, val, count);
0545 }
0546 
0547 static int tb_drom_parse(struct tb_switch *sw)
0548 {
0549     const struct tb_drom_header *header =
0550         (const struct tb_drom_header *)sw->drom;
0551     u32 crc;
0552 
0553     crc = tb_crc8((u8 *) &header->uid, 8);
0554     if (crc != header->uid_crc8) {
0555         tb_sw_warn(sw,
0556             "DROM UID CRC8 mismatch (expected: %#x, got: %#x)\n",
0557             header->uid_crc8, crc);
0558         return -EILSEQ;
0559     }
0560     if (!sw->uid)
0561         sw->uid = header->uid;
0562     sw->vendor = header->vendor_id;
0563     sw->device = header->model_id;
0564 
0565     crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
0566     if (crc != header->data_crc32) {
0567         tb_sw_warn(sw,
0568             "DROM data CRC32 mismatch (expected: %#x, got: %#x), continuing\n",
0569             header->data_crc32, crc);
0570     }
0571 
0572     return tb_drom_parse_entries(sw, TB_DROM_HEADER_SIZE);
0573 }
0574 
0575 static int usb4_drom_parse(struct tb_switch *sw)
0576 {
0577     const struct tb_drom_header *header =
0578         (const struct tb_drom_header *)sw->drom;
0579     u32 crc;
0580 
0581     crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
0582     if (crc != header->data_crc32) {
0583         tb_sw_warn(sw,
0584                "DROM data CRC32 mismatch (expected: %#x, got: %#x), aborting\n",
0585                header->data_crc32, crc);
0586         return -EINVAL;
0587     }
0588 
0589     return tb_drom_parse_entries(sw, USB4_DROM_HEADER_SIZE);
0590 }
0591 
0592 /**
0593  * tb_drom_read() - Copy DROM to sw->drom and parse it
0594  * @sw: Router whose DROM to read and parse
0595  *
0596  * This function reads router DROM and if successful parses the entries and
0597  * populates the fields in @sw accordingly. Can be called for any router
0598  * generation.
0599  *
0600  * Returns %0 in case of success and negative errno otherwise.
0601  */
0602 int tb_drom_read(struct tb_switch *sw)
0603 {
0604     u16 size;
0605     struct tb_drom_header *header;
0606     int res, retries = 1;
0607 
0608     if (sw->drom)
0609         return 0;
0610 
0611     if (tb_route(sw) == 0) {
0612         /*
0613          * Apple's NHI EFI driver supplies a DROM for the root switch
0614          * in a device property. Use it if available.
0615          */
0616         if (tb_drom_copy_efi(sw, &size) == 0)
0617             goto parse;
0618 
0619         /* Non-Apple hardware has the DROM as part of NVM */
0620         if (tb_drom_copy_nvm(sw, &size) == 0)
0621             goto parse;
0622 
0623         /*
0624          * USB4 hosts may support reading DROM through router
0625          * operations.
0626          */
0627         if (tb_switch_is_usb4(sw)) {
0628             usb4_switch_read_uid(sw, &sw->uid);
0629             if (!usb4_copy_host_drom(sw, &size))
0630                 goto parse;
0631         } else {
0632             /*
0633              * The root switch contains only a dummy drom
0634              * (header only, no entries). Hardcode the
0635              * configuration here.
0636              */
0637             tb_drom_read_uid_only(sw, &sw->uid);
0638         }
0639 
0640         return 0;
0641     }
0642 
0643     res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
0644     if (res)
0645         return res;
0646     size &= 0x3ff;
0647     size += TB_DROM_DATA_START;
0648     tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
0649     if (size < sizeof(*header)) {
0650         tb_sw_warn(sw, "drom too small, aborting\n");
0651         return -EIO;
0652     }
0653 
0654     sw->drom = kzalloc(size, GFP_KERNEL);
0655     if (!sw->drom)
0656         return -ENOMEM;
0657 read:
0658     res = tb_drom_read_n(sw, 0, sw->drom, size);
0659     if (res)
0660         goto err;
0661 
0662 parse:
0663     header = (void *) sw->drom;
0664 
0665     if (header->data_len + TB_DROM_DATA_START != size) {
0666         tb_sw_warn(sw, "drom size mismatch\n");
0667         if (retries--) {
0668             msleep(100);
0669             goto read;
0670         }
0671         goto err;
0672     }
0673 
0674     tb_sw_dbg(sw, "DROM version: %d\n", header->device_rom_revision);
0675 
0676     switch (header->device_rom_revision) {
0677     case 3:
0678         res = usb4_drom_parse(sw);
0679         break;
0680     default:
0681         tb_sw_warn(sw, "DROM device_rom_revision %#x unknown\n",
0682                header->device_rom_revision);
0683         fallthrough;
0684     case 1:
0685         res = tb_drom_parse(sw);
0686         break;
0687     }
0688 
0689     /* If the DROM parsing fails, wait a moment and retry once */
0690     if (res == -EILSEQ && retries--) {
0691         tb_sw_warn(sw, "parsing DROM failed\n");
0692         msleep(100);
0693         goto read;
0694     }
0695 
0696     if (!res)
0697         return 0;
0698 
0699 err:
0700     kfree(sw->drom);
0701     sw->drom = NULL;
0702     return -EIO;
0703 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!