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0010 #include <linux/bitops.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/regmap.h>
0018 #include <linux/thermal.h>
0019
0020 #include "thermal_core.h"
0021
0022
0023
0024
0025
0026 #define PVTCTLEN 0x0000
0027 #define PVTCTLEN_EN BIT(0)
0028
0029 #define PVTCTLMODE 0x0004
0030 #define PVTCTLMODE_MASK 0xf
0031 #define PVTCTLMODE_TEMPMON 0x5
0032
0033 #define EMONREPEAT 0x0040
0034 #define EMONREPEAT_ENDLESS BIT(24)
0035 #define EMONREPEAT_PERIOD GENMASK(3, 0)
0036 #define EMONREPEAT_PERIOD_1000000 0x9
0037
0038
0039
0040
0041
0042 #define PVTCTLSEL 0x0900
0043 #define PVTCTLSEL_MASK GENMASK(2, 0)
0044 #define PVTCTLSEL_MONITOR 0
0045
0046 #define SETALERT0 0x0910
0047 #define SETALERT1 0x0914
0048 #define SETALERT2 0x0918
0049 #define SETALERT_TEMP_OVF (GENMASK(7, 0) << 16)
0050 #define SETALERT_TEMP_OVF_VALUE(val) (((val) & GENMASK(7, 0)) << 16)
0051 #define SETALERT_EN BIT(0)
0052
0053 #define PMALERTINTCTL 0x0920
0054 #define PMALERTINTCTL_CLR(ch) BIT(4 * (ch) + 2)
0055 #define PMALERTINTCTL_SET(ch) BIT(4 * (ch) + 1)
0056 #define PMALERTINTCTL_EN(ch) BIT(4 * (ch) + 0)
0057 #define PMALERTINTCTL_MASK (GENMASK(10, 8) | GENMASK(6, 4) | \
0058 GENMASK(2, 0))
0059
0060 #define TMOD 0x0928
0061 #define TMOD_WIDTH 9
0062
0063 #define TMODCOEF 0x0e5c
0064
0065 #define TMODSETUP0_EN BIT(30)
0066 #define TMODSETUP0_VAL(val) (((val) & GENMASK(13, 0)) << 16)
0067 #define TMODSETUP1_EN BIT(15)
0068 #define TMODSETUP1_VAL(val) ((val) & GENMASK(14, 0))
0069
0070
0071 #define CRITICAL_TEMP_LIMIT (120 * 1000)
0072
0073
0074 #define ALERT_CH_NUM 3
0075
0076
0077 struct uniphier_tm_soc_data {
0078 u32 map_base;
0079 u32 block_base;
0080 u32 tmod_setup_addr;
0081 };
0082
0083 struct uniphier_tm_dev {
0084 struct regmap *regmap;
0085 struct device *dev;
0086 bool alert_en[ALERT_CH_NUM];
0087 struct thermal_zone_device *tz_dev;
0088 const struct uniphier_tm_soc_data *data;
0089 };
0090
0091 static int uniphier_tm_initialize_sensor(struct uniphier_tm_dev *tdev)
0092 {
0093 struct regmap *map = tdev->regmap;
0094 u32 val;
0095 u32 tmod_calib[2];
0096 int ret;
0097
0098
0099 regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
0100 PVTCTLEN_EN, 0);
0101
0102
0103
0104
0105
0106
0107
0108
0109 ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val);
0110 if (ret)
0111 return ret;
0112 if (!val) {
0113
0114 ret = of_property_read_u32_array(tdev->dev->of_node,
0115 "socionext,tmod-calibration",
0116 tmod_calib,
0117 ARRAY_SIZE(tmod_calib));
0118 if (ret)
0119 return ret;
0120
0121 regmap_write(map, tdev->data->tmod_setup_addr,
0122 TMODSETUP0_EN | TMODSETUP0_VAL(tmod_calib[0]) |
0123 TMODSETUP1_EN | TMODSETUP1_VAL(tmod_calib[1]));
0124 }
0125
0126
0127 regmap_write_bits(map, tdev->data->block_base + PVTCTLMODE,
0128 PVTCTLMODE_MASK, PVTCTLMODE_TEMPMON);
0129
0130
0131 regmap_write_bits(map, tdev->data->block_base + EMONREPEAT,
0132 EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD,
0133 EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD_1000000);
0134
0135
0136 regmap_write_bits(map, tdev->data->map_base + PVTCTLSEL,
0137 PVTCTLSEL_MASK, PVTCTLSEL_MONITOR);
0138
0139 return 0;
0140 }
0141
0142 static void uniphier_tm_set_alert(struct uniphier_tm_dev *tdev, u32 ch,
0143 u32 temp)
0144 {
0145 struct regmap *map = tdev->regmap;
0146
0147
0148 regmap_write_bits(map, tdev->data->map_base + SETALERT0 + (ch << 2),
0149 SETALERT_EN | SETALERT_TEMP_OVF,
0150 SETALERT_EN |
0151 SETALERT_TEMP_OVF_VALUE(temp / 1000));
0152 }
0153
0154 static void uniphier_tm_enable_sensor(struct uniphier_tm_dev *tdev)
0155 {
0156 struct regmap *map = tdev->regmap;
0157 int i;
0158 u32 bits = 0;
0159
0160 for (i = 0; i < ALERT_CH_NUM; i++)
0161 if (tdev->alert_en[i])
0162 bits |= PMALERTINTCTL_EN(i);
0163
0164
0165 regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL,
0166 PMALERTINTCTL_MASK, bits);
0167
0168
0169 regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
0170 PVTCTLEN_EN, PVTCTLEN_EN);
0171
0172 usleep_range(700, 1500);
0173 }
0174
0175 static void uniphier_tm_disable_sensor(struct uniphier_tm_dev *tdev)
0176 {
0177 struct regmap *map = tdev->regmap;
0178
0179
0180 regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL,
0181 PMALERTINTCTL_MASK, 0);
0182
0183
0184 regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
0185 PVTCTLEN_EN, 0);
0186
0187 usleep_range(1000, 2000);
0188 }
0189
0190 static int uniphier_tm_get_temp(void *data, int *out_temp)
0191 {
0192 struct uniphier_tm_dev *tdev = data;
0193 struct regmap *map = tdev->regmap;
0194 int ret;
0195 u32 temp;
0196
0197 ret = regmap_read(map, tdev->data->map_base + TMOD, &temp);
0198 if (ret)
0199 return ret;
0200
0201
0202 *out_temp = sign_extend32(temp, TMOD_WIDTH - 1) * 1000;
0203
0204 return 0;
0205 }
0206
0207 static const struct thermal_zone_of_device_ops uniphier_of_thermal_ops = {
0208 .get_temp = uniphier_tm_get_temp,
0209 };
0210
0211 static void uniphier_tm_irq_clear(struct uniphier_tm_dev *tdev)
0212 {
0213 u32 mask = 0, bits = 0;
0214 int i;
0215
0216 for (i = 0; i < ALERT_CH_NUM; i++) {
0217 mask |= (PMALERTINTCTL_CLR(i) | PMALERTINTCTL_SET(i));
0218 bits |= PMALERTINTCTL_CLR(i);
0219 }
0220
0221
0222 regmap_write_bits(tdev->regmap,
0223 tdev->data->map_base + PMALERTINTCTL, mask, bits);
0224 }
0225
0226 static irqreturn_t uniphier_tm_alarm_irq(int irq, void *_tdev)
0227 {
0228 struct uniphier_tm_dev *tdev = _tdev;
0229
0230 disable_irq_nosync(irq);
0231 uniphier_tm_irq_clear(tdev);
0232
0233 return IRQ_WAKE_THREAD;
0234 }
0235
0236 static irqreturn_t uniphier_tm_alarm_irq_thread(int irq, void *_tdev)
0237 {
0238 struct uniphier_tm_dev *tdev = _tdev;
0239
0240 thermal_zone_device_update(tdev->tz_dev, THERMAL_EVENT_UNSPECIFIED);
0241
0242 return IRQ_HANDLED;
0243 }
0244
0245 static int uniphier_tm_probe(struct platform_device *pdev)
0246 {
0247 struct device *dev = &pdev->dev;
0248 struct regmap *regmap;
0249 struct device_node *parent;
0250 struct uniphier_tm_dev *tdev;
0251 const struct thermal_trip *trips;
0252 int i, ret, irq, ntrips, crit_temp = INT_MAX;
0253
0254 tdev = devm_kzalloc(dev, sizeof(*tdev), GFP_KERNEL);
0255 if (!tdev)
0256 return -ENOMEM;
0257 tdev->dev = dev;
0258
0259 tdev->data = of_device_get_match_data(dev);
0260 if (WARN_ON(!tdev->data))
0261 return -EINVAL;
0262
0263 irq = platform_get_irq(pdev, 0);
0264 if (irq < 0)
0265 return irq;
0266
0267
0268 parent = of_get_parent(dev->of_node);
0269 regmap = syscon_node_to_regmap(parent);
0270 of_node_put(parent);
0271 if (IS_ERR(regmap)) {
0272 dev_err(dev, "failed to get regmap (error %ld)\n",
0273 PTR_ERR(regmap));
0274 return PTR_ERR(regmap);
0275 }
0276 tdev->regmap = regmap;
0277
0278 ret = uniphier_tm_initialize_sensor(tdev);
0279 if (ret) {
0280 dev_err(dev, "failed to initialize sensor\n");
0281 return ret;
0282 }
0283
0284 ret = devm_request_threaded_irq(dev, irq, uniphier_tm_alarm_irq,
0285 uniphier_tm_alarm_irq_thread,
0286 0, "thermal", tdev);
0287 if (ret)
0288 return ret;
0289
0290 platform_set_drvdata(pdev, tdev);
0291
0292 tdev->tz_dev = devm_thermal_zone_of_sensor_register(dev, 0, tdev,
0293 &uniphier_of_thermal_ops);
0294 if (IS_ERR(tdev->tz_dev)) {
0295 dev_err(dev, "failed to register sensor device\n");
0296 return PTR_ERR(tdev->tz_dev);
0297 }
0298
0299
0300 trips = of_thermal_get_trip_points(tdev->tz_dev);
0301 ntrips = of_thermal_get_ntrips(tdev->tz_dev);
0302 if (ntrips > ALERT_CH_NUM) {
0303 dev_err(dev, "thermal zone has too many trips\n");
0304 return -E2BIG;
0305 }
0306
0307
0308 for (i = 0; i < ntrips; i++) {
0309 if (trips[i].type == THERMAL_TRIP_CRITICAL &&
0310 trips[i].temperature < crit_temp)
0311 crit_temp = trips[i].temperature;
0312 uniphier_tm_set_alert(tdev, i, trips[i].temperature);
0313 tdev->alert_en[i] = true;
0314 }
0315 if (crit_temp > CRITICAL_TEMP_LIMIT) {
0316 dev_err(dev, "critical trip is over limit(>%d), or not set\n",
0317 CRITICAL_TEMP_LIMIT);
0318 return -EINVAL;
0319 }
0320
0321 uniphier_tm_enable_sensor(tdev);
0322
0323 return 0;
0324 }
0325
0326 static int uniphier_tm_remove(struct platform_device *pdev)
0327 {
0328 struct uniphier_tm_dev *tdev = platform_get_drvdata(pdev);
0329
0330
0331 uniphier_tm_disable_sensor(tdev);
0332
0333 return 0;
0334 }
0335
0336 static const struct uniphier_tm_soc_data uniphier_pxs2_tm_data = {
0337 .map_base = 0xe000,
0338 .block_base = 0xe000,
0339 .tmod_setup_addr = 0xe904,
0340 };
0341
0342 static const struct uniphier_tm_soc_data uniphier_ld20_tm_data = {
0343 .map_base = 0xe000,
0344 .block_base = 0xe800,
0345 .tmod_setup_addr = 0xe938,
0346 };
0347
0348 static const struct of_device_id uniphier_tm_dt_ids[] = {
0349 {
0350 .compatible = "socionext,uniphier-pxs2-thermal",
0351 .data = &uniphier_pxs2_tm_data,
0352 },
0353 {
0354 .compatible = "socionext,uniphier-ld20-thermal",
0355 .data = &uniphier_ld20_tm_data,
0356 },
0357 {
0358 .compatible = "socionext,uniphier-pxs3-thermal",
0359 .data = &uniphier_ld20_tm_data,
0360 },
0361 {
0362 .compatible = "socionext,uniphier-nx1-thermal",
0363 .data = &uniphier_ld20_tm_data,
0364 },
0365 { }
0366 };
0367 MODULE_DEVICE_TABLE(of, uniphier_tm_dt_ids);
0368
0369 static struct platform_driver uniphier_tm_driver = {
0370 .probe = uniphier_tm_probe,
0371 .remove = uniphier_tm_remove,
0372 .driver = {
0373 .name = "uniphier-thermal",
0374 .of_match_table = uniphier_tm_dt_ids,
0375 },
0376 };
0377 module_platform_driver(uniphier_tm_driver);
0378
0379 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
0380 MODULE_DESCRIPTION("UniPhier thermal driver");
0381 MODULE_LICENSE("GPL v2");