thermal/ti-soc-thermal/omap5xxx-bandgap.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP5xxx bandgap registers, bitfields and temperature definitions
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
0006  * Contact:
0007  *   Eduardo Valentin <eduardo.valentin@ti.com>
0008  */
0009 #ifndef __OMAP5XXX_BANDGAP_H
0010 #define __OMAP5XXX_BANDGAP_H
0011
0012 /**
0013  * *** OMAP5430 ***
0014  *
0015  * Below, in sequence, are the Register definitions,
0016  * the bitfields and the temperature definitions for OMAP5430.
0017  */
0018
0019 /**
0020  * OMAP5430 register definitions
0021  *
0022  * Registers are defined as offsets. The offsets are
0023  * relative to FUSE_OPP_BGAP_GPU on 5430.
0024  *
0025  * Register below are grouped by domain (not necessarily in offset order)
0026  */
0027
0028 /* OMAP5430.GPU register offsets */
0029 #define OMAP5430_FUSE_OPP_BGAP_GPU          0x0
0030 #define OMAP5430_TEMP_SENSOR_GPU_OFFSET         0x150
0031 #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET      0x1A8
0032 #define OMAP5430_BGAP_TSHUT_GPU_OFFSET          0x1B4
0033 #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET        0x1F8
0034 #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET        0x1FC
0035
0036 /* OMAP5430.MPU register offsets */
0037 #define OMAP5430_FUSE_OPP_BGAP_MPU          0x4
0038 #define OMAP5430_TEMP_SENSOR_MPU_OFFSET         0x14C
0039 #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET      0x1A4
0040 #define OMAP5430_BGAP_TSHUT_MPU_OFFSET          0x1B0
0041 #define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET        0x1E4
0042 #define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET        0x1E8
0043
0044 /* OMAP5430.MPU register offsets */
0045 #define OMAP5430_FUSE_OPP_BGAP_CORE         0x8
0046 #define OMAP5430_TEMP_SENSOR_CORE_OFFSET        0x154
0047 #define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET     0x1AC
0048 #define OMAP5430_BGAP_TSHUT_CORE_OFFSET         0x1B8
0049 #define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET       0x20C
0050 #define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET       0x210
0051
0052 /* OMAP5430.common register offsets */
0053 #define OMAP5430_BGAP_CTRL_OFFSET           0x1A0
0054 #define OMAP5430_BGAP_STATUS_OFFSET         0x1C8
0055
0056 /**
0057  * Register bitfields for OMAP5430
0058  *
0059  * All the macros bellow define the required bits for
0060  * controlling temperature on OMAP5430. Bit defines are
0061  * grouped by register.
0062  */
0063
0064 /* OMAP5430.TEMP_SENSOR */
0065 #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK      BIT(12)
0066 #define OMAP5430_BGAP_TEMPSOFF_MASK         BIT(11)
0067 #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK     BIT(10)
0068 #define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK        (0x3ff << 0)
0069
0070 /* OMAP5430.BANDGAP_CTRL */
0071 #define OMAP5430_MASK_COUNTER_DELAY_MASK        (0x7 << 27)
0072 #define OMAP5430_MASK_FREEZE_CORE_MASK          BIT(23)
0073 #define OMAP5430_MASK_FREEZE_GPU_MASK           BIT(22)
0074 #define OMAP5430_MASK_FREEZE_MPU_MASK           BIT(21)
0075 #define OMAP5430_MASK_HOT_CORE_MASK         BIT(5)
0076 #define OMAP5430_MASK_COLD_CORE_MASK            BIT(4)
0077 #define OMAP5430_MASK_HOT_GPU_MASK          BIT(3)
0078 #define OMAP5430_MASK_COLD_GPU_MASK         BIT(2)
0079 #define OMAP5430_MASK_HOT_MPU_MASK          BIT(1)
0080 #define OMAP5430_MASK_COLD_MPU_MASK         BIT(0)
0081
0082 /* OMAP5430.BANDGAP_COUNTER */
0083 #define OMAP5430_COUNTER_MASK               (0xffffff << 0)
0084
0085 /* OMAP5430.BANDGAP_THRESHOLD */
0086 #define OMAP5430_T_HOT_MASK             (0x3ff << 16)
0087 #define OMAP5430_T_COLD_MASK                (0x3ff << 0)
0088
0089 /* OMAP5430.TSHUT_THRESHOLD */
0090 #define OMAP5430_TSHUT_HOT_MASK             (0x3ff << 16)
0091 #define OMAP5430_TSHUT_COLD_MASK            (0x3ff << 0)
0092
0093 /* OMAP5430.BANDGAP_STATUS */
0094 #define OMAP5430_HOT_CORE_FLAG_MASK         BIT(5)
0095 #define OMAP5430_COLD_CORE_FLAG_MASK            BIT(4)
0096 #define OMAP5430_HOT_GPU_FLAG_MASK          BIT(3)
0097 #define OMAP5430_COLD_GPU_FLAG_MASK         BIT(2)
0098 #define OMAP5430_HOT_MPU_FLAG_MASK          BIT(1)
0099 #define OMAP5430_COLD_MPU_FLAG_MASK         BIT(0)
0100
0101 /**
0102  * Temperature limits and thresholds for OMAP5430
0103  *
0104  * All the macros bellow are definitions for handling the
0105  * ADC conversions and representation of temperature limits
0106  * and thresholds for OMAP5430. Definitions are grouped
0107  * by temperature domain.
0108  */
0109
0110 /* OMAP5430.common temperature definitions */
0111 /* ADC conversion table limits */
0112 #define OMAP5430_ADC_START_VALUE            540
0113 #define OMAP5430_ADC_END_VALUE              945
0114
0115 /* OMAP5430.GPU temperature definitions */
0116 /* bandgap clock limits */
0117 #define OMAP5430_GPU_MAX_FREQ               1500000
0118 #define OMAP5430_GPU_MIN_FREQ               1000000
0119 /* interrupts thresholds */
0120 #define OMAP5430_GPU_TSHUT_HOT              915
0121 #define OMAP5430_GPU_TSHUT_COLD             900
0122 #define OMAP5430_GPU_T_HOT              800
0123 #define OMAP5430_GPU_T_COLD             795
0124
0125 /* OMAP5430.MPU temperature definitions */
0126 /* bandgap clock limits */
0127 #define OMAP5430_MPU_MAX_FREQ               1500000
0128 #define OMAP5430_MPU_MIN_FREQ               1000000
0129 /* interrupts thresholds */
0130 #define OMAP5430_MPU_TSHUT_HOT              915
0131 #define OMAP5430_MPU_TSHUT_COLD             900
0132 #define OMAP5430_MPU_T_HOT              800
0133 #define OMAP5430_MPU_T_COLD             795
0134
0135 /* OMAP5430.CORE temperature definitions */
0136 /* bandgap clock limits */
0137 #define OMAP5430_CORE_MAX_FREQ              1500000
0138 #define OMAP5430_CORE_MIN_FREQ              1000000
0139 /* interrupts thresholds */
0140 #define OMAP5430_CORE_TSHUT_HOT             915
0141 #define OMAP5430_CORE_TSHUT_COLD            900
0142 #define OMAP5430_CORE_T_HOT             800
0143 #define OMAP5430_CORE_T_COLD                795
0144
0145 #endif /* __OMAP5XXX_BANDGAP_H */