thermal/ti-soc-thermal/dra752-thermal-data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DRA752 thermal data.
0004  *
0005  * Copyright (C) 2013 Texas Instruments Inc.
0006  * Contact:
0007  *  Eduardo Valentin <eduardo.valentin@ti.com>
0008  *  Tero Kristo <t-kristo@ti.com>
0009  *
0010  * This file is partially autogenerated.
0011  */
0012
0013 #include "ti-thermal.h"
0014 #include "ti-bandgap.h"
0015 #include "dra752-bandgap.h"
0016
0017 /*
0018  * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
0019  * IVA and DSPEVE need to describe the individual registers and
0020  * bit fields.
0021  */
0022
0023 /*
0024  * DRA752 CORE thermal sensor register offsets and bit-fields
0025  */
0026 static struct temp_sensor_registers
0027 dra752_core_temp_sensor_registers = {
0028     .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
0029     .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
0030     .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
0031     .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
0032     .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
0033     .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
0034     .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
0035     .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
0036     .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
0037     .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
0038     .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
0039     .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
0040     .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
0041     .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
0042     .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
0043     .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
0044     .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
0045     .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
0046 };
0047
0048 /*
0049  * DRA752 IVA thermal sensor register offsets and bit-fields
0050  */
0051 static struct temp_sensor_registers
0052 dra752_iva_temp_sensor_registers = {
0053     .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
0054     .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
0055     .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
0056     .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
0057     .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
0058     .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
0059     .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
0060     .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
0061     .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
0062     .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
0063     .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
0064     .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
0065     .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
0066     .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
0067     .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
0068     .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
0069     .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
0070     .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
0071 };
0072
0073 /*
0074  * DRA752 MPU thermal sensor register offsets and bit-fields
0075  */
0076 static struct temp_sensor_registers
0077 dra752_mpu_temp_sensor_registers = {
0078     .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
0079     .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
0080     .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
0081     .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
0082     .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
0083     .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
0084     .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
0085     .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
0086     .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
0087     .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
0088     .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
0089     .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
0090     .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
0091     .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
0092     .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
0093     .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
0094     .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
0095     .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
0096 };
0097
0098 /*
0099  * DRA752 DSPEVE thermal sensor register offsets and bit-fields
0100  */
0101 static struct temp_sensor_registers
0102 dra752_dspeve_temp_sensor_registers = {
0103     .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
0104     .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
0105     .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
0106     .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
0107     .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
0108     .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
0109     .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
0110     .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
0111     .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
0112     .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
0113     .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
0114     .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
0115     .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
0116     .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
0117     .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
0118     .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
0119     .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
0120     .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
0121 };
0122
0123 /*
0124  * DRA752 GPU thermal sensor register offsets and bit-fields
0125  */
0126 static struct temp_sensor_registers
0127 dra752_gpu_temp_sensor_registers = {
0128     .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
0129     .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
0130     .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
0131     .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
0132     .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
0133     .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
0134     .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
0135     .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
0136     .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
0137     .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
0138     .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
0139     .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
0140     .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
0141     .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
0142     .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
0143     .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
0144     .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
0145     .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
0146 };
0147
0148 /* Thresholds and limits for DRA752 MPU temperature sensor */
0149 static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
0150     .t_hot = DRA752_MPU_T_HOT,
0151     .t_cold = DRA752_MPU_T_COLD,
0152     .min_freq = DRA752_MPU_MIN_FREQ,
0153     .max_freq = DRA752_MPU_MAX_FREQ,
0154 };
0155
0156 /* Thresholds and limits for DRA752 GPU temperature sensor */
0157 static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
0158     .t_hot = DRA752_GPU_T_HOT,
0159     .t_cold = DRA752_GPU_T_COLD,
0160     .min_freq = DRA752_GPU_MIN_FREQ,
0161     .max_freq = DRA752_GPU_MAX_FREQ,
0162 };
0163
0164 /* Thresholds and limits for DRA752 CORE temperature sensor */
0165 static struct temp_sensor_data dra752_core_temp_sensor_data = {
0166     .t_hot = DRA752_CORE_T_HOT,
0167     .t_cold = DRA752_CORE_T_COLD,
0168     .min_freq = DRA752_CORE_MIN_FREQ,
0169     .max_freq = DRA752_CORE_MAX_FREQ,
0170 };
0171
0172 /* Thresholds and limits for DRA752 DSPEVE temperature sensor */
0173 static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
0174     .t_hot = DRA752_DSPEVE_T_HOT,
0175     .t_cold = DRA752_DSPEVE_T_COLD,
0176     .min_freq = DRA752_DSPEVE_MIN_FREQ,
0177     .max_freq = DRA752_DSPEVE_MAX_FREQ,
0178 };
0179
0180 /* Thresholds and limits for DRA752 IVA temperature sensor */
0181 static struct temp_sensor_data dra752_iva_temp_sensor_data = {
0182     .t_hot = DRA752_IVA_T_HOT,
0183     .t_cold = DRA752_IVA_T_COLD,
0184     .min_freq = DRA752_IVA_MIN_FREQ,
0185     .max_freq = DRA752_IVA_MAX_FREQ,
0186 };
0187
0188 /*
0189  * DRA752 : Temperature values in milli degree celsius
0190  * ADC code values from 540 to 945
0191  */
0192 static
0193 int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
0194     /* Index 540 - 549 */
0195     -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
0196     -37800,
0197     /* Index 550 - 559 */
0198     -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
0199     -33400,
0200     /* Index 560 - 569 */
0201     -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
0202     -29400,
0203     /* Index 570 - 579 */
0204     -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
0205     -25000,
0206     /* Index 580 - 589 */
0207     -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
0208     -21000,
0209     /* Index 590 - 599 */
0210     -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
0211     -16600,
0212     /* Index 600 - 609 */
0213     -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
0214     -12500,
0215     /* Index 610 - 619 */
0216     -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
0217     -8200,
0218     /* Index 620 - 629 */
0219     -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
0220     -3900,
0221     /* Index 630 - 639 */
0222     -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
0223     200,
0224     /* Index 640 - 649 */
0225     600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
0226     4500,
0227     /* Index 650 - 659 */
0228     5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
0229     8600,
0230     /* Index 660 - 669 */
0231     9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
0232     12700,
0233     /* Index 670 - 679 */
0234     13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
0235     17000,
0236     /* Index 680 - 689 */
0237     17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
0238     21000,
0239     /* Index 690 - 699 */
0240     21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
0241     25400,
0242     /* Index 700 - 709 */
0243     25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
0244     29400,
0245     /* Index 710 - 719 */
0246     29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
0247     33800,
0248     /* Index 720 - 729 */
0249     34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
0250     37800,
0251     /* Index 730 - 739 */
0252     38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
0253     41800,
0254     /* Index 740 - 749 */
0255     42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
0256     46200,
0257     /* Index 750 - 759 */
0258     46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
0259     50200,
0260     /* Index 760 - 769 */
0261     50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
0262     54200,
0263     /* Index 770 - 779 */
0264     54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
0265     58600,
0266     /* Index 780 - 789 */
0267     59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
0268     62600,
0269     /* Index 790 - 799 */
0270     63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
0271     66600,
0272     /* Index 800 - 809 */
0273     67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
0274     70600,
0275     /* Index 810 - 819 */
0276     71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
0277     75000,
0278     /* Index 820 - 829 */
0279     75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
0280     79000,
0281     /* Index 830 - 839 */
0282     79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
0283     83000,
0284     /* Index 840 - 849 */
0285     83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
0286     87000,
0287     /* Index 850 - 859 */
0288     87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
0289     91000,
0290     /* Index 860 - 869 */
0291     91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
0292     95000,
0293     /* Index 870 - 879 */
0294     95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
0295     99400,
0296     /* Index 880 - 889 */
0297     99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
0298     103400,
0299     /* Index 890 - 899 */
0300     103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
0301     107400,
0302     /* Index 900 - 909 */
0303     107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
0304     111400,
0305     /* Index 910 - 919 */
0306     111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
0307     115400,
0308     /* Index 920 - 929 */
0309     115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
0310     119400,
0311     /* Index 930 - 939 */
0312     119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
0313     123400,
0314     /* Index 940 - 945 */
0315     123800, 124200, 124600, 124900, 125000, 125000,
0316 };
0317
0318 /* DRA752 data */
0319 const struct ti_bandgap_data dra752_data = {
0320     .features = TI_BANDGAP_FEATURE_FREEZE_BIT |
0321             TI_BANDGAP_FEATURE_TALERT |
0322             TI_BANDGAP_FEATURE_COUNTER_DELAY |
0323             TI_BANDGAP_FEATURE_HISTORY_BUFFER |
0324             TI_BANDGAP_FEATURE_ERRATA_814,
0325     .fclock_name = "l3instr_ts_gclk_div",
0326     .div_ck_name = "l3instr_ts_gclk_div",
0327     .conv_table = dra752_adc_to_temp,
0328     .adc_start_val = DRA752_ADC_START_VALUE,
0329     .adc_end_val = DRA752_ADC_END_VALUE,
0330     .expose_sensor = ti_thermal_expose_sensor,
0331     .remove_sensor = ti_thermal_remove_sensor,
0332     .sensors = {
0333         {
0334         .registers = &dra752_mpu_temp_sensor_registers,
0335         .ts_data = &dra752_mpu_temp_sensor_data,
0336         .domain = "cpu",
0337         .register_cooling = ti_thermal_register_cpu_cooling,
0338         .unregister_cooling = ti_thermal_unregister_cpu_cooling,
0339         .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
0340         .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
0341         },
0342         {
0343         .registers = &dra752_gpu_temp_sensor_registers,
0344         .ts_data = &dra752_gpu_temp_sensor_data,
0345         .domain = "gpu",
0346         .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
0347         .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
0348         },
0349         {
0350         .registers = &dra752_core_temp_sensor_registers,
0351         .ts_data = &dra752_core_temp_sensor_data,
0352         .domain = "core",
0353         .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
0354         .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
0355         },
0356         {
0357         .registers = &dra752_dspeve_temp_sensor_registers,
0358         .ts_data = &dra752_dspeve_temp_sensor_data,
0359         .domain = "dspeve",
0360         .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
0361         .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
0362         },
0363         {
0364         .registers = &dra752_iva_temp_sensor_registers,
0365         .ts_data = &dra752_iva_temp_sensor_data,
0366         .domain = "iva",
0367         .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
0368         .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
0369         },
0370     },
0371     .sensor_count = 5,
0372 };