thermal/ti-soc-thermal/dra752-bandgap.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * DRA752 bandgap registers, bitfields and temperature definitions
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
0006  * Contact:
0007  *   Eduardo Valentin <eduardo.valentin@ti.com>
0008  *   Tero Kristo <t-kristo@ti.com>
0009  *
0010  * This is an auto generated file.
0011  */
0012 #ifndef __DRA752_BANDGAP_H
0013 #define __DRA752_BANDGAP_H
0014
0015 /**
0016  * *** DRA752 ***
0017  *
0018  * Below, in sequence, are the Register definitions,
0019  * the bitfields and the temperature definitions for DRA752.
0020  */
0021
0022 /**
0023  * DRA752 register definitions
0024  *
0025  * Registers are defined as offsets. The offsets are
0026  * relative to FUSE_OPP_BGAP_GPU on DRA752.
0027  * DRA752_BANDGAP_BASE      0x4a0021e0
0028  *
0029  * Register below are grouped by domain (not necessarily in offset order)
0030  */
0031
0032
0033 /* DRA752.common register offsets */
0034 #define DRA752_BANDGAP_CTRL_1_OFFSET        0x1a0
0035 #define DRA752_BANDGAP_STATUS_1_OFFSET      0x1c8
0036 #define DRA752_BANDGAP_CTRL_2_OFFSET        0x39c
0037 #define DRA752_BANDGAP_STATUS_2_OFFSET      0x3b8
0038
0039 /* DRA752.core register offsets */
0040 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET        0x8
0041 #define DRA752_TEMP_SENSOR_CORE_OFFSET          0x154
0042 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET        0x1ac
0043 #define DRA752_DTEMP_CORE_1_OFFSET          0x20c
0044 #define DRA752_DTEMP_CORE_2_OFFSET          0x210
0045
0046 /* DRA752.iva register offsets */
0047 #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET     0x388
0048 #define DRA752_TEMP_SENSOR_IVA_OFFSET           0x398
0049 #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET     0x3a4
0050 #define DRA752_DTEMP_IVA_1_OFFSET           0x3d4
0051 #define DRA752_DTEMP_IVA_2_OFFSET           0x3d8
0052
0053 /* DRA752.mpu register offsets */
0054 #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET     0x4
0055 #define DRA752_TEMP_SENSOR_MPU_OFFSET           0x14c
0056 #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET     0x1a4
0057 #define DRA752_DTEMP_MPU_1_OFFSET           0x1e4
0058 #define DRA752_DTEMP_MPU_2_OFFSET           0x1e8
0059
0060 /* DRA752.dspeve register offsets */
0061 #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET          0x384
0062 #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET            0x394
0063 #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET          0x3a0
0064 #define DRA752_DTEMP_DSPEVE_1_OFFSET                0x3c0
0065 #define DRA752_DTEMP_DSPEVE_2_OFFSET                0x3c4
0066
0067 /* DRA752.gpu register offsets */
0068 #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET     0x0
0069 #define DRA752_TEMP_SENSOR_GPU_OFFSET           0x150
0070 #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET     0x1a8
0071 #define DRA752_DTEMP_GPU_1_OFFSET           0x1f8
0072 #define DRA752_DTEMP_GPU_2_OFFSET           0x1fc
0073
0074 /**
0075  * Register bitfields for DRA752
0076  *
0077  * All the macros bellow define the required bits for
0078  * controlling temperature on DRA752. Bit defines are
0079  * grouped by register.
0080  */
0081
0082 /* DRA752.BANDGAP_STATUS_1 */
0083 #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK       BIT(5)
0084 #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK      BIT(4)
0085 #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK        BIT(3)
0086 #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK       BIT(2)
0087 #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK        BIT(1)
0088 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK       BIT(0)
0089
0090 /* DRA752.BANDGAP_CTRL_2 */
0091 #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK           BIT(22)
0092 #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK        BIT(21)
0093 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK         BIT(3)
0094 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK        BIT(2)
0095 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK      BIT(1)
0096 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK     BIT(0)
0097
0098 /* DRA752.BANDGAP_STATUS_2 */
0099 #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK            BIT(3)
0100 #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK           BIT(2)
0101 #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK         BIT(1)
0102 #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK        BIT(0)
0103
0104 /* DRA752.BANDGAP_CTRL_1 */
0105 #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK        (0x7 << 27)
0106 #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK          BIT(23)
0107 #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK           BIT(22)
0108 #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK           BIT(21)
0109 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK        BIT(5)
0110 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK       BIT(4)
0111 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK         BIT(3)
0112 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK        BIT(2)
0113 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK         BIT(1)
0114 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK        BIT(0)
0115
0116 /* DRA752.TEMP_SENSOR */
0117 #define DRA752_TEMP_SENSOR_TMPSOFF_MASK     BIT(11)
0118 #define DRA752_TEMP_SENSOR_EOCZ_MASK        BIT(10)
0119 #define DRA752_TEMP_SENSOR_DTEMP_MASK       (0x3ff << 0)
0120
0121 /* DRA752.BANDGAP_THRESHOLD */
0122 #define DRA752_BANDGAP_THRESHOLD_HOT_MASK       (0x3ff << 16)
0123 #define DRA752_BANDGAP_THRESHOLD_COLD_MASK      (0x3ff << 0)
0124
0125 /**
0126  * Temperature limits and thresholds for DRA752
0127  *
0128  * All the macros bellow are definitions for handling the
0129  * ADC conversions and representation of temperature limits
0130  * and thresholds for DRA752. Definitions are grouped
0131  * by temperature domain.
0132  */
0133
0134 /* DRA752.common temperature definitions */
0135 /* ADC conversion table limits */
0136 #define DRA752_ADC_START_VALUE      540
0137 #define DRA752_ADC_END_VALUE        945
0138
0139 /* DRA752.GPU temperature definitions */
0140 /* bandgap clock limits */
0141 #define DRA752_GPU_MAX_FREQ             1500000
0142 #define DRA752_GPU_MIN_FREQ             1000000
0143 /* interrupts thresholds */
0144 #define DRA752_GPU_T_HOT                800
0145 #define DRA752_GPU_T_COLD               795
0146
0147 /* DRA752.MPU temperature definitions */
0148 /* bandgap clock limits */
0149 #define DRA752_MPU_MAX_FREQ             1500000
0150 #define DRA752_MPU_MIN_FREQ             1000000
0151 /* interrupts thresholds */
0152 #define DRA752_MPU_T_HOT                800
0153 #define DRA752_MPU_T_COLD               795
0154
0155 /* DRA752.CORE temperature definitions */
0156 /* bandgap clock limits */
0157 #define DRA752_CORE_MAX_FREQ                1500000
0158 #define DRA752_CORE_MIN_FREQ                1000000
0159 /* interrupts thresholds */
0160 #define DRA752_CORE_T_HOT               800
0161 #define DRA752_CORE_T_COLD              795
0162
0163 /* DRA752.DSPEVE temperature definitions */
0164 /* bandgap clock limits */
0165 #define DRA752_DSPEVE_MAX_FREQ              1500000
0166 #define DRA752_DSPEVE_MIN_FREQ              1000000
0167 /* interrupts thresholds */
0168 #define DRA752_DSPEVE_T_HOT             800
0169 #define DRA752_DSPEVE_T_COLD                795
0170
0171 /* DRA752.IVA temperature definitions */
0172 /* bandgap clock limits */
0173 #define DRA752_IVA_MAX_FREQ             1500000
0174 #define DRA752_IVA_MIN_FREQ             1000000
0175 /* interrupts thresholds */
0176 #define DRA752_IVA_T_HOT                800
0177 #define DRA752_IVA_T_COLD               795
0178
0179 #endif /* __DRA752_BANDGAP_H */