thermal/tegra/tegra30-tsensor.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Tegra30 SoC Thermal Sensor driver
0004  *
0005  * Based on downstream HWMON driver from NVIDIA.
0006  * Copyright (C) 2011 NVIDIA Corporation
0007  *
0008  * Author: Dmitry Osipenko <digetx@gmail.com>
0009  * Copyright (C) 2021 GRATE-DRIVER project
0010  */
0011
0012 #include <linux/bitfield.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/errno.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/iopoll.h>
0019 #include <linux/math.h>
0020 #include <linux/module.h>
0021 #include <linux/of_device.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/pm.h>
0024 #include <linux/reset.h>
0025 #include <linux/slab.h>
0026 #include <linux/thermal.h>
0027 #include <linux/types.h>
0028
0029 #include <soc/tegra/fuse.h>
0030
0031 #include "../thermal_core.h"
0032 #include "../thermal_hwmon.h"
0033
0034 #define TSENSOR_SENSOR0_CONFIG0             0x0
0035 #define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP     BIT(0)
0036 #define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN      BIT(1)
0037 #define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN      BIT(2)
0038 #define TSENSOR_SENSOR0_CONFIG0_DVFS_EN         BIT(3)
0039 #define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN    BIT(4)
0040 #define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5)
0041 #define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6)
0042 #define TSENSOR_SENSOR0_CONFIG0_M           GENMASK(23,  8)
0043 #define TSENSOR_SENSOR0_CONFIG0_N           GENMASK(31, 24)
0044
0045 #define TSENSOR_SENSOR0_CONFIG1             0x8
0046 #define TSENSOR_SENSOR0_CONFIG1_TH1         GENMASK(15,  0)
0047 #define TSENSOR_SENSOR0_CONFIG1_TH2         GENMASK(31, 16)
0048
0049 #define TSENSOR_SENSOR0_CONFIG2             0xc
0050 #define TSENSOR_SENSOR0_CONFIG2_TH3         GENMASK(15,  0)
0051
0052 #define TSENSOR_SENSOR0_STATUS0             0x18
0053 #define TSENSOR_SENSOR0_STATUS0_STATE           GENMASK(2, 0)
0054 #define TSENSOR_SENSOR0_STATUS0_INTR            BIT(8)
0055 #define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID       BIT(9)
0056
0057 #define TSENSOR_SENSOR0_TS_STATUS1          0x1c
0058 #define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT    GENMASK(31, 16)
0059
0060 #define TEGRA30_FUSE_TEST_PROG_VER          0x28
0061
0062 #define TEGRA30_FUSE_TSENSOR_CALIB          0x98
0063 #define TEGRA30_FUSE_TSENSOR_CALIB_LOW          GENMASK(15,  0)
0064 #define TEGRA30_FUSE_TSENSOR_CALIB_HIGH         GENMASK(31, 16)
0065
0066 #define TEGRA30_FUSE_SPARE_BIT              0x144
0067
0068 struct tegra_tsensor;
0069
0070 struct tegra_tsensor_calibration_data {
0071     int a, b, m, n, p, r;
0072 };
0073
0074 struct tegra_tsensor_channel {
0075     void __iomem *regs;
0076     unsigned int id;
0077     struct tegra_tsensor *ts;
0078     struct thermal_zone_device *tzd;
0079 };
0080
0081 struct tegra_tsensor {
0082     void __iomem *regs;
0083     bool swap_channels;
0084     struct clk *clk;
0085     struct device *dev;
0086     struct reset_control *rst;
0087     struct tegra_tsensor_channel ch[2];
0088     struct tegra_tsensor_calibration_data calib;
0089 };
0090
0091 static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts)
0092 {
0093     u32 val;
0094     int err;
0095
0096     err = reset_control_assert(ts->rst);
0097     if (err) {
0098         dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
0099         return err;
0100     }
0101
0102     err = clk_prepare_enable(ts->clk);
0103     if (err) {
0104         dev_err(ts->dev, "failed to enable clock: %d\n", err);
0105         return err;
0106     }
0107
0108     fsleep(1000);
0109
0110     err = reset_control_deassert(ts->rst);
0111     if (err) {
0112         dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err);
0113         goto disable_clk;
0114     }
0115
0116     /*
0117      * Sensors are enabled after reset by default, but not gauging
0118      * until clock counter is programmed.
0119      *
0120      * M: number of reference clock pulses after which every
0121      *    temperature / voltage measurement is made
0122      *
0123      * N: number of reference clock counts for which the counter runs
0124      */
0125     val  = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500);
0126     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255);
0127
0128     /* apply the same configuration to both channels */
0129     writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);
0130     writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);
0131
0132     return 0;
0133
0134 disable_clk:
0135     clk_disable_unprepare(ts->clk);
0136
0137     return err;
0138 }
0139
0140 static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts)
0141 {
0142     int err;
0143
0144     err = reset_control_assert(ts->rst);
0145     if (err) {
0146         dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
0147         return err;
0148     }
0149
0150     clk_disable_unprepare(ts->clk);
0151
0152     return 0;
0153 }
0154
0155 static void devm_tegra_tsensor_hw_disable(void *data)
0156 {
0157     const struct tegra_tsensor *ts = data;
0158
0159     tegra_tsensor_hw_disable(ts);
0160 }
0161
0162 static int tegra_tsensor_get_temp(void *data, int *temp)
0163 {
0164     const struct tegra_tsensor_channel *tsc = data;
0165     const struct tegra_tsensor *ts = tsc->ts;
0166     int err, c1, c2, c3, c4, counter;
0167     u32 val;
0168
0169     /*
0170      * Counter will be invalid if hardware is misprogrammed or not enough
0171      * time passed since the time when sensor was enabled.
0172      */
0173     err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val,
0174                      val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID,
0175                      21 * USEC_PER_MSEC,
0176                      21 * USEC_PER_MSEC * 50);
0177     if (err) {
0178         dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id);
0179         return err;
0180     }
0181
0182     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1);
0183     counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val);
0184
0185     /*
0186      * This shouldn't happen with a valid counter status, nevertheless
0187      * lets verify the value since it's in a separate (from status)
0188      * register.
0189      */
0190     if (counter == 0xffff) {
0191         dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id);
0192         return -EINVAL;
0193     }
0194
0195     /*
0196      * temperature = a * counter + b
0197      * temperature = m * (temperature ^ 2) + n * temperature + p
0198      */
0199     c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000);
0200     c1 = c1 ?: 1;
0201     c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1);
0202     c3 = c1 * ts->calib.m;
0203     c4 = ts->calib.n;
0204
0205     *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000);
0206
0207     return 0;
0208 }
0209
0210 static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp)
0211 {
0212     int c1, c2;
0213
0214     c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m);
0215     c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1);
0216
0217     return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a);
0218 }
0219
0220 static int tegra_tsensor_set_trips(void *data, int low, int high)
0221 {
0222     const struct tegra_tsensor_channel *tsc = data;
0223     const struct tegra_tsensor *ts = tsc->ts;
0224     u32 val;
0225
0226     /*
0227      * TSENSOR doesn't trigger interrupt on the "low" temperature breach,
0228      * hence bail out if high temperature is unspecified.
0229      */
0230     if (high == INT_MAX)
0231         return 0;
0232
0233     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
0234     val &= ~TSENSOR_SENSOR0_CONFIG1_TH1;
0235
0236     high = tegra_tsensor_temp_to_counter(ts, high);
0237     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high);
0238     writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
0239
0240     return 0;
0241 }
0242
0243 static const struct thermal_zone_of_device_ops ops = {
0244     .get_temp = tegra_tsensor_get_temp,
0245     .set_trips = tegra_tsensor_set_trips,
0246 };
0247
0248 static bool
0249 tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts,
0250                        unsigned int id)
0251 {
0252     const struct tegra_tsensor_channel *tsc = &ts->ch[id];
0253     u32 val;
0254
0255     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0);
0256     writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);
0257
0258     if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5)
0259         dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id);
0260
0261     if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val))
0262         return false;
0263
0264     thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED);
0265
0266     return true;
0267 }
0268
0269 static irqreturn_t tegra_tsensor_isr(int irq, void *data)
0270 {
0271     const struct tegra_tsensor *ts = data;
0272     bool handled = false;
0273     unsigned int i;
0274
0275     for (i = 0; i < ARRAY_SIZE(ts->ch); i++)
0276         handled |= tegra_tsensor_handle_channel_interrupt(ts, i);
0277
0278     return handled ? IRQ_HANDLED : IRQ_NONE;
0279 }
0280
0281 static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts,
0282                         unsigned int id)
0283 {
0284     const struct tegra_tsensor_channel *tsc = &ts->ch[id];
0285     struct thermal_zone_device *tzd = tsc->tzd;
0286     u32 val;
0287     int err;
0288
0289     if (!tzd)
0290         goto stop_channel;
0291
0292     err = thermal_zone_device_disable(tzd);
0293     if (err) {
0294         dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err);
0295         return err;
0296     }
0297
0298 stop_channel:
0299     /* stop channel gracefully */
0300     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
0301     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1);
0302     writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
0303
0304     return 0;
0305 }
0306
0307 static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd,
0308                            int *hot_trip, int *crit_trip)
0309 {
0310     unsigned int i;
0311
0312     /*
0313      * 90C is the maximal critical temperature of all Tegra30 SoC variants,
0314      * use it for the default trip if unspecified in a device-tree.
0315      */
0316     *hot_trip  = 85000;
0317     *crit_trip = 90000;
0318
0319     for (i = 0; i < tzd->num_trips; i++) {
0320         enum thermal_trip_type type;
0321         int trip_temp;
0322
0323         tzd->ops->get_trip_temp(tzd, i, &trip_temp);
0324         tzd->ops->get_trip_type(tzd, i, &type);
0325
0326         if (type == THERMAL_TRIP_HOT)
0327             *hot_trip = trip_temp;
0328
0329         if (type == THERMAL_TRIP_CRITICAL)
0330             *crit_trip = trip_temp;
0331     }
0332
0333     /* clamp hardware trips to the calibration limits */
0334     *hot_trip = clamp(*hot_trip, 25000, 90000);
0335
0336     /*
0337      * Kernel will perform a normal system shut down if it will
0338      * see that critical temperature is breached, hence set the
0339      * hardware limit by 5C higher in order to allow system to
0340      * shut down gracefully before sending signal to the Power
0341      * Management controller.
0342      */
0343     *crit_trip = clamp(*crit_trip + 5000, 25000, 90000);
0344 }
0345
0346 static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts,
0347                        unsigned int id)
0348 {
0349     const struct tegra_tsensor_channel *tsc = &ts->ch[id];
0350     struct thermal_zone_device *tzd = tsc->tzd;
0351     int err, hot_trip = 0, crit_trip = 0;
0352     u32 val;
0353
0354     if (!tzd) {
0355         val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
0356         val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
0357         writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
0358
0359         return 0;
0360     }
0361
0362     tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip);
0363
0364     /* prevent potential racing with tegra_tsensor_set_trips() */
0365     mutex_lock(&tzd->lock);
0366
0367     dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n",
0368               id, DIV_ROUND_CLOSEST(crit_trip, 1000));
0369
0370     hot_trip  = tegra_tsensor_temp_to_counter(ts, hot_trip);
0371     crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip);
0372
0373     /* program LEVEL2 counter threshold */
0374     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
0375     val &= ~TSENSOR_SENSOR0_CONFIG1_TH2;
0376     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip);
0377     writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
0378
0379     /* program LEVEL3 counter threshold */
0380     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2);
0381     val &= ~TSENSOR_SENSOR0_CONFIG2_TH3;
0382     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip);
0383     writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);
0384
0385     /*
0386      * Enable sensor, emergency shutdown, interrupts for level 1/2/3
0387      * breaches and counter overflow condition.
0388      *
0389      * Disable DIV2 throttle for now since we need to figure out how
0390      * to integrate it properly with the thermal framework.
0391      *
0392      * Thermal levels supported by hardware:
0393      *
0394      *     Level 0 = cold
0395      *     Level 1 = passive cooling (cpufreq DVFS)
0396      *     Level 2 = passive cooling assisted by hardware (DIV2)
0397      *     Level 3 = emergency shutdown assisted by hardware (PMC)
0398      */
0399     val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
0400     val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
0401     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1);
0402     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0);
0403     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1);
0404     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1);
0405     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1);
0406     val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1);
0407     writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
0408
0409     mutex_unlock(&tzd->lock);
0410
0411     err = thermal_zone_device_enable(tzd);
0412     if (err) {
0413         dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err);
0414         return err;
0415     }
0416
0417     return 0;
0418 }
0419
0420 static bool tegra_tsensor_fuse_read_spare(unsigned int spare)
0421 {
0422     u32 val = 0;
0423
0424     tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val);
0425
0426     return !!val;
0427 }
0428
0429 static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts)
0430 {
0431     u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0;
0432     int err, c1_25C, c2_90C;
0433
0434     err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver);
0435     if (err) {
0436         dev_err_probe(ts->dev, err, "failed to get ATE version\n");
0437         return err;
0438     }
0439
0440     if (ate_ver < 8) {
0441         dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver);
0442         return -ENODEV;
0443     }
0444
0445     /*
0446      * We have two TSENSOR channels in a two different spots on SoC.
0447      * Second channel provides more accurate data on older SoC versions,
0448      * use it as a primary channel.
0449      */
0450     if (ate_ver <= 21) {
0451         dev_info_once(ts->dev,
0452                   "older ATE version detected, channels remapped\n");
0453         ts->swap_channels = true;
0454     }
0455
0456     err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal);
0457     if (err) {
0458         dev_err(ts->dev, "failed to get calibration data: %d\n", err);
0459         return err;
0460     }
0461
0462     /* get calibrated counter values for 25C/90C thresholds */
0463     c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal);
0464     c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal);
0465
0466     /* and calibrated temperatures corresponding to the counter values */
0467     for (i = 0; i < 7; i++) {
0468         t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i;
0469         t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i;
0470
0471         t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i;
0472         t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i;
0473     }
0474
0475     if (c2_90C - c1_25C <= t2_90C - t1_25C) {
0476         dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n",
0477             c2_90C, c1_25C, t2_90C, t1_25C);
0478         return -EINVAL;
0479     }
0480
0481     /* all calibration coefficients are premultiplied by 1000000 */
0482
0483     ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000,
0484                     (c2_90C - c1_25C));
0485
0486     ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C;
0487
0488     if (tegra_sku_info.revision == TEGRA_REVISION_A01) {
0489         ts->calib.m =     -2775;
0490         ts->calib.n =   1338811;
0491         ts->calib.p =  -7300000;
0492     } else {
0493         ts->calib.m =     -3512;
0494         ts->calib.n =   1528943;
0495         ts->calib.p = -11100000;
0496     }
0497
0498     /* except the coefficient of a reduced quadratic equation */
0499     ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2);
0500
0501     dev_info_once(ts->dev,
0502               "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n",
0503               c2_90C, c1_25C, t2_90C, t1_25C, ate_ver,
0504               tegra_sku_info.revision);
0505
0506     return 0;
0507 }
0508
0509 static int tegra_tsensor_register_channel(struct tegra_tsensor *ts,
0510                       unsigned int id)
0511 {
0512     struct tegra_tsensor_channel *tsc = &ts->ch[id];
0513     unsigned int hw_id = ts->swap_channels ? !id : id;
0514
0515     tsc->ts = ts;
0516     tsc->id = id;
0517     tsc->regs = ts->regs + 0x40 * (hw_id + 1);
0518
0519     tsc->tzd = devm_thermal_zone_of_sensor_register(ts->dev, id, tsc, &ops);
0520     if (IS_ERR(tsc->tzd)) {
0521         if (PTR_ERR(tsc->tzd) != -ENODEV)
0522             return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd),
0523                          "failed to register thermal zone\n");
0524
0525         /*
0526          * It's okay if sensor isn't assigned to any thermal zone
0527          * in a device-tree.
0528          */
0529         tsc->tzd = NULL;
0530         return 0;
0531     }
0532
0533     if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
0534         dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
0535
0536     return 0;
0537 }
0538
0539 static int tegra_tsensor_probe(struct platform_device *pdev)
0540 {
0541     struct tegra_tsensor *ts;
0542     unsigned int i;
0543     int err, irq;
0544
0545     ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL);
0546     if (!ts)
0547         return -ENOMEM;
0548
0549     irq = platform_get_irq(pdev, 0);
0550     if (irq < 0)
0551         return irq;
0552
0553     ts->dev = &pdev->dev;
0554     platform_set_drvdata(pdev, ts);
0555
0556     ts->regs = devm_platform_ioremap_resource(pdev, 0);
0557     if (IS_ERR(ts->regs))
0558         return PTR_ERR(ts->regs);
0559
0560     ts->clk = devm_clk_get(&pdev->dev, NULL);
0561     if (IS_ERR(ts->clk))
0562         return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk),
0563                      "failed to get clock\n");
0564
0565     ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0566     if (IS_ERR(ts->rst))
0567         return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst),
0568                      "failed to get reset control\n");
0569
0570     err = tegra_tsensor_nvmem_setup(ts);
0571     if (err)
0572         return err;
0573
0574     err = tegra_tsensor_hw_enable(ts);
0575     if (err)
0576         return err;
0577
0578     err = devm_add_action_or_reset(&pdev->dev,
0579                        devm_tegra_tsensor_hw_disable,
0580                        ts);
0581     if (err)
0582         return err;
0583
0584     for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
0585         err = tegra_tsensor_register_channel(ts, i);
0586         if (err)
0587             return err;
0588     }
0589
0590     err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0591                     tegra_tsensor_isr, IRQF_ONESHOT,
0592                     "tegra_tsensor", ts);
0593     if (err)
0594         return dev_err_probe(&pdev->dev, err,
0595                      "failed to request interrupt\n");
0596
0597     for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
0598         err = tegra_tsensor_enable_hw_channel(ts, i);
0599         if (err)
0600             return err;
0601     }
0602
0603     return 0;
0604 }
0605
0606 static int __maybe_unused tegra_tsensor_suspend(struct device *dev)
0607 {
0608     struct tegra_tsensor *ts = dev_get_drvdata(dev);
0609     unsigned int i;
0610     int err;
0611
0612     for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
0613         err = tegra_tsensor_disable_hw_channel(ts, i);
0614         if (err)
0615             goto enable_channel;
0616     }
0617
0618     err = tegra_tsensor_hw_disable(ts);
0619     if (err)
0620         goto enable_channel;
0621
0622     return 0;
0623
0624 enable_channel:
0625     while (i--)
0626         tegra_tsensor_enable_hw_channel(ts, i);
0627
0628     return err;
0629 }
0630
0631 static int __maybe_unused tegra_tsensor_resume(struct device *dev)
0632 {
0633     struct tegra_tsensor *ts = dev_get_drvdata(dev);
0634     unsigned int i;
0635     int err;
0636
0637     err = tegra_tsensor_hw_enable(ts);
0638     if (err)
0639         return err;
0640
0641     for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
0642         err = tegra_tsensor_enable_hw_channel(ts, i);
0643         if (err)
0644             return err;
0645     }
0646
0647     return 0;
0648 }
0649
0650 static const struct dev_pm_ops tegra_tsensor_pm_ops = {
0651     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend,
0652                       tegra_tsensor_resume)
0653 };
0654
0655 static const struct of_device_id tegra_tsensor_of_match[] = {
0656     { .compatible = "nvidia,tegra30-tsensor", },
0657     {},
0658 };
0659 MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match);
0660
0661 static struct platform_driver tegra_tsensor_driver = {
0662     .probe = tegra_tsensor_probe,
0663     .driver = {
0664         .name = "tegra30-tsensor",
0665         .of_match_table = tegra_tsensor_of_match,
0666         .pm = &tegra_tsensor_pm_ops,
0667     },
0668 };
0669 module_platform_driver(tegra_tsensor_driver);
0670
0671 MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver");
0672 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
0673 MODULE_LICENSE("GPL");