thermal/tegra/tegra210-soctherm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
0004  *
0005  * This software is licensed under the terms of the GNU General Public
0006  * License version 2, as published by the Free Software Foundation, and
0007  * may be copied, distributed, and modified under those terms.
0008  *
0009  * This program is distributed in the hope that it will be useful,
0010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0012  * GNU General Public License for more details.
0013  *
0014  */
0015
0016 #include <linux/module.h>
0017 #include <linux/platform_device.h>
0018 #include <soc/tegra/fuse.h>
0019
0020 #include <dt-bindings/thermal/tegra124-soctherm.h>
0021
0022 #include "soctherm.h"
0023
0024 #define TEGRA210_THERMTRIP_ANY_EN_MASK      (0x1 << 31)
0025 #define TEGRA210_THERMTRIP_MEM_EN_MASK      (0x1 << 30)
0026 #define TEGRA210_THERMTRIP_GPU_EN_MASK      (0x1 << 29)
0027 #define TEGRA210_THERMTRIP_CPU_EN_MASK      (0x1 << 28)
0028 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK   (0x1 << 27)
0029 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK   (0x1ff << 18)
0030 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK  (0x1ff << 9)
0031 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK   0x1ff
0032
0033 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK   (0x1ff << 18)
0034 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK   (0x1ff << 9)
0035
0036 #define TEGRA210_THRESH_GRAIN           500
0037 #define TEGRA210_BPTT               9
0038
0039 static const struct tegra_tsensor_configuration tegra210_tsensor_config = {
0040     .tall = 16300,
0041     .tiddq_en = 1,
0042     .ten_count = 1,
0043     .tsample = 120,
0044     .tsample_ate = 480,
0045 };
0046
0047 static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = {
0048     .id = TEGRA124_SOCTHERM_SENSOR_CPU,
0049     .name = "cpu",
0050     .sensor_temp_offset = SENSOR_TEMP1,
0051     .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
0052     .pdiv = 8,
0053     .pdiv_ate = 8,
0054     .pdiv_mask = SENSOR_PDIV_CPU_MASK,
0055     .pllx_hotspot_diff = 10,
0056     .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
0057     .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
0058     .thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK,
0059     .thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK,
0060     .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
0061     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
0062     .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
0063     .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
0064 };
0065
0066 static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = {
0067     .id = TEGRA124_SOCTHERM_SENSOR_GPU,
0068     .name = "gpu",
0069     .sensor_temp_offset = SENSOR_TEMP1,
0070     .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
0071     .pdiv = 8,
0072     .pdiv_ate = 8,
0073     .pdiv_mask = SENSOR_PDIV_GPU_MASK,
0074     .pllx_hotspot_diff = 5,
0075     .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
0076     .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
0077     .thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK,
0078     .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
0079     .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
0080     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
0081     .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
0082     .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
0083 };
0084
0085 static const struct tegra_tsensor_group tegra210_tsensor_group_pll = {
0086     .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
0087     .name = "pll",
0088     .sensor_temp_offset = SENSOR_TEMP2,
0089     .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
0090     .pdiv = 8,
0091     .pdiv_ate = 8,
0092     .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
0093     .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
0094     .thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK,
0095     .thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK,
0096     .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
0097     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
0098     .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
0099     .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
0100 };
0101
0102 static const struct tegra_tsensor_group tegra210_tsensor_group_mem = {
0103     .id = TEGRA124_SOCTHERM_SENSOR_MEM,
0104     .name = "mem",
0105     .sensor_temp_offset = SENSOR_TEMP2,
0106     .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
0107     .pdiv = 8,
0108     .pdiv_ate = 8,
0109     .pdiv_mask = SENSOR_PDIV_MEM_MASK,
0110     .pllx_hotspot_diff = 0,
0111     .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
0112     .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
0113     .thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK,
0114     .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
0115     .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
0116     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
0117     .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
0118     .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
0119 };
0120
0121 static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = {
0122     &tegra210_tsensor_group_cpu,
0123     &tegra210_tsensor_group_gpu,
0124     &tegra210_tsensor_group_pll,
0125     &tegra210_tsensor_group_mem,
0126 };
0127
0128 static const struct tegra_tsensor tegra210_tsensors[] = {
0129     {
0130         .name = "cpu0",
0131         .base = 0xc0,
0132         .config = &tegra210_tsensor_config,
0133         .calib_fuse_offset = 0x098,
0134         .fuse_corr_alpha = 1085000,
0135         .fuse_corr_beta = 3244200,
0136         .group = &tegra210_tsensor_group_cpu,
0137     }, {
0138         .name = "cpu1",
0139         .base = 0xe0,
0140         .config = &tegra210_tsensor_config,
0141         .calib_fuse_offset = 0x084,
0142         .fuse_corr_alpha = 1126200,
0143         .fuse_corr_beta = -67500,
0144         .group = &tegra210_tsensor_group_cpu,
0145     }, {
0146         .name = "cpu2",
0147         .base = 0x100,
0148         .config = &tegra210_tsensor_config,
0149         .calib_fuse_offset = 0x088,
0150         .fuse_corr_alpha = 1098400,
0151         .fuse_corr_beta = 2251100,
0152         .group = &tegra210_tsensor_group_cpu,
0153     }, {
0154         .name = "cpu3",
0155         .base = 0x120,
0156         .config = &tegra210_tsensor_config,
0157         .calib_fuse_offset = 0x12c,
0158         .fuse_corr_alpha = 1108000,
0159         .fuse_corr_beta = 602700,
0160         .group = &tegra210_tsensor_group_cpu,
0161     }, {
0162         .name = "mem0",
0163         .base = 0x140,
0164         .config = &tegra210_tsensor_config,
0165         .calib_fuse_offset = 0x158,
0166         .fuse_corr_alpha = 1069200,
0167         .fuse_corr_beta = 3549900,
0168         .group = &tegra210_tsensor_group_mem,
0169     }, {
0170         .name = "mem1",
0171         .base = 0x160,
0172         .config = &tegra210_tsensor_config,
0173         .calib_fuse_offset = 0x15c,
0174         .fuse_corr_alpha = 1173700,
0175         .fuse_corr_beta = -6263600,
0176         .group = &tegra210_tsensor_group_mem,
0177     }, {
0178         .name = "gpu",
0179         .base = 0x180,
0180         .config = &tegra210_tsensor_config,
0181         .calib_fuse_offset = 0x154,
0182         .fuse_corr_alpha = 1074300,
0183         .fuse_corr_beta = 2734900,
0184         .group = &tegra210_tsensor_group_gpu,
0185     }, {
0186         .name = "pllx",
0187         .base = 0x1a0,
0188         .config = &tegra210_tsensor_config,
0189         .calib_fuse_offset = 0x160,
0190         .fuse_corr_alpha = 1039700,
0191         .fuse_corr_beta = 6829100,
0192         .group = &tegra210_tsensor_group_pll,
0193     },
0194 };
0195
0196 /*
0197  * Mask/shift bits in FUSE_TSENSOR_COMMON and
0198  * FUSE_TSENSOR_COMMON, which are described in
0199  * tegra_soctherm_fuse.c
0200  */
0201 static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
0202     .fuse_base_cp_mask = 0x3ff << 11,
0203     .fuse_base_cp_shift = 11,
0204     .fuse_base_ft_mask = 0x7ff << 21,
0205     .fuse_base_ft_shift = 21,
0206     .fuse_shift_ft_mask = 0x1f << 6,
0207     .fuse_shift_ft_shift = 6,
0208     .fuse_spare_realignment = 0,
0209 };
0210
0211 static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
0212     {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
0213     {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
0214     {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
0215     {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
0216 };
0217
0218 const struct tegra_soctherm_soc tegra210_soctherm = {
0219     .tsensors = tegra210_tsensors,
0220     .num_tsensors = ARRAY_SIZE(tegra210_tsensors),
0221     .ttgs = tegra210_tsensor_groups,
0222     .num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups),
0223     .tfuse = &tegra210_soctherm_fuse,
0224     .thresh_grain = TEGRA210_THRESH_GRAIN,
0225     .bptt = TEGRA210_BPTT,
0226     .use_ccroc = false,
0227     .thermtrips = tegra210_tsensor_thermtrips,
0228 };