thermal/tegra/tegra124-soctherm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
0004  *
0005  * This software is licensed under the terms of the GNU General Public
0006  * License version 2, as published by the Free Software Foundation, and
0007  * may be copied, distributed, and modified under those terms.
0008  *
0009  * This program is distributed in the hope that it will be useful,
0010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0012  * GNU General Public License for more details.
0013  *
0014  */
0015
0016 #include <linux/module.h>
0017 #include <linux/platform_device.h>
0018
0019 #include <dt-bindings/thermal/tegra124-soctherm.h>
0020
0021 #include "soctherm.h"
0022
0023 #define TEGRA124_THERMTRIP_ANY_EN_MASK      (0x1 << 28)
0024 #define TEGRA124_THERMTRIP_MEM_EN_MASK      (0x1 << 27)
0025 #define TEGRA124_THERMTRIP_GPU_EN_MASK      (0x1 << 26)
0026 #define TEGRA124_THERMTRIP_CPU_EN_MASK      (0x1 << 25)
0027 #define TEGRA124_THERMTRIP_TSENSE_EN_MASK   (0x1 << 24)
0028 #define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK   (0xff << 16)
0029 #define TEGRA124_THERMTRIP_CPU_THRESH_MASK  (0xff << 8)
0030 #define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK   0xff
0031
0032 #define TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK   (0xff << 17)
0033 #define TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK   (0xff << 9)
0034
0035 #define TEGRA124_THRESH_GRAIN           1000
0036 #define TEGRA124_BPTT               8
0037
0038 static const struct tegra_tsensor_configuration tegra124_tsensor_config = {
0039     .tall = 16300,
0040     .tiddq_en = 1,
0041     .ten_count = 1,
0042     .tsample = 120,
0043     .tsample_ate = 480,
0044 };
0045
0046 static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
0047     .id = TEGRA124_SOCTHERM_SENSOR_CPU,
0048     .name   = "cpu",
0049     .sensor_temp_offset = SENSOR_TEMP1,
0050     .sensor_temp_mask   = SENSOR_TEMP1_CPU_TEMP_MASK,
0051     .pdiv = 8,
0052     .pdiv_ate = 8,
0053     .pdiv_mask = SENSOR_PDIV_CPU_MASK,
0054     .pllx_hotspot_diff = 10,
0055     .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
0056     .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
0057     .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK,
0058     .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK,
0059     .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
0060     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
0061     .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
0062     .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
0063 };
0064
0065 static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
0066     .id = TEGRA124_SOCTHERM_SENSOR_GPU,
0067     .name = "gpu",
0068     .sensor_temp_offset = SENSOR_TEMP1,
0069     .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
0070     .pdiv = 8,
0071     .pdiv_ate = 8,
0072     .pdiv_mask = SENSOR_PDIV_GPU_MASK,
0073     .pllx_hotspot_diff = 5,
0074     .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
0075     .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
0076     .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK,
0077     .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
0078     .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
0079     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
0080     .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
0081     .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
0082 };
0083
0084 static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
0085     .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
0086     .name = "pll",
0087     .sensor_temp_offset = SENSOR_TEMP2,
0088     .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
0089     .pdiv = 8,
0090     .pdiv_ate = 8,
0091     .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
0092     .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
0093     .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK,
0094     .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK,
0095     .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
0096     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
0097     .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
0098     .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
0099 };
0100
0101 static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
0102     .id = TEGRA124_SOCTHERM_SENSOR_MEM,
0103     .name = "mem",
0104     .sensor_temp_offset = SENSOR_TEMP2,
0105     .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
0106     .pdiv = 8,
0107     .pdiv_ate = 8,
0108     .pdiv_mask = SENSOR_PDIV_MEM_MASK,
0109     .pllx_hotspot_diff = 0,
0110     .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
0111     .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
0112     .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK,
0113     .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
0114     .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
0115     .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
0116     .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
0117     .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
0118 };
0119
0120 static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
0121     &tegra124_tsensor_group_cpu,
0122     &tegra124_tsensor_group_gpu,
0123     &tegra124_tsensor_group_pll,
0124     &tegra124_tsensor_group_mem,
0125 };
0126
0127 static const struct tegra_tsensor tegra124_tsensors[] = {
0128     {
0129         .name = "cpu0",
0130         .base = 0xc0,
0131         .config = &tegra124_tsensor_config,
0132         .calib_fuse_offset = 0x098,
0133         .fuse_corr_alpha = 1135400,
0134         .fuse_corr_beta = -6266900,
0135         .group = &tegra124_tsensor_group_cpu,
0136     }, {
0137         .name = "cpu1",
0138         .base = 0xe0,
0139         .config = &tegra124_tsensor_config,
0140         .calib_fuse_offset = 0x084,
0141         .fuse_corr_alpha = 1122220,
0142         .fuse_corr_beta = -5700700,
0143         .group = &tegra124_tsensor_group_cpu,
0144     }, {
0145         .name = "cpu2",
0146         .base = 0x100,
0147         .config = &tegra124_tsensor_config,
0148         .calib_fuse_offset = 0x088,
0149         .fuse_corr_alpha = 1127000,
0150         .fuse_corr_beta = -6768200,
0151         .group = &tegra124_tsensor_group_cpu,
0152     }, {
0153         .name = "cpu3",
0154         .base = 0x120,
0155         .config = &tegra124_tsensor_config,
0156         .calib_fuse_offset = 0x12c,
0157         .fuse_corr_alpha = 1110900,
0158         .fuse_corr_beta = -6232000,
0159         .group = &tegra124_tsensor_group_cpu,
0160     }, {
0161         .name = "mem0",
0162         .base = 0x140,
0163         .config = &tegra124_tsensor_config,
0164         .calib_fuse_offset = 0x158,
0165         .fuse_corr_alpha = 1122300,
0166         .fuse_corr_beta = -5936400,
0167         .group = &tegra124_tsensor_group_mem,
0168     }, {
0169         .name = "mem1",
0170         .base = 0x160,
0171         .config = &tegra124_tsensor_config,
0172         .calib_fuse_offset = 0x15c,
0173         .fuse_corr_alpha = 1145700,
0174         .fuse_corr_beta = -7124600,
0175         .group = &tegra124_tsensor_group_mem,
0176     }, {
0177         .name = "gpu",
0178         .base = 0x180,
0179         .config = &tegra124_tsensor_config,
0180         .calib_fuse_offset = 0x154,
0181         .fuse_corr_alpha = 1120100,
0182         .fuse_corr_beta = -6000500,
0183         .group = &tegra124_tsensor_group_gpu,
0184     }, {
0185         .name = "pllx",
0186         .base = 0x1a0,
0187         .config = &tegra124_tsensor_config,
0188         .calib_fuse_offset = 0x160,
0189         .fuse_corr_alpha = 1106500,
0190         .fuse_corr_beta = -6729300,
0191         .group = &tegra124_tsensor_group_pll,
0192     },
0193 };
0194
0195 /*
0196  * Mask/shift bits in FUSE_TSENSOR_COMMON and
0197  * FUSE_TSENSOR_COMMON, which are described in
0198  * tegra_soctherm_fuse.c
0199  */
0200 static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
0201     .fuse_base_cp_mask = 0x3ff,
0202     .fuse_base_cp_shift = 0,
0203     .fuse_base_ft_mask = 0x7ff << 10,
0204     .fuse_base_ft_shift = 10,
0205     .fuse_shift_ft_mask = 0x1f << 21,
0206     .fuse_shift_ft_shift = 21,
0207     .fuse_spare_realignment = 0x1fc,
0208 };
0209
0210 const struct tegra_soctherm_soc tegra124_soctherm = {
0211     .tsensors = tegra124_tsensors,
0212     .num_tsensors = ARRAY_SIZE(tegra124_tsensors),
0213     .ttgs = tegra124_tsensor_groups,
0214     .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups),
0215     .tfuse = &tegra124_soctherm_fuse,
0216     .thresh_grain = TEGRA124_THRESH_GRAIN,
0217     .bptt = TEGRA124_BPTT,
0218     .use_ccroc = false,
0219 };