thermal/tegra/soctherm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
0004  *
0005  * This software is licensed under the terms of the GNU General Public
0006  * License version 2, as published by the Free Software Foundation, and
0007  * may be copied, distributed, and modified under those terms.
0008  *
0009  * This program is distributed in the hope that it will be useful,
0010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0012  * GNU General Public License for more details.
0013  *
0014  */
0015
0016 #ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
0017 #define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
0018
0019 #define THERMCTL_LEVEL0_GROUP_CPU               0x0
0020 #define THERMCTL_LEVEL0_GROUP_GPU       0x4
0021 #define THERMCTL_LEVEL0_GROUP_MEM       0x8
0022 #define THERMCTL_LEVEL0_GROUP_TSENSE        0xc
0023
0024 #define SENSOR_CONFIG2                          8
0025 #define SENSOR_CONFIG2_THERMA_MASK      (0xffff << 16)
0026 #define SENSOR_CONFIG2_THERMA_SHIFT     16
0027 #define SENSOR_CONFIG2_THERMB_MASK      0xffff
0028 #define SENSOR_CONFIG2_THERMB_SHIFT     0
0029
0030 #define THERMCTL_THERMTRIP_CTL          0x80
0031 /* BITs are defined in device file */
0032
0033 #define THERMCTL_INTR_ENABLE            0x88
0034 #define THERMCTL_INTR_DISABLE           0x8c
0035 #define TH_INTR_UP_DN_EN            0x3
0036 #define THERM_IRQ_MEM_MASK          (TH_INTR_UP_DN_EN << 24)
0037 #define THERM_IRQ_GPU_MASK          (TH_INTR_UP_DN_EN << 16)
0038 #define THERM_IRQ_CPU_MASK          (TH_INTR_UP_DN_EN << 8)
0039 #define THERM_IRQ_TSENSE_MASK           (TH_INTR_UP_DN_EN << 0)
0040
0041 #define SENSOR_PDIV             0x1c0
0042 #define SENSOR_PDIV_CPU_MASK            (0xf << 12)
0043 #define SENSOR_PDIV_GPU_MASK            (0xf << 8)
0044 #define SENSOR_PDIV_MEM_MASK            (0xf << 4)
0045 #define SENSOR_PDIV_PLLX_MASK           (0xf << 0)
0046
0047 #define SENSOR_HOTSPOT_OFF          0x1c4
0048 #define SENSOR_HOTSPOT_CPU_MASK         (0xff << 16)
0049 #define SENSOR_HOTSPOT_GPU_MASK         (0xff << 8)
0050 #define SENSOR_HOTSPOT_MEM_MASK         (0xff << 0)
0051
0052 #define SENSOR_TEMP1                0x1c8
0053 #define SENSOR_TEMP1_CPU_TEMP_MASK      (0xffff << 16)
0054 #define SENSOR_TEMP1_GPU_TEMP_MASK      0xffff
0055 #define SENSOR_TEMP2                0x1cc
0056 #define SENSOR_TEMP2_MEM_TEMP_MASK      (0xffff << 16)
0057 #define SENSOR_TEMP2_PLLX_TEMP_MASK     0xffff
0058
0059 /**
0060  * struct tegra_tsensor_group - SOC_THERM sensor group data
0061  * @name: short name of the temperature sensor group
0062  * @id: numeric ID of the temperature sensor group
0063  * @sensor_temp_offset: offset of the SENSOR_TEMP* register
0064  * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
0065  * @pdiv: the sensor count post-divider to use during runtime
0066  * @pdiv_ate: the sensor count post-divider used during automated test
0067  * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
0068  * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
0069     PLLX sensor group
0070  * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
0071  */
0072 struct tegra_tsensor_group {
0073     const char *name;
0074     u8 id;
0075     u16 sensor_temp_offset;
0076     u32 sensor_temp_mask;
0077     u32 pdiv, pdiv_ate, pdiv_mask;
0078     u32 pllx_hotspot_diff, pllx_hotspot_mask;
0079     u32 thermtrip_enable_mask;
0080     u32 thermtrip_any_en_mask;
0081     u32 thermtrip_threshold_mask;
0082     u32 thermctl_isr_mask;
0083     u16 thermctl_lvl0_offset;
0084     u32 thermctl_lvl0_up_thresh_mask;
0085     u32 thermctl_lvl0_dn_thresh_mask;
0086 };
0087
0088 struct tegra_tsensor_configuration {
0089     u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate;
0090 };
0091
0092 struct tegra_tsensor {
0093     const char *name;
0094     const u32 base;
0095     const struct tegra_tsensor_configuration *config;
0096     const u32 calib_fuse_offset;
0097     /*
0098      * Correction values used to modify values read from
0099      * calibration fuses
0100      */
0101     const s32 fuse_corr_alpha, fuse_corr_beta;
0102     const struct tegra_tsensor_group *group;
0103 };
0104
0105 struct tsensor_group_thermtrips {
0106     u8 id;
0107     u32 temp;
0108 };
0109
0110 struct tegra_soctherm_fuse {
0111     u32 fuse_base_cp_mask, fuse_base_cp_shift;
0112     u32 fuse_base_ft_mask, fuse_base_ft_shift;
0113     u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
0114     u32 fuse_spare_realignment;
0115 };
0116
0117 struct tsensor_shared_calib {
0118     u32 base_cp, base_ft;
0119     u32 actual_temp_cp, actual_temp_ft;
0120 };
0121
0122 struct tegra_soctherm_soc {
0123     const struct tegra_tsensor *tsensors;
0124     const unsigned int num_tsensors;
0125     const struct tegra_tsensor_group **ttgs;
0126     const unsigned int num_ttgs;
0127     const struct tegra_soctherm_fuse *tfuse;
0128     const int thresh_grain;
0129     const unsigned int bptt;
0130     const bool use_ccroc;
0131     struct tsensor_group_thermtrips *thermtrips;
0132 };
0133
0134 int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
0135                 struct tsensor_shared_calib *shared);
0136 int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
0137                  const struct tsensor_shared_calib *shared,
0138                  u32 *calib);
0139
0140 #ifdef CONFIG_ARCH_TEGRA_124_SOC
0141 extern const struct tegra_soctherm_soc tegra124_soctherm;
0142 #endif
0143
0144 #ifdef CONFIG_ARCH_TEGRA_132_SOC
0145 extern const struct tegra_soctherm_soc tegra132_soctherm;
0146 #endif
0147
0148 #ifdef CONFIG_ARCH_TEGRA_210_SOC
0149 extern const struct tegra_soctherm_soc tegra210_soctherm;
0150 #endif
0151
0152 #endif
0153