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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
0004  * Caesar Wang <wxt@rock-chips.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/reset.h>
0018 #include <linux/thermal.h>
0019 #include <linux/mfd/syscon.h>
0020 #include <linux/pinctrl/consumer.h>
0021 
0022 /*
0023  * If the temperature over a period of time High,
0024  * the resulting TSHUT gave CRU module,let it reset the entire chip,
0025  * or via GPIO give PMIC.
0026  */
0027 enum tshut_mode {
0028     TSHUT_MODE_CRU = 0,
0029     TSHUT_MODE_GPIO,
0030 };
0031 
0032 /*
0033  * The system Temperature Sensors tshut(tshut) polarity
0034  * the bit 8 is tshut polarity.
0035  * 0: low active, 1: high active
0036  */
0037 enum tshut_polarity {
0038     TSHUT_LOW_ACTIVE = 0,
0039     TSHUT_HIGH_ACTIVE,
0040 };
0041 
0042 /*
0043  * The system has two Temperature Sensors.
0044  * sensor0 is for CPU, and sensor1 is for GPU.
0045  */
0046 enum sensor_id {
0047     SENSOR_CPU = 0,
0048     SENSOR_GPU,
0049 };
0050 
0051 /*
0052  * The conversion table has the adc value and temperature.
0053  * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
0054  * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
0055  */
0056 enum adc_sort_mode {
0057     ADC_DECREMENT = 0,
0058     ADC_INCREMENT,
0059 };
0060 
0061 #include "thermal_hwmon.h"
0062 
0063 /**
0064  * The max sensors is two in rockchip SoCs.
0065  * Two sensors: CPU and GPU sensor.
0066  */
0067 #define SOC_MAX_SENSORS 2
0068 
0069 /**
0070  * struct chip_tsadc_table - hold information about chip-specific differences
0071  * @id: conversion table
0072  * @length: size of conversion table
0073  * @data_mask: mask to apply on data inputs
0074  * @mode: sort mode of this adc variant (incrementing or decrementing)
0075  */
0076 struct chip_tsadc_table {
0077     const struct tsadc_table *id;
0078     unsigned int length;
0079     u32 data_mask;
0080     enum adc_sort_mode mode;
0081 };
0082 
0083 /**
0084  * struct rockchip_tsadc_chip - hold the private data of tsadc chip
0085  * @chn_id: array of sensor ids of chip corresponding to the channel
0086  * @chn_num: the channel number of tsadc chip
0087  * @tshut_temp: the hardware-controlled shutdown temperature value
0088  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
0089  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
0090  * @initialize: SoC special initialize tsadc controller method
0091  * @irq_ack: clear the interrupt
0092  * @control: enable/disable method for the tsadc controller
0093  * @get_temp: get the temperature
0094  * @set_alarm_temp: set the high temperature interrupt
0095  * @set_tshut_temp: set the hardware-controlled shutdown temperature
0096  * @set_tshut_mode: set the hardware-controlled shutdown mode
0097  * @table: the chip-specific conversion table
0098  */
0099 struct rockchip_tsadc_chip {
0100     /* The sensor id of chip correspond to the ADC channel */
0101     int chn_id[SOC_MAX_SENSORS];
0102     int chn_num;
0103 
0104     /* The hardware-controlled tshut property */
0105     int tshut_temp;
0106     enum tshut_mode tshut_mode;
0107     enum tshut_polarity tshut_polarity;
0108 
0109     /* Chip-wide methods */
0110     void (*initialize)(struct regmap *grf,
0111                void __iomem *reg, enum tshut_polarity p);
0112     void (*irq_ack)(void __iomem *reg);
0113     void (*control)(void __iomem *reg, bool on);
0114 
0115     /* Per-sensor methods */
0116     int (*get_temp)(const struct chip_tsadc_table *table,
0117             int chn, void __iomem *reg, int *temp);
0118     int (*set_alarm_temp)(const struct chip_tsadc_table *table,
0119                   int chn, void __iomem *reg, int temp);
0120     int (*set_tshut_temp)(const struct chip_tsadc_table *table,
0121                   int chn, void __iomem *reg, int temp);
0122     void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
0123 
0124     /* Per-table methods */
0125     struct chip_tsadc_table table;
0126 };
0127 
0128 /**
0129  * struct rockchip_thermal_sensor - hold the information of thermal sensor
0130  * @thermal:  pointer to the platform/configuration data
0131  * @tzd: pointer to a thermal zone
0132  * @id: identifier of the thermal sensor
0133  */
0134 struct rockchip_thermal_sensor {
0135     struct rockchip_thermal_data *thermal;
0136     struct thermal_zone_device *tzd;
0137     int id;
0138 };
0139 
0140 /**
0141  * struct rockchip_thermal_data - hold the private data of thermal driver
0142  * @chip: pointer to the platform/configuration data
0143  * @pdev: platform device of thermal
0144  * @reset: the reset controller of tsadc
0145  * @sensors: array of thermal sensors
0146  * @clk: the controller clock is divided by the exteral 24MHz
0147  * @pclk: the advanced peripherals bus clock
0148  * @grf: the general register file will be used to do static set by software
0149  * @regs: the base address of tsadc controller
0150  * @tshut_temp: the hardware-controlled shutdown temperature value
0151  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
0152  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
0153  */
0154 struct rockchip_thermal_data {
0155     const struct rockchip_tsadc_chip *chip;
0156     struct platform_device *pdev;
0157     struct reset_control *reset;
0158 
0159     struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
0160 
0161     struct clk *clk;
0162     struct clk *pclk;
0163 
0164     struct regmap *grf;
0165     void __iomem *regs;
0166 
0167     int tshut_temp;
0168     enum tshut_mode tshut_mode;
0169     enum tshut_polarity tshut_polarity;
0170 };
0171 
0172 /**
0173  * TSADC Sensor Register description:
0174  *
0175  * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
0176  * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
0177  *
0178  */
0179 #define TSADCV2_USER_CON            0x00
0180 #define TSADCV2_AUTO_CON            0x04
0181 #define TSADCV2_INT_EN              0x08
0182 #define TSADCV2_INT_PD              0x0c
0183 #define TSADCV2_DATA(chn)           (0x20 + (chn) * 0x04)
0184 #define TSADCV2_COMP_INT(chn)               (0x30 + (chn) * 0x04)
0185 #define TSADCV2_COMP_SHUT(chn)              (0x40 + (chn) * 0x04)
0186 #define TSADCV2_HIGHT_INT_DEBOUNCE      0x60
0187 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE        0x64
0188 #define TSADCV2_AUTO_PERIOD         0x68
0189 #define TSADCV2_AUTO_PERIOD_HT          0x6c
0190 
0191 #define TSADCV2_AUTO_EN             BIT(0)
0192 #define TSADCV2_AUTO_SRC_EN(chn)        BIT(4 + (chn))
0193 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH    BIT(8)
0194 
0195 #define TSADCV3_AUTO_Q_SEL_EN           BIT(1)
0196 
0197 #define TSADCV2_INT_SRC_EN(chn)         BIT(chn)
0198 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn)      BIT(4 + (chn))
0199 #define TSADCV2_SHUT_2CRU_SRC_EN(chn)       BIT(8 + (chn))
0200 
0201 #define TSADCV2_INT_PD_CLEAR_MASK       ~BIT(8)
0202 #define TSADCV3_INT_PD_CLEAR_MASK       ~BIT(16)
0203 
0204 #define TSADCV2_DATA_MASK           0xfff
0205 #define TSADCV3_DATA_MASK           0x3ff
0206 
0207 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT    4
0208 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT  4
0209 #define TSADCV2_AUTO_PERIOD_TIME        250 /* 250ms */
0210 #define TSADCV2_AUTO_PERIOD_HT_TIME     50  /* 50ms */
0211 #define TSADCV3_AUTO_PERIOD_TIME        1875 /* 2.5ms */
0212 #define TSADCV3_AUTO_PERIOD_HT_TIME     1875 /* 2.5ms */
0213 
0214 #define TSADCV5_AUTO_PERIOD_TIME        1622 /* 2.5ms */
0215 #define TSADCV5_AUTO_PERIOD_HT_TIME     1622 /* 2.5ms */
0216 
0217 #define TSADCV2_USER_INTER_PD_SOC       0x340 /* 13 clocks */
0218 #define TSADCV5_USER_INTER_PD_SOC       0xfc0 /* 97us, at least 90us */
0219 
0220 #define GRF_SARADC_TESTBIT          0x0e644
0221 #define GRF_TSADC_TESTBIT_L         0x0e648
0222 #define GRF_TSADC_TESTBIT_H         0x0e64c
0223 
0224 #define PX30_GRF_SOC_CON2           0x0408
0225 
0226 #define RK3568_GRF_TSADC_CON            0x0600
0227 #define RK3568_GRF_TSADC_ANA_REG0       (0x10001 << 0)
0228 #define RK3568_GRF_TSADC_ANA_REG1       (0x10001 << 1)
0229 #define RK3568_GRF_TSADC_ANA_REG2       (0x10001 << 2)
0230 #define RK3568_GRF_TSADC_TSEN           (0x10001 << 8)
0231 
0232 #define GRF_SARADC_TESTBIT_ON           (0x10001 << 2)
0233 #define GRF_TSADC_TESTBIT_H_ON          (0x10001 << 2)
0234 #define GRF_TSADC_VCM_EN_L          (0x10001 << 7)
0235 #define GRF_TSADC_VCM_EN_H          (0x10001 << 7)
0236 
0237 #define GRF_CON_TSADC_CH_INV            (0x10001 << 1)
0238 
0239 /**
0240  * struct tsadc_table - code to temperature conversion table
0241  * @code: the value of adc channel
0242  * @temp: the temperature
0243  * Note:
0244  * code to temperature mapping of the temperature sensor is a piece wise linear
0245  * curve.Any temperature, code faling between to 2 give temperatures can be
0246  * linearly interpolated.
0247  * Code to Temperature mapping should be updated based on manufacturer results.
0248  */
0249 struct tsadc_table {
0250     u32 code;
0251     int temp;
0252 };
0253 
0254 static const struct tsadc_table rv1108_table[] = {
0255     {0, -40000},
0256     {374, -40000},
0257     {382, -35000},
0258     {389, -30000},
0259     {397, -25000},
0260     {405, -20000},
0261     {413, -15000},
0262     {421, -10000},
0263     {429, -5000},
0264     {436, 0},
0265     {444, 5000},
0266     {452, 10000},
0267     {460, 15000},
0268     {468, 20000},
0269     {476, 25000},
0270     {483, 30000},
0271     {491, 35000},
0272     {499, 40000},
0273     {507, 45000},
0274     {515, 50000},
0275     {523, 55000},
0276     {531, 60000},
0277     {539, 65000},
0278     {547, 70000},
0279     {555, 75000},
0280     {562, 80000},
0281     {570, 85000},
0282     {578, 90000},
0283     {586, 95000},
0284     {594, 100000},
0285     {602, 105000},
0286     {610, 110000},
0287     {618, 115000},
0288     {626, 120000},
0289     {634, 125000},
0290     {TSADCV2_DATA_MASK, 125000},
0291 };
0292 
0293 static const struct tsadc_table rk3228_code_table[] = {
0294     {0, -40000},
0295     {588, -40000},
0296     {593, -35000},
0297     {598, -30000},
0298     {603, -25000},
0299     {608, -20000},
0300     {613, -15000},
0301     {618, -10000},
0302     {623, -5000},
0303     {629, 0},
0304     {634, 5000},
0305     {639, 10000},
0306     {644, 15000},
0307     {649, 20000},
0308     {654, 25000},
0309     {660, 30000},
0310     {665, 35000},
0311     {670, 40000},
0312     {675, 45000},
0313     {681, 50000},
0314     {686, 55000},
0315     {691, 60000},
0316     {696, 65000},
0317     {702, 70000},
0318     {707, 75000},
0319     {712, 80000},
0320     {717, 85000},
0321     {723, 90000},
0322     {728, 95000},
0323     {733, 100000},
0324     {738, 105000},
0325     {744, 110000},
0326     {749, 115000},
0327     {754, 120000},
0328     {760, 125000},
0329     {TSADCV2_DATA_MASK, 125000},
0330 };
0331 
0332 static const struct tsadc_table rk3288_code_table[] = {
0333     {TSADCV2_DATA_MASK, -40000},
0334     {3800, -40000},
0335     {3792, -35000},
0336     {3783, -30000},
0337     {3774, -25000},
0338     {3765, -20000},
0339     {3756, -15000},
0340     {3747, -10000},
0341     {3737, -5000},
0342     {3728, 0},
0343     {3718, 5000},
0344     {3708, 10000},
0345     {3698, 15000},
0346     {3688, 20000},
0347     {3678, 25000},
0348     {3667, 30000},
0349     {3656, 35000},
0350     {3645, 40000},
0351     {3634, 45000},
0352     {3623, 50000},
0353     {3611, 55000},
0354     {3600, 60000},
0355     {3588, 65000},
0356     {3575, 70000},
0357     {3563, 75000},
0358     {3550, 80000},
0359     {3537, 85000},
0360     {3524, 90000},
0361     {3510, 95000},
0362     {3496, 100000},
0363     {3482, 105000},
0364     {3467, 110000},
0365     {3452, 115000},
0366     {3437, 120000},
0367     {3421, 125000},
0368     {0, 125000},
0369 };
0370 
0371 static const struct tsadc_table rk3328_code_table[] = {
0372     {0, -40000},
0373     {296, -40000},
0374     {304, -35000},
0375     {313, -30000},
0376     {331, -20000},
0377     {340, -15000},
0378     {349, -10000},
0379     {359, -5000},
0380     {368, 0},
0381     {378, 5000},
0382     {388, 10000},
0383     {398, 15000},
0384     {408, 20000},
0385     {418, 25000},
0386     {429, 30000},
0387     {440, 35000},
0388     {451, 40000},
0389     {462, 45000},
0390     {473, 50000},
0391     {485, 55000},
0392     {496, 60000},
0393     {508, 65000},
0394     {521, 70000},
0395     {533, 75000},
0396     {546, 80000},
0397     {559, 85000},
0398     {572, 90000},
0399     {586, 95000},
0400     {600, 100000},
0401     {614, 105000},
0402     {629, 110000},
0403     {644, 115000},
0404     {659, 120000},
0405     {675, 125000},
0406     {TSADCV2_DATA_MASK, 125000},
0407 };
0408 
0409 static const struct tsadc_table rk3368_code_table[] = {
0410     {0, -40000},
0411     {106, -40000},
0412     {108, -35000},
0413     {110, -30000},
0414     {112, -25000},
0415     {114, -20000},
0416     {116, -15000},
0417     {118, -10000},
0418     {120, -5000},
0419     {122, 0},
0420     {124, 5000},
0421     {126, 10000},
0422     {128, 15000},
0423     {130, 20000},
0424     {132, 25000},
0425     {134, 30000},
0426     {136, 35000},
0427     {138, 40000},
0428     {140, 45000},
0429     {142, 50000},
0430     {144, 55000},
0431     {146, 60000},
0432     {148, 65000},
0433     {150, 70000},
0434     {152, 75000},
0435     {154, 80000},
0436     {156, 85000},
0437     {158, 90000},
0438     {160, 95000},
0439     {162, 100000},
0440     {163, 105000},
0441     {165, 110000},
0442     {167, 115000},
0443     {169, 120000},
0444     {171, 125000},
0445     {TSADCV3_DATA_MASK, 125000},
0446 };
0447 
0448 static const struct tsadc_table rk3399_code_table[] = {
0449     {0, -40000},
0450     {402, -40000},
0451     {410, -35000},
0452     {419, -30000},
0453     {427, -25000},
0454     {436, -20000},
0455     {444, -15000},
0456     {453, -10000},
0457     {461, -5000},
0458     {470, 0},
0459     {478, 5000},
0460     {487, 10000},
0461     {496, 15000},
0462     {504, 20000},
0463     {513, 25000},
0464     {521, 30000},
0465     {530, 35000},
0466     {538, 40000},
0467     {547, 45000},
0468     {555, 50000},
0469     {564, 55000},
0470     {573, 60000},
0471     {581, 65000},
0472     {590, 70000},
0473     {599, 75000},
0474     {607, 80000},
0475     {616, 85000},
0476     {624, 90000},
0477     {633, 95000},
0478     {642, 100000},
0479     {650, 105000},
0480     {659, 110000},
0481     {668, 115000},
0482     {677, 120000},
0483     {685, 125000},
0484     {TSADCV3_DATA_MASK, 125000},
0485 };
0486 
0487 static const struct tsadc_table rk3568_code_table[] = {
0488     {0, -40000},
0489     {1584, -40000},
0490     {1620, -35000},
0491     {1652, -30000},
0492     {1688, -25000},
0493     {1720, -20000},
0494     {1756, -15000},
0495     {1788, -10000},
0496     {1824, -5000},
0497     {1856, 0},
0498     {1892, 5000},
0499     {1924, 10000},
0500     {1956, 15000},
0501     {1992, 20000},
0502     {2024, 25000},
0503     {2060, 30000},
0504     {2092, 35000},
0505     {2128, 40000},
0506     {2160, 45000},
0507     {2196, 50000},
0508     {2228, 55000},
0509     {2264, 60000},
0510     {2300, 65000},
0511     {2332, 70000},
0512     {2368, 75000},
0513     {2400, 80000},
0514     {2436, 85000},
0515     {2468, 90000},
0516     {2500, 95000},
0517     {2536, 100000},
0518     {2572, 105000},
0519     {2604, 110000},
0520     {2636, 115000},
0521     {2672, 120000},
0522     {2704, 125000},
0523     {TSADCV2_DATA_MASK, 125000},
0524 };
0525 
0526 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
0527                    int temp)
0528 {
0529     int high, low, mid;
0530     unsigned long num;
0531     unsigned int denom;
0532     u32 error = table->data_mask;
0533 
0534     low = 0;
0535     high = (table->length - 1) - 1; /* ignore the last check for table */
0536     mid = (high + low) / 2;
0537 
0538     /* Return mask code data when the temp is over table range */
0539     if (temp < table->id[low].temp || temp > table->id[high].temp)
0540         goto exit;
0541 
0542     while (low <= high) {
0543         if (temp == table->id[mid].temp)
0544             return table->id[mid].code;
0545         else if (temp < table->id[mid].temp)
0546             high = mid - 1;
0547         else
0548             low = mid + 1;
0549         mid = (low + high) / 2;
0550     }
0551 
0552     /*
0553      * The conversion code granularity provided by the table. Let's
0554      * assume that the relationship between temperature and
0555      * analog value between 2 table entries is linear and interpolate
0556      * to produce less granular result.
0557      */
0558     num = abs(table->id[mid + 1].code - table->id[mid].code);
0559     num *= temp - table->id[mid].temp;
0560     denom = table->id[mid + 1].temp - table->id[mid].temp;
0561 
0562     switch (table->mode) {
0563     case ADC_DECREMENT:
0564         return table->id[mid].code - (num / denom);
0565     case ADC_INCREMENT:
0566         return table->id[mid].code + (num / denom);
0567     default:
0568         pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
0569         return error;
0570     }
0571 
0572 exit:
0573     pr_err("%s: invalid temperature, temp=%d error=%d\n",
0574            __func__, temp, error);
0575     return error;
0576 }
0577 
0578 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
0579                    u32 code, int *temp)
0580 {
0581     unsigned int low = 1;
0582     unsigned int high = table->length - 1;
0583     unsigned int mid = (low + high) / 2;
0584     unsigned int num;
0585     unsigned long denom;
0586 
0587     WARN_ON(table->length < 2);
0588 
0589     switch (table->mode) {
0590     case ADC_DECREMENT:
0591         code &= table->data_mask;
0592         if (code <= table->id[high].code)
0593             return -EAGAIN;     /* Incorrect reading */
0594 
0595         while (low <= high) {
0596             if (code >= table->id[mid].code &&
0597                 code < table->id[mid - 1].code)
0598                 break;
0599             else if (code < table->id[mid].code)
0600                 low = mid + 1;
0601             else
0602                 high = mid - 1;
0603 
0604             mid = (low + high) / 2;
0605         }
0606         break;
0607     case ADC_INCREMENT:
0608         code &= table->data_mask;
0609         if (code < table->id[low].code)
0610             return -EAGAIN;     /* Incorrect reading */
0611 
0612         while (low <= high) {
0613             if (code <= table->id[mid].code &&
0614                 code > table->id[mid - 1].code)
0615                 break;
0616             else if (code > table->id[mid].code)
0617                 low = mid + 1;
0618             else
0619                 high = mid - 1;
0620 
0621             mid = (low + high) / 2;
0622         }
0623         break;
0624     default:
0625         pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
0626         return -EINVAL;
0627     }
0628 
0629     /*
0630      * The 5C granularity provided by the table is too much. Let's
0631      * assume that the relationship between sensor readings and
0632      * temperature between 2 table entries is linear and interpolate
0633      * to produce less granular result.
0634      */
0635     num = table->id[mid].temp - table->id[mid - 1].temp;
0636     num *= abs(table->id[mid - 1].code - code);
0637     denom = abs(table->id[mid - 1].code - table->id[mid].code);
0638     *temp = table->id[mid - 1].temp + (num / denom);
0639 
0640     return 0;
0641 }
0642 
0643 /**
0644  * rk_tsadcv2_initialize - initialize TASDC Controller.
0645  * @grf: the general register file will be used to do static set by software
0646  * @regs: the base address of tsadc controller
0647  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
0648  *
0649  * (1) Set TSADC_V2_AUTO_PERIOD:
0650  *     Configure the interleave between every two accessing of
0651  *     TSADC in normal operation.
0652  *
0653  * (2) Set TSADCV2_AUTO_PERIOD_HT:
0654  *     Configure the interleave between every two accessing of
0655  *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
0656  *
0657  * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
0658  *     If the temperature is higher than COMP_INT or COMP_SHUT for
0659  *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
0660  */
0661 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
0662                   enum tshut_polarity tshut_polarity)
0663 {
0664     if (tshut_polarity == TSHUT_HIGH_ACTIVE)
0665         writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
0666                    regs + TSADCV2_AUTO_CON);
0667     else
0668         writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
0669                    regs + TSADCV2_AUTO_CON);
0670 
0671     writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
0672     writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
0673                regs + TSADCV2_HIGHT_INT_DEBOUNCE);
0674     writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
0675                regs + TSADCV2_AUTO_PERIOD_HT);
0676     writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
0677                regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
0678 }
0679 
0680 /**
0681  * rk_tsadcv3_initialize - initialize TASDC Controller.
0682  * @grf: the general register file will be used to do static set by software
0683  * @regs: the base address of tsadc controller
0684  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
0685  *
0686  * (1) The tsadc control power sequence.
0687  *
0688  * (2) Set TSADC_V2_AUTO_PERIOD:
0689  *     Configure the interleave between every two accessing of
0690  *     TSADC in normal operation.
0691  *
0692  * (2) Set TSADCV2_AUTO_PERIOD_HT:
0693  *     Configure the interleave between every two accessing of
0694  *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
0695  *
0696  * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
0697  *     If the temperature is higher than COMP_INT or COMP_SHUT for
0698  *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
0699  */
0700 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
0701                   enum tshut_polarity tshut_polarity)
0702 {
0703     /* The tsadc control power sequence */
0704     if (IS_ERR(grf)) {
0705         /* Set interleave value to workround ic time sync issue */
0706         writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
0707                    TSADCV2_USER_CON);
0708 
0709         writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
0710                    regs + TSADCV2_AUTO_PERIOD);
0711         writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
0712                    regs + TSADCV2_HIGHT_INT_DEBOUNCE);
0713         writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
0714                    regs + TSADCV2_AUTO_PERIOD_HT);
0715         writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
0716                    regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
0717 
0718     } else {
0719         /* Enable the voltage common mode feature */
0720         regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
0721         regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
0722 
0723         usleep_range(15, 100); /* The spec note says at least 15 us */
0724         regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
0725         regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
0726         usleep_range(90, 200); /* The spec note says at least 90 us */
0727 
0728         writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
0729                    regs + TSADCV2_AUTO_PERIOD);
0730         writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
0731                    regs + TSADCV2_HIGHT_INT_DEBOUNCE);
0732         writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
0733                    regs + TSADCV2_AUTO_PERIOD_HT);
0734         writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
0735                    regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
0736     }
0737 
0738     if (tshut_polarity == TSHUT_HIGH_ACTIVE)
0739         writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
0740                    regs + TSADCV2_AUTO_CON);
0741     else
0742         writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
0743                    regs + TSADCV2_AUTO_CON);
0744 }
0745 
0746 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
0747                   enum tshut_polarity tshut_polarity)
0748 {
0749     rk_tsadcv2_initialize(grf, regs, tshut_polarity);
0750     regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
0751 }
0752 
0753 static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
0754                   enum tshut_polarity tshut_polarity)
0755 {
0756     writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
0757     writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
0758     writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
0759                regs + TSADCV2_HIGHT_INT_DEBOUNCE);
0760     writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
0761                regs + TSADCV2_AUTO_PERIOD_HT);
0762     writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
0763                regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
0764 
0765     if (tshut_polarity == TSHUT_HIGH_ACTIVE)
0766         writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
0767                    regs + TSADCV2_AUTO_CON);
0768     else
0769         writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
0770                    regs + TSADCV2_AUTO_CON);
0771 
0772     /*
0773      * The general register file will is optional
0774      * and might not be available.
0775      */
0776     if (!IS_ERR(grf)) {
0777         regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
0778         /*
0779          * RK3568 TRM, section 18.5. requires a delay no less
0780          * than 10us between the rising edge of tsadc_tsen_en
0781          * and the rising edge of tsadc_ana_reg_0/1/2.
0782          */
0783         udelay(15);
0784         regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
0785         regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
0786         regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
0787 
0788         /*
0789          * RK3568 TRM, section 18.5. requires a delay no less
0790          * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
0791          */
0792         usleep_range(100, 200);
0793     }
0794 }
0795 
0796 static void rk_tsadcv2_irq_ack(void __iomem *regs)
0797 {
0798     u32 val;
0799 
0800     val = readl_relaxed(regs + TSADCV2_INT_PD);
0801     writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
0802 }
0803 
0804 static void rk_tsadcv3_irq_ack(void __iomem *regs)
0805 {
0806     u32 val;
0807 
0808     val = readl_relaxed(regs + TSADCV2_INT_PD);
0809     writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
0810 }
0811 
0812 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
0813 {
0814     u32 val;
0815 
0816     val = readl_relaxed(regs + TSADCV2_AUTO_CON);
0817     if (enable)
0818         val |= TSADCV2_AUTO_EN;
0819     else
0820         val &= ~TSADCV2_AUTO_EN;
0821 
0822     writel_relaxed(val, regs + TSADCV2_AUTO_CON);
0823 }
0824 
0825 /**
0826  * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
0827  * @regs: the base address of tsadc controller
0828  * @enable: boolean flag to enable the controller
0829  *
0830  * NOTE: TSADC controller works at auto mode, and some SoCs need set the
0831  * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
0832  * adc value if setting this bit to enable.
0833  */
0834 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
0835 {
0836     u32 val;
0837 
0838     val = readl_relaxed(regs + TSADCV2_AUTO_CON);
0839     if (enable)
0840         val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
0841     else
0842         val &= ~TSADCV2_AUTO_EN;
0843 
0844     writel_relaxed(val, regs + TSADCV2_AUTO_CON);
0845 }
0846 
0847 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
0848                    int chn, void __iomem *regs, int *temp)
0849 {
0850     u32 val;
0851 
0852     val = readl_relaxed(regs + TSADCV2_DATA(chn));
0853 
0854     return rk_tsadcv2_code_to_temp(table, val, temp);
0855 }
0856 
0857 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
0858                  int chn, void __iomem *regs, int temp)
0859 {
0860     u32 alarm_value;
0861     u32 int_en, int_clr;
0862 
0863     /*
0864      * In some cases, some sensors didn't need the trip points, the
0865      * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
0866      * in the end, ignore this case and disable the high temperature
0867      * interrupt.
0868      */
0869     if (temp == INT_MAX) {
0870         int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
0871         int_clr &= ~TSADCV2_INT_SRC_EN(chn);
0872         writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
0873         return 0;
0874     }
0875 
0876     /* Make sure the value is valid */
0877     alarm_value = rk_tsadcv2_temp_to_code(table, temp);
0878     if (alarm_value == table->data_mask)
0879         return -ERANGE;
0880 
0881     writel_relaxed(alarm_value & table->data_mask,
0882                regs + TSADCV2_COMP_INT(chn));
0883 
0884     int_en = readl_relaxed(regs + TSADCV2_INT_EN);
0885     int_en |= TSADCV2_INT_SRC_EN(chn);
0886     writel_relaxed(int_en, regs + TSADCV2_INT_EN);
0887 
0888     return 0;
0889 }
0890 
0891 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
0892                  int chn, void __iomem *regs, int temp)
0893 {
0894     u32 tshut_value, val;
0895 
0896     /* Make sure the value is valid */
0897     tshut_value = rk_tsadcv2_temp_to_code(table, temp);
0898     if (tshut_value == table->data_mask)
0899         return -ERANGE;
0900 
0901     writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
0902 
0903     /* TSHUT will be valid */
0904     val = readl_relaxed(regs + TSADCV2_AUTO_CON);
0905     writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
0906 
0907     return 0;
0908 }
0909 
0910 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
0911                   enum tshut_mode mode)
0912 {
0913     u32 val;
0914 
0915     val = readl_relaxed(regs + TSADCV2_INT_EN);
0916     if (mode == TSHUT_MODE_GPIO) {
0917         val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
0918         val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
0919     } else {
0920         val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
0921         val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
0922     }
0923 
0924     writel_relaxed(val, regs + TSADCV2_INT_EN);
0925 }
0926 
0927 static const struct rockchip_tsadc_chip px30_tsadc_data = {
0928     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
0929     .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
0930     .chn_num = 2, /* 2 channels for tsadc */
0931 
0932     .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
0933     .tshut_temp = 95000,
0934 
0935     .initialize = rk_tsadcv4_initialize,
0936     .irq_ack = rk_tsadcv3_irq_ack,
0937     .control = rk_tsadcv3_control,
0938     .get_temp = rk_tsadcv2_get_temp,
0939     .set_alarm_temp = rk_tsadcv2_alarm_temp,
0940     .set_tshut_temp = rk_tsadcv2_tshut_temp,
0941     .set_tshut_mode = rk_tsadcv2_tshut_mode,
0942 
0943     .table = {
0944         .id = rk3328_code_table,
0945         .length = ARRAY_SIZE(rk3328_code_table),
0946         .data_mask = TSADCV2_DATA_MASK,
0947         .mode = ADC_INCREMENT,
0948     },
0949 };
0950 
0951 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
0952     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
0953     .chn_num = 1, /* one channel for tsadc */
0954 
0955     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
0956     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
0957     .tshut_temp = 95000,
0958 
0959     .initialize = rk_tsadcv2_initialize,
0960     .irq_ack = rk_tsadcv3_irq_ack,
0961     .control = rk_tsadcv3_control,
0962     .get_temp = rk_tsadcv2_get_temp,
0963     .set_alarm_temp = rk_tsadcv2_alarm_temp,
0964     .set_tshut_temp = rk_tsadcv2_tshut_temp,
0965     .set_tshut_mode = rk_tsadcv2_tshut_mode,
0966 
0967     .table = {
0968         .id = rv1108_table,
0969         .length = ARRAY_SIZE(rv1108_table),
0970         .data_mask = TSADCV2_DATA_MASK,
0971         .mode = ADC_INCREMENT,
0972     },
0973 };
0974 
0975 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
0976     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
0977     .chn_num = 1, /* one channel for tsadc */
0978 
0979     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
0980     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
0981     .tshut_temp = 95000,
0982 
0983     .initialize = rk_tsadcv2_initialize,
0984     .irq_ack = rk_tsadcv3_irq_ack,
0985     .control = rk_tsadcv3_control,
0986     .get_temp = rk_tsadcv2_get_temp,
0987     .set_alarm_temp = rk_tsadcv2_alarm_temp,
0988     .set_tshut_temp = rk_tsadcv2_tshut_temp,
0989     .set_tshut_mode = rk_tsadcv2_tshut_mode,
0990 
0991     .table = {
0992         .id = rk3228_code_table,
0993         .length = ARRAY_SIZE(rk3228_code_table),
0994         .data_mask = TSADCV3_DATA_MASK,
0995         .mode = ADC_INCREMENT,
0996     },
0997 };
0998 
0999 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1000     .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
1001     .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
1002     .chn_num = 2, /* two channels for tsadc */
1003 
1004     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1005     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1006     .tshut_temp = 95000,
1007 
1008     .initialize = rk_tsadcv2_initialize,
1009     .irq_ack = rk_tsadcv2_irq_ack,
1010     .control = rk_tsadcv2_control,
1011     .get_temp = rk_tsadcv2_get_temp,
1012     .set_alarm_temp = rk_tsadcv2_alarm_temp,
1013     .set_tshut_temp = rk_tsadcv2_tshut_temp,
1014     .set_tshut_mode = rk_tsadcv2_tshut_mode,
1015 
1016     .table = {
1017         .id = rk3288_code_table,
1018         .length = ARRAY_SIZE(rk3288_code_table),
1019         .data_mask = TSADCV2_DATA_MASK,
1020         .mode = ADC_DECREMENT,
1021     },
1022 };
1023 
1024 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1025     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1026     .chn_num = 1, /* one channels for tsadc */
1027 
1028     .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1029     .tshut_temp = 95000,
1030 
1031     .initialize = rk_tsadcv2_initialize,
1032     .irq_ack = rk_tsadcv3_irq_ack,
1033     .control = rk_tsadcv3_control,
1034     .get_temp = rk_tsadcv2_get_temp,
1035     .set_alarm_temp = rk_tsadcv2_alarm_temp,
1036     .set_tshut_temp = rk_tsadcv2_tshut_temp,
1037     .set_tshut_mode = rk_tsadcv2_tshut_mode,
1038 
1039     .table = {
1040         .id = rk3328_code_table,
1041         .length = ARRAY_SIZE(rk3328_code_table),
1042         .data_mask = TSADCV2_DATA_MASK,
1043         .mode = ADC_INCREMENT,
1044     },
1045 };
1046 
1047 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1048     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1049     .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1050     .chn_num = 2, /* two channels for tsadc */
1051 
1052     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1053     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1054     .tshut_temp = 95000,
1055 
1056     .initialize = rk_tsadcv3_initialize,
1057     .irq_ack = rk_tsadcv3_irq_ack,
1058     .control = rk_tsadcv3_control,
1059     .get_temp = rk_tsadcv2_get_temp,
1060     .set_alarm_temp = rk_tsadcv2_alarm_temp,
1061     .set_tshut_temp = rk_tsadcv2_tshut_temp,
1062     .set_tshut_mode = rk_tsadcv2_tshut_mode,
1063 
1064     .table = {
1065         .id = rk3228_code_table,
1066         .length = ARRAY_SIZE(rk3228_code_table),
1067         .data_mask = TSADCV3_DATA_MASK,
1068         .mode = ADC_INCREMENT,
1069     },
1070 };
1071 
1072 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1073     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1074     .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1075     .chn_num = 2, /* two channels for tsadc */
1076 
1077     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1078     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1079     .tshut_temp = 95000,
1080 
1081     .initialize = rk_tsadcv2_initialize,
1082     .irq_ack = rk_tsadcv2_irq_ack,
1083     .control = rk_tsadcv2_control,
1084     .get_temp = rk_tsadcv2_get_temp,
1085     .set_alarm_temp = rk_tsadcv2_alarm_temp,
1086     .set_tshut_temp = rk_tsadcv2_tshut_temp,
1087     .set_tshut_mode = rk_tsadcv2_tshut_mode,
1088 
1089     .table = {
1090         .id = rk3368_code_table,
1091         .length = ARRAY_SIZE(rk3368_code_table),
1092         .data_mask = TSADCV3_DATA_MASK,
1093         .mode = ADC_INCREMENT,
1094     },
1095 };
1096 
1097 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1098     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1099     .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1100     .chn_num = 2, /* two channels for tsadc */
1101 
1102     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1103     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1104     .tshut_temp = 95000,
1105 
1106     .initialize = rk_tsadcv3_initialize,
1107     .irq_ack = rk_tsadcv3_irq_ack,
1108     .control = rk_tsadcv3_control,
1109     .get_temp = rk_tsadcv2_get_temp,
1110     .set_alarm_temp = rk_tsadcv2_alarm_temp,
1111     .set_tshut_temp = rk_tsadcv2_tshut_temp,
1112     .set_tshut_mode = rk_tsadcv2_tshut_mode,
1113 
1114     .table = {
1115         .id = rk3399_code_table,
1116         .length = ARRAY_SIZE(rk3399_code_table),
1117         .data_mask = TSADCV3_DATA_MASK,
1118         .mode = ADC_INCREMENT,
1119     },
1120 };
1121 
1122 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1123     .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1124     .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1125     .chn_num = 2, /* two channels for tsadc */
1126 
1127     .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1128     .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1129     .tshut_temp = 95000,
1130 
1131     .initialize = rk_tsadcv7_initialize,
1132     .irq_ack = rk_tsadcv3_irq_ack,
1133     .control = rk_tsadcv3_control,
1134     .get_temp = rk_tsadcv2_get_temp,
1135     .set_alarm_temp = rk_tsadcv2_alarm_temp,
1136     .set_tshut_temp = rk_tsadcv2_tshut_temp,
1137     .set_tshut_mode = rk_tsadcv2_tshut_mode,
1138 
1139     .table = {
1140         .id = rk3568_code_table,
1141         .length = ARRAY_SIZE(rk3568_code_table),
1142         .data_mask = TSADCV2_DATA_MASK,
1143         .mode = ADC_INCREMENT,
1144     },
1145 };
1146 
1147 static const struct of_device_id of_rockchip_thermal_match[] = {
1148     {   .compatible = "rockchip,px30-tsadc",
1149         .data = (void *)&px30_tsadc_data,
1150     },
1151     {
1152         .compatible = "rockchip,rv1108-tsadc",
1153         .data = (void *)&rv1108_tsadc_data,
1154     },
1155     {
1156         .compatible = "rockchip,rk3228-tsadc",
1157         .data = (void *)&rk3228_tsadc_data,
1158     },
1159     {
1160         .compatible = "rockchip,rk3288-tsadc",
1161         .data = (void *)&rk3288_tsadc_data,
1162     },
1163     {
1164         .compatible = "rockchip,rk3328-tsadc",
1165         .data = (void *)&rk3328_tsadc_data,
1166     },
1167     {
1168         .compatible = "rockchip,rk3366-tsadc",
1169         .data = (void *)&rk3366_tsadc_data,
1170     },
1171     {
1172         .compatible = "rockchip,rk3368-tsadc",
1173         .data = (void *)&rk3368_tsadc_data,
1174     },
1175     {
1176         .compatible = "rockchip,rk3399-tsadc",
1177         .data = (void *)&rk3399_tsadc_data,
1178     },
1179     {
1180         .compatible = "rockchip,rk3568-tsadc",
1181         .data = (void *)&rk3568_tsadc_data,
1182     },
1183     { /* end */ },
1184 };
1185 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1186 
1187 static void
1188 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1189 {
1190     struct thermal_zone_device *tzd = sensor->tzd;
1191 
1192     if (on)
1193         thermal_zone_device_enable(tzd);
1194     else
1195         thermal_zone_device_disable(tzd);
1196 }
1197 
1198 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1199 {
1200     struct rockchip_thermal_data *thermal = dev;
1201     int i;
1202 
1203     dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1204 
1205     thermal->chip->irq_ack(thermal->regs);
1206 
1207     for (i = 0; i < thermal->chip->chn_num; i++)
1208         thermal_zone_device_update(thermal->sensors[i].tzd,
1209                        THERMAL_EVENT_UNSPECIFIED);
1210 
1211     return IRQ_HANDLED;
1212 }
1213 
1214 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
1215 {
1216     struct rockchip_thermal_sensor *sensor = _sensor;
1217     struct rockchip_thermal_data *thermal = sensor->thermal;
1218     const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1219 
1220     dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1221         __func__, sensor->id, low, high);
1222 
1223     return tsadc->set_alarm_temp(&tsadc->table,
1224                      sensor->id, thermal->regs, high);
1225 }
1226 
1227 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
1228 {
1229     struct rockchip_thermal_sensor *sensor = _sensor;
1230     struct rockchip_thermal_data *thermal = sensor->thermal;
1231     const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1232     int retval;
1233 
1234     retval = tsadc->get_temp(&tsadc->table,
1235                  sensor->id, thermal->regs, out_temp);
1236     dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
1237         sensor->id, *out_temp, retval);
1238 
1239     return retval;
1240 }
1241 
1242 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1243     .get_temp = rockchip_thermal_get_temp,
1244     .set_trips = rockchip_thermal_set_trips,
1245 };
1246 
1247 static int rockchip_configure_from_dt(struct device *dev,
1248                       struct device_node *np,
1249                       struct rockchip_thermal_data *thermal)
1250 {
1251     u32 shut_temp, tshut_mode, tshut_polarity;
1252 
1253     if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1254         dev_warn(dev,
1255              "Missing tshut temp property, using default %d\n",
1256              thermal->chip->tshut_temp);
1257         thermal->tshut_temp = thermal->chip->tshut_temp;
1258     } else {
1259         if (shut_temp > INT_MAX) {
1260             dev_err(dev, "Invalid tshut temperature specified: %d\n",
1261                 shut_temp);
1262             return -ERANGE;
1263         }
1264         thermal->tshut_temp = shut_temp;
1265     }
1266 
1267     if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1268         dev_warn(dev,
1269              "Missing tshut mode property, using default (%s)\n",
1270              thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1271                 "gpio" : "cru");
1272         thermal->tshut_mode = thermal->chip->tshut_mode;
1273     } else {
1274         thermal->tshut_mode = tshut_mode;
1275     }
1276 
1277     if (thermal->tshut_mode > 1) {
1278         dev_err(dev, "Invalid tshut mode specified: %d\n",
1279             thermal->tshut_mode);
1280         return -EINVAL;
1281     }
1282 
1283     if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1284                  &tshut_polarity)) {
1285         dev_warn(dev,
1286              "Missing tshut-polarity property, using default (%s)\n",
1287              thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1288                 "low" : "high");
1289         thermal->tshut_polarity = thermal->chip->tshut_polarity;
1290     } else {
1291         thermal->tshut_polarity = tshut_polarity;
1292     }
1293 
1294     if (thermal->tshut_polarity > 1) {
1295         dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1296             thermal->tshut_polarity);
1297         return -EINVAL;
1298     }
1299 
1300     /* The tsadc wont to handle the error in here since some SoCs didn't
1301      * need this property.
1302      */
1303     thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1304     if (IS_ERR(thermal->grf))
1305         dev_warn(dev, "Missing rockchip,grf property\n");
1306 
1307     return 0;
1308 }
1309 
1310 static int
1311 rockchip_thermal_register_sensor(struct platform_device *pdev,
1312                  struct rockchip_thermal_data *thermal,
1313                  struct rockchip_thermal_sensor *sensor,
1314                  int id)
1315 {
1316     const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1317     int error;
1318 
1319     tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1320 
1321     error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1322                   thermal->tshut_temp);
1323     if (error)
1324         dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1325             __func__, thermal->tshut_temp, error);
1326 
1327     sensor->thermal = thermal;
1328     sensor->id = id;
1329     sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
1330                     sensor, &rockchip_of_thermal_ops);
1331     if (IS_ERR(sensor->tzd)) {
1332         error = PTR_ERR(sensor->tzd);
1333         dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1334             id, error);
1335         return error;
1336     }
1337 
1338     return 0;
1339 }
1340 
1341 /**
1342  * Reset TSADC Controller, reset all tsadc registers.
1343  * @reset: the reset controller of tsadc
1344  */
1345 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1346 {
1347     reset_control_assert(reset);
1348     usleep_range(10, 20);
1349     reset_control_deassert(reset);
1350 }
1351 
1352 static int rockchip_thermal_probe(struct platform_device *pdev)
1353 {
1354     struct device_node *np = pdev->dev.of_node;
1355     struct rockchip_thermal_data *thermal;
1356     const struct of_device_id *match;
1357     struct resource *res;
1358     int irq;
1359     int i;
1360     int error;
1361 
1362     match = of_match_node(of_rockchip_thermal_match, np);
1363     if (!match)
1364         return -ENXIO;
1365 
1366     irq = platform_get_irq(pdev, 0);
1367     if (irq < 0)
1368         return -EINVAL;
1369 
1370     thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1371                    GFP_KERNEL);
1372     if (!thermal)
1373         return -ENOMEM;
1374 
1375     thermal->pdev = pdev;
1376 
1377     thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1378     if (!thermal->chip)
1379         return -EINVAL;
1380 
1381     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382     thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1383     if (IS_ERR(thermal->regs))
1384         return PTR_ERR(thermal->regs);
1385 
1386     thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
1387     if (IS_ERR(thermal->reset)) {
1388         error = PTR_ERR(thermal->reset);
1389         dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1390         return error;
1391     }
1392 
1393     thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1394     if (IS_ERR(thermal->clk)) {
1395         error = PTR_ERR(thermal->clk);
1396         dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1397         return error;
1398     }
1399 
1400     thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1401     if (IS_ERR(thermal->pclk)) {
1402         error = PTR_ERR(thermal->pclk);
1403         dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1404             error);
1405         return error;
1406     }
1407 
1408     error = clk_prepare_enable(thermal->clk);
1409     if (error) {
1410         dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1411             error);
1412         return error;
1413     }
1414 
1415     error = clk_prepare_enable(thermal->pclk);
1416     if (error) {
1417         dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1418         goto err_disable_clk;
1419     }
1420 
1421     rockchip_thermal_reset_controller(thermal->reset);
1422 
1423     error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1424     if (error) {
1425         dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1426             error);
1427         goto err_disable_pclk;
1428     }
1429 
1430     thermal->chip->initialize(thermal->grf, thermal->regs,
1431                   thermal->tshut_polarity);
1432 
1433     for (i = 0; i < thermal->chip->chn_num; i++) {
1434         error = rockchip_thermal_register_sensor(pdev, thermal,
1435                         &thermal->sensors[i],
1436                         thermal->chip->chn_id[i]);
1437         if (error) {
1438             dev_err(&pdev->dev,
1439                 "failed to register sensor[%d] : error = %d\n",
1440                 i, error);
1441             goto err_disable_pclk;
1442         }
1443     }
1444 
1445     error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1446                       &rockchip_thermal_alarm_irq_thread,
1447                       IRQF_ONESHOT,
1448                       "rockchip_thermal", thermal);
1449     if (error) {
1450         dev_err(&pdev->dev,
1451             "failed to request tsadc irq: %d\n", error);
1452         goto err_disable_pclk;
1453     }
1454 
1455     thermal->chip->control(thermal->regs, true);
1456 
1457     for (i = 0; i < thermal->chip->chn_num; i++) {
1458         rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1459         thermal->sensors[i].tzd->tzp->no_hwmon = false;
1460         error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1461         if (error)
1462             dev_warn(&pdev->dev,
1463                  "failed to register sensor %d with hwmon: %d\n",
1464                  i, error);
1465     }
1466 
1467     platform_set_drvdata(pdev, thermal);
1468 
1469     return 0;
1470 
1471 err_disable_pclk:
1472     clk_disable_unprepare(thermal->pclk);
1473 err_disable_clk:
1474     clk_disable_unprepare(thermal->clk);
1475 
1476     return error;
1477 }
1478 
1479 static int rockchip_thermal_remove(struct platform_device *pdev)
1480 {
1481     struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1482     int i;
1483 
1484     for (i = 0; i < thermal->chip->chn_num; i++) {
1485         struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1486 
1487         thermal_remove_hwmon_sysfs(sensor->tzd);
1488         rockchip_thermal_toggle_sensor(sensor, false);
1489     }
1490 
1491     thermal->chip->control(thermal->regs, false);
1492 
1493     clk_disable_unprepare(thermal->pclk);
1494     clk_disable_unprepare(thermal->clk);
1495 
1496     return 0;
1497 }
1498 
1499 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1500 {
1501     struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1502     int i;
1503 
1504     for (i = 0; i < thermal->chip->chn_num; i++)
1505         rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1506 
1507     thermal->chip->control(thermal->regs, false);
1508 
1509     clk_disable(thermal->pclk);
1510     clk_disable(thermal->clk);
1511 
1512     pinctrl_pm_select_sleep_state(dev);
1513 
1514     return 0;
1515 }
1516 
1517 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1518 {
1519     struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1520     int i;
1521     int error;
1522 
1523     error = clk_enable(thermal->clk);
1524     if (error)
1525         return error;
1526 
1527     error = clk_enable(thermal->pclk);
1528     if (error) {
1529         clk_disable(thermal->clk);
1530         return error;
1531     }
1532 
1533     rockchip_thermal_reset_controller(thermal->reset);
1534 
1535     thermal->chip->initialize(thermal->grf, thermal->regs,
1536                   thermal->tshut_polarity);
1537 
1538     for (i = 0; i < thermal->chip->chn_num; i++) {
1539         int id = thermal->sensors[i].id;
1540 
1541         thermal->chip->set_tshut_mode(id, thermal->regs,
1542                           thermal->tshut_mode);
1543 
1544         error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1545                           id, thermal->regs,
1546                           thermal->tshut_temp);
1547         if (error)
1548             dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1549                 __func__, thermal->tshut_temp, error);
1550     }
1551 
1552     thermal->chip->control(thermal->regs, true);
1553 
1554     for (i = 0; i < thermal->chip->chn_num; i++)
1555         rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1556 
1557     pinctrl_pm_select_default_state(dev);
1558 
1559     return 0;
1560 }
1561 
1562 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1563              rockchip_thermal_suspend, rockchip_thermal_resume);
1564 
1565 static struct platform_driver rockchip_thermal_driver = {
1566     .driver = {
1567         .name = "rockchip-thermal",
1568         .pm = &rockchip_thermal_pm_ops,
1569         .of_match_table = of_rockchip_thermal_match,
1570     },
1571     .probe = rockchip_thermal_probe,
1572     .remove = rockchip_thermal_remove,
1573 };
1574 
1575 module_platform_driver(rockchip_thermal_driver);
1576 
1577 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1578 MODULE_AUTHOR("Rockchip, Inc.");
1579 MODULE_LICENSE("GPL v2");
1580 MODULE_ALIAS("platform:rockchip-thermal");
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