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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #ifndef __QCOM_TSENS_H__
0007 #define __QCOM_TSENS_H__
0008 
0009 #define ONE_PT_CALIB        0x1
0010 #define ONE_PT_CALIB2       0x2
0011 #define TWO_PT_CALIB        0x3
0012 #define CAL_DEGC_PT1        30
0013 #define CAL_DEGC_PT2        120
0014 #define SLOPE_FACTOR        1000
0015 #define SLOPE_DEFAULT       3200
0016 #define TIMEOUT_US      100
0017 #define THRESHOLD_MAX_ADC_CODE  0x3ff
0018 #define THRESHOLD_MIN_ADC_CODE  0x0
0019 
0020 #include <linux/interrupt.h>
0021 #include <linux/thermal.h>
0022 #include <linux/regmap.h>
0023 #include <linux/slab.h>
0024 
0025 struct tsens_priv;
0026 
0027 /* IP version numbers in ascending order */
0028 enum tsens_ver {
0029     VER_0 = 0,
0030     VER_0_1,
0031     VER_1_X,
0032     VER_2_X,
0033 };
0034 
0035 enum tsens_irq_type {
0036     LOWER,
0037     UPPER,
0038     CRITICAL,
0039 };
0040 
0041 /**
0042  * struct tsens_sensor - data for each sensor connected to the tsens device
0043  * @priv: tsens device instance that this sensor is connected to
0044  * @tzd: pointer to the thermal zone that this sensor is in
0045  * @offset: offset of temperature adjustment curve
0046  * @hw_id: HW ID can be used in case of platform-specific IDs
0047  * @slope: slope of temperature adjustment curve
0048  * @status: 8960-specific variable to track 8960 and 8660 status register offset
0049  */
0050 struct tsens_sensor {
0051     struct tsens_priv       *priv;
0052     struct thermal_zone_device  *tzd;
0053     int             offset;
0054     unsigned int            hw_id;
0055     int             slope;
0056     u32             status;
0057 };
0058 
0059 /**
0060  * struct tsens_ops - operations as supported by the tsens device
0061  * @init: Function to initialize the tsens device
0062  * @calibrate: Function to calibrate the tsens device
0063  * @get_temp: Function which returns the temp in millidegC
0064  * @enable: Function to enable (clocks/power) tsens device
0065  * @disable: Function to disable the tsens device
0066  * @suspend: Function to suspend the tsens device
0067  * @resume: Function to resume the tsens device
0068  */
0069 struct tsens_ops {
0070     /* mandatory callbacks */
0071     int (*init)(struct tsens_priv *priv);
0072     int (*calibrate)(struct tsens_priv *priv);
0073     int (*get_temp)(const struct tsens_sensor *s, int *temp);
0074     /* optional callbacks */
0075     int (*enable)(struct tsens_priv *priv, int i);
0076     void (*disable)(struct tsens_priv *priv);
0077     int (*suspend)(struct tsens_priv *priv);
0078     int (*resume)(struct tsens_priv *priv);
0079 };
0080 
0081 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
0082     [_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),  \
0083     [_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
0084     [_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
0085     [_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
0086     [_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
0087     [_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
0088     [_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
0089     [_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
0090     [_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
0091     [_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
0092     [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
0093 
0094 #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
0095     [_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),  \
0096     [_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
0097     [_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
0098     [_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
0099     [_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
0100     [_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
0101     [_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
0102     [_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
0103     [_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
0104     [_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
0105     [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
0106     [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
0107     [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
0108     [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
0109     [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
0110     [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
0111 
0112 #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset)       \
0113     [_name##_##0]  = REG_FIELD(_offset,  0,  0),        \
0114     [_name##_##1]  = REG_FIELD(_offset,  1,  1),    \
0115     [_name##_##2]  = REG_FIELD(_offset,  2,  2),    \
0116     [_name##_##3]  = REG_FIELD(_offset,  3,  3),    \
0117     [_name##_##4]  = REG_FIELD(_offset,  4,  4),    \
0118     [_name##_##5]  = REG_FIELD(_offset,  5,  5),    \
0119     [_name##_##6]  = REG_FIELD(_offset,  6,  6),    \
0120     [_name##_##7]  = REG_FIELD(_offset,  7,  7),    \
0121     [_name##_##8]  = REG_FIELD(_offset,  8,  8),    \
0122     [_name##_##9]  = REG_FIELD(_offset,  9,  9),    \
0123     [_name##_##10] = REG_FIELD(_offset, 10, 10),    \
0124     [_name##_##11] = REG_FIELD(_offset, 11, 11),    \
0125     [_name##_##12] = REG_FIELD(_offset, 12, 12),    \
0126     [_name##_##13] = REG_FIELD(_offset, 13, 13),    \
0127     [_name##_##14] = REG_FIELD(_offset, 14, 14),    \
0128     [_name##_##15] = REG_FIELD(_offset, 15, 15)
0129 
0130 #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset)      \
0131     [_name##_##0]  = REG_FIELD(_offset, 16, 16),        \
0132     [_name##_##1]  = REG_FIELD(_offset, 17, 17),    \
0133     [_name##_##2]  = REG_FIELD(_offset, 18, 18),    \
0134     [_name##_##3]  = REG_FIELD(_offset, 19, 19),    \
0135     [_name##_##4]  = REG_FIELD(_offset, 20, 20),    \
0136     [_name##_##5]  = REG_FIELD(_offset, 21, 21),    \
0137     [_name##_##6]  = REG_FIELD(_offset, 22, 22),    \
0138     [_name##_##7]  = REG_FIELD(_offset, 23, 23),    \
0139     [_name##_##8]  = REG_FIELD(_offset, 24, 24),    \
0140     [_name##_##9]  = REG_FIELD(_offset, 25, 25),    \
0141     [_name##_##10] = REG_FIELD(_offset, 26, 26),    \
0142     [_name##_##11] = REG_FIELD(_offset, 27, 27),    \
0143     [_name##_##12] = REG_FIELD(_offset, 28, 28),    \
0144     [_name##_##13] = REG_FIELD(_offset, 29, 29),    \
0145     [_name##_##14] = REG_FIELD(_offset, 30, 30),    \
0146     [_name##_##15] = REG_FIELD(_offset, 31, 31)
0147 
0148 /*
0149  * reg_field IDs to use as an index into an array
0150  * If you change the order of the entries, check the devm_regmap_field_alloc()
0151  * calls in init_common()
0152  */
0153 enum regfield_ids {
0154     /* ----- SROT ------ */
0155     /* HW_VER */
0156     VER_MAJOR,
0157     VER_MINOR,
0158     VER_STEP,
0159     /* CTRL_OFFSET */
0160     TSENS_EN,
0161     TSENS_SW_RST,
0162     SENSOR_EN,
0163     CODE_OR_TEMP,
0164 
0165     /* ----- TM ------ */
0166     /* TRDY */
0167     TRDY,
0168     /* INTERRUPT ENABLE */
0169     INT_EN, /* v2+ has separate enables for crit, upper and lower irq */
0170     /* STATUS */
0171     LAST_TEMP_0,    /* Last temperature reading */
0172     LAST_TEMP_1,
0173     LAST_TEMP_2,
0174     LAST_TEMP_3,
0175     LAST_TEMP_4,
0176     LAST_TEMP_5,
0177     LAST_TEMP_6,
0178     LAST_TEMP_7,
0179     LAST_TEMP_8,
0180     LAST_TEMP_9,
0181     LAST_TEMP_10,
0182     LAST_TEMP_11,
0183     LAST_TEMP_12,
0184     LAST_TEMP_13,
0185     LAST_TEMP_14,
0186     LAST_TEMP_15,
0187     VALID_0,        /* VALID reading or not */
0188     VALID_1,
0189     VALID_2,
0190     VALID_3,
0191     VALID_4,
0192     VALID_5,
0193     VALID_6,
0194     VALID_7,
0195     VALID_8,
0196     VALID_9,
0197     VALID_10,
0198     VALID_11,
0199     VALID_12,
0200     VALID_13,
0201     VALID_14,
0202     VALID_15,
0203     LOWER_STATUS_0, /* LOWER threshold violated */
0204     LOWER_STATUS_1,
0205     LOWER_STATUS_2,
0206     LOWER_STATUS_3,
0207     LOWER_STATUS_4,
0208     LOWER_STATUS_5,
0209     LOWER_STATUS_6,
0210     LOWER_STATUS_7,
0211     LOWER_STATUS_8,
0212     LOWER_STATUS_9,
0213     LOWER_STATUS_10,
0214     LOWER_STATUS_11,
0215     LOWER_STATUS_12,
0216     LOWER_STATUS_13,
0217     LOWER_STATUS_14,
0218     LOWER_STATUS_15,
0219     LOW_INT_STATUS_0,   /* LOWER interrupt status */
0220     LOW_INT_STATUS_1,
0221     LOW_INT_STATUS_2,
0222     LOW_INT_STATUS_3,
0223     LOW_INT_STATUS_4,
0224     LOW_INT_STATUS_5,
0225     LOW_INT_STATUS_6,
0226     LOW_INT_STATUS_7,
0227     LOW_INT_STATUS_8,
0228     LOW_INT_STATUS_9,
0229     LOW_INT_STATUS_10,
0230     LOW_INT_STATUS_11,
0231     LOW_INT_STATUS_12,
0232     LOW_INT_STATUS_13,
0233     LOW_INT_STATUS_14,
0234     LOW_INT_STATUS_15,
0235     LOW_INT_CLEAR_0,    /* LOWER interrupt clear */
0236     LOW_INT_CLEAR_1,
0237     LOW_INT_CLEAR_2,
0238     LOW_INT_CLEAR_3,
0239     LOW_INT_CLEAR_4,
0240     LOW_INT_CLEAR_5,
0241     LOW_INT_CLEAR_6,
0242     LOW_INT_CLEAR_7,
0243     LOW_INT_CLEAR_8,
0244     LOW_INT_CLEAR_9,
0245     LOW_INT_CLEAR_10,
0246     LOW_INT_CLEAR_11,
0247     LOW_INT_CLEAR_12,
0248     LOW_INT_CLEAR_13,
0249     LOW_INT_CLEAR_14,
0250     LOW_INT_CLEAR_15,
0251     LOW_INT_MASK_0, /* LOWER interrupt mask */
0252     LOW_INT_MASK_1,
0253     LOW_INT_MASK_2,
0254     LOW_INT_MASK_3,
0255     LOW_INT_MASK_4,
0256     LOW_INT_MASK_5,
0257     LOW_INT_MASK_6,
0258     LOW_INT_MASK_7,
0259     LOW_INT_MASK_8,
0260     LOW_INT_MASK_9,
0261     LOW_INT_MASK_10,
0262     LOW_INT_MASK_11,
0263     LOW_INT_MASK_12,
0264     LOW_INT_MASK_13,
0265     LOW_INT_MASK_14,
0266     LOW_INT_MASK_15,
0267     LOW_THRESH_0,       /* LOWER threshold values */
0268     LOW_THRESH_1,
0269     LOW_THRESH_2,
0270     LOW_THRESH_3,
0271     LOW_THRESH_4,
0272     LOW_THRESH_5,
0273     LOW_THRESH_6,
0274     LOW_THRESH_7,
0275     LOW_THRESH_8,
0276     LOW_THRESH_9,
0277     LOW_THRESH_10,
0278     LOW_THRESH_11,
0279     LOW_THRESH_12,
0280     LOW_THRESH_13,
0281     LOW_THRESH_14,
0282     LOW_THRESH_15,
0283     UPPER_STATUS_0, /* UPPER threshold violated */
0284     UPPER_STATUS_1,
0285     UPPER_STATUS_2,
0286     UPPER_STATUS_3,
0287     UPPER_STATUS_4,
0288     UPPER_STATUS_5,
0289     UPPER_STATUS_6,
0290     UPPER_STATUS_7,
0291     UPPER_STATUS_8,
0292     UPPER_STATUS_9,
0293     UPPER_STATUS_10,
0294     UPPER_STATUS_11,
0295     UPPER_STATUS_12,
0296     UPPER_STATUS_13,
0297     UPPER_STATUS_14,
0298     UPPER_STATUS_15,
0299     UP_INT_STATUS_0,    /* UPPER interrupt status */
0300     UP_INT_STATUS_1,
0301     UP_INT_STATUS_2,
0302     UP_INT_STATUS_3,
0303     UP_INT_STATUS_4,
0304     UP_INT_STATUS_5,
0305     UP_INT_STATUS_6,
0306     UP_INT_STATUS_7,
0307     UP_INT_STATUS_8,
0308     UP_INT_STATUS_9,
0309     UP_INT_STATUS_10,
0310     UP_INT_STATUS_11,
0311     UP_INT_STATUS_12,
0312     UP_INT_STATUS_13,
0313     UP_INT_STATUS_14,
0314     UP_INT_STATUS_15,
0315     UP_INT_CLEAR_0, /* UPPER interrupt clear */
0316     UP_INT_CLEAR_1,
0317     UP_INT_CLEAR_2,
0318     UP_INT_CLEAR_3,
0319     UP_INT_CLEAR_4,
0320     UP_INT_CLEAR_5,
0321     UP_INT_CLEAR_6,
0322     UP_INT_CLEAR_7,
0323     UP_INT_CLEAR_8,
0324     UP_INT_CLEAR_9,
0325     UP_INT_CLEAR_10,
0326     UP_INT_CLEAR_11,
0327     UP_INT_CLEAR_12,
0328     UP_INT_CLEAR_13,
0329     UP_INT_CLEAR_14,
0330     UP_INT_CLEAR_15,
0331     UP_INT_MASK_0,      /* UPPER interrupt mask */
0332     UP_INT_MASK_1,
0333     UP_INT_MASK_2,
0334     UP_INT_MASK_3,
0335     UP_INT_MASK_4,
0336     UP_INT_MASK_5,
0337     UP_INT_MASK_6,
0338     UP_INT_MASK_7,
0339     UP_INT_MASK_8,
0340     UP_INT_MASK_9,
0341     UP_INT_MASK_10,
0342     UP_INT_MASK_11,
0343     UP_INT_MASK_12,
0344     UP_INT_MASK_13,
0345     UP_INT_MASK_14,
0346     UP_INT_MASK_15,
0347     UP_THRESH_0,        /* UPPER threshold values */
0348     UP_THRESH_1,
0349     UP_THRESH_2,
0350     UP_THRESH_3,
0351     UP_THRESH_4,
0352     UP_THRESH_5,
0353     UP_THRESH_6,
0354     UP_THRESH_7,
0355     UP_THRESH_8,
0356     UP_THRESH_9,
0357     UP_THRESH_10,
0358     UP_THRESH_11,
0359     UP_THRESH_12,
0360     UP_THRESH_13,
0361     UP_THRESH_14,
0362     UP_THRESH_15,
0363     CRITICAL_STATUS_0,  /* CRITICAL threshold violated */
0364     CRITICAL_STATUS_1,
0365     CRITICAL_STATUS_2,
0366     CRITICAL_STATUS_3,
0367     CRITICAL_STATUS_4,
0368     CRITICAL_STATUS_5,
0369     CRITICAL_STATUS_6,
0370     CRITICAL_STATUS_7,
0371     CRITICAL_STATUS_8,
0372     CRITICAL_STATUS_9,
0373     CRITICAL_STATUS_10,
0374     CRITICAL_STATUS_11,
0375     CRITICAL_STATUS_12,
0376     CRITICAL_STATUS_13,
0377     CRITICAL_STATUS_14,
0378     CRITICAL_STATUS_15,
0379     CRIT_INT_STATUS_0,  /* CRITICAL interrupt status */
0380     CRIT_INT_STATUS_1,
0381     CRIT_INT_STATUS_2,
0382     CRIT_INT_STATUS_3,
0383     CRIT_INT_STATUS_4,
0384     CRIT_INT_STATUS_5,
0385     CRIT_INT_STATUS_6,
0386     CRIT_INT_STATUS_7,
0387     CRIT_INT_STATUS_8,
0388     CRIT_INT_STATUS_9,
0389     CRIT_INT_STATUS_10,
0390     CRIT_INT_STATUS_11,
0391     CRIT_INT_STATUS_12,
0392     CRIT_INT_STATUS_13,
0393     CRIT_INT_STATUS_14,
0394     CRIT_INT_STATUS_15,
0395     CRIT_INT_CLEAR_0,   /* CRITICAL interrupt clear */
0396     CRIT_INT_CLEAR_1,
0397     CRIT_INT_CLEAR_2,
0398     CRIT_INT_CLEAR_3,
0399     CRIT_INT_CLEAR_4,
0400     CRIT_INT_CLEAR_5,
0401     CRIT_INT_CLEAR_6,
0402     CRIT_INT_CLEAR_7,
0403     CRIT_INT_CLEAR_8,
0404     CRIT_INT_CLEAR_9,
0405     CRIT_INT_CLEAR_10,
0406     CRIT_INT_CLEAR_11,
0407     CRIT_INT_CLEAR_12,
0408     CRIT_INT_CLEAR_13,
0409     CRIT_INT_CLEAR_14,
0410     CRIT_INT_CLEAR_15,
0411     CRIT_INT_MASK_0,    /* CRITICAL interrupt mask */
0412     CRIT_INT_MASK_1,
0413     CRIT_INT_MASK_2,
0414     CRIT_INT_MASK_3,
0415     CRIT_INT_MASK_4,
0416     CRIT_INT_MASK_5,
0417     CRIT_INT_MASK_6,
0418     CRIT_INT_MASK_7,
0419     CRIT_INT_MASK_8,
0420     CRIT_INT_MASK_9,
0421     CRIT_INT_MASK_10,
0422     CRIT_INT_MASK_11,
0423     CRIT_INT_MASK_12,
0424     CRIT_INT_MASK_13,
0425     CRIT_INT_MASK_14,
0426     CRIT_INT_MASK_15,
0427     CRIT_THRESH_0,      /* CRITICAL threshold values */
0428     CRIT_THRESH_1,
0429     CRIT_THRESH_2,
0430     CRIT_THRESH_3,
0431     CRIT_THRESH_4,
0432     CRIT_THRESH_5,
0433     CRIT_THRESH_6,
0434     CRIT_THRESH_7,
0435     CRIT_THRESH_8,
0436     CRIT_THRESH_9,
0437     CRIT_THRESH_10,
0438     CRIT_THRESH_11,
0439     CRIT_THRESH_12,
0440     CRIT_THRESH_13,
0441     CRIT_THRESH_14,
0442     CRIT_THRESH_15,
0443 
0444     /* WATCHDOG */
0445     WDOG_BARK_STATUS,
0446     WDOG_BARK_CLEAR,
0447     WDOG_BARK_MASK,
0448     WDOG_BARK_COUNT,
0449 
0450     /* CYCLE COMPLETION MONITOR */
0451     CC_MON_STATUS,
0452     CC_MON_CLEAR,
0453     CC_MON_MASK,
0454 
0455     MIN_STATUS_0,       /* MIN threshold violated */
0456     MIN_STATUS_1,
0457     MIN_STATUS_2,
0458     MIN_STATUS_3,
0459     MIN_STATUS_4,
0460     MIN_STATUS_5,
0461     MIN_STATUS_6,
0462     MIN_STATUS_7,
0463     MIN_STATUS_8,
0464     MIN_STATUS_9,
0465     MIN_STATUS_10,
0466     MIN_STATUS_11,
0467     MIN_STATUS_12,
0468     MIN_STATUS_13,
0469     MIN_STATUS_14,
0470     MIN_STATUS_15,
0471     MAX_STATUS_0,       /* MAX threshold violated */
0472     MAX_STATUS_1,
0473     MAX_STATUS_2,
0474     MAX_STATUS_3,
0475     MAX_STATUS_4,
0476     MAX_STATUS_5,
0477     MAX_STATUS_6,
0478     MAX_STATUS_7,
0479     MAX_STATUS_8,
0480     MAX_STATUS_9,
0481     MAX_STATUS_10,
0482     MAX_STATUS_11,
0483     MAX_STATUS_12,
0484     MAX_STATUS_13,
0485     MAX_STATUS_14,
0486     MAX_STATUS_15,
0487 
0488     /* Keep last */
0489     MAX_REGFIELDS
0490 };
0491 
0492 /**
0493  * struct tsens_features - Features supported by the IP
0494  * @ver_major: Major number of IP version
0495  * @crit_int: does the IP support critical interrupts?
0496  * @adc:      do the sensors only output adc code (instead of temperature)?
0497  * @srot_split: does the IP neatly splits the register space into SROT and TM,
0498  *              with SROT only being available to secure boot firmware?
0499  * @has_watchdog: does this IP support watchdog functionality?
0500  * @max_sensors: maximum sensors supported by this version of the IP
0501  */
0502 struct tsens_features {
0503     unsigned int ver_major;
0504     unsigned int crit_int:1;
0505     unsigned int adc:1;
0506     unsigned int srot_split:1;
0507     unsigned int has_watchdog:1;
0508     unsigned int max_sensors;
0509 };
0510 
0511 /**
0512  * struct tsens_plat_data - tsens compile-time platform data
0513  * @num_sensors: Number of sensors supported by platform
0514  * @ops: operations the tsens instance supports
0515  * @hw_ids: Subset of sensors ids supported by platform, if not the first n
0516  * @feat: features of the IP
0517  * @fields: bitfield locations
0518  */
0519 struct tsens_plat_data {
0520     const u32       num_sensors;
0521     const struct tsens_ops  *ops;
0522     unsigned int        *hw_ids;
0523     struct tsens_features   *feat;
0524     const struct reg_field      *fields;
0525 };
0526 
0527 /**
0528  * struct tsens_context - Registers to be saved/restored across a context loss
0529  * @threshold: Threshold register value
0530  * @control: Control register value
0531  */
0532 struct tsens_context {
0533     int threshold;
0534     int control;
0535 };
0536 
0537 /**
0538  * struct tsens_priv - private data for each instance of the tsens IP
0539  * @dev: pointer to struct device
0540  * @num_sensors: number of sensors enabled on this device
0541  * @tm_map: pointer to TM register address space
0542  * @srot_map: pointer to SROT register address space
0543  * @tm_offset: deal with old device trees that don't address TM and SROT
0544  *             address space separately
0545  * @ul_lock: lock while processing upper/lower threshold interrupts
0546  * @crit_lock: lock while processing critical threshold interrupts
0547  * @rf: array of regmap_fields used to store value of the field
0548  * @ctx: registers to be saved and restored during suspend/resume
0549  * @feat: features of the IP
0550  * @fields: bitfield locations
0551  * @ops: pointer to list of callbacks supported by this device
0552  * @debug_root: pointer to debugfs dentry for all tsens
0553  * @debug: pointer to debugfs dentry for tsens controller
0554  * @sensor: list of sensors attached to this device
0555  */
0556 struct tsens_priv {
0557     struct device           *dev;
0558     u32             num_sensors;
0559     struct regmap           *tm_map;
0560     struct regmap           *srot_map;
0561     u32             tm_offset;
0562 
0563     /* lock for upper/lower threshold interrupts */
0564     spinlock_t          ul_lock;
0565 
0566     struct regmap_field     *rf[MAX_REGFIELDS];
0567     struct tsens_context        ctx;
0568     struct tsens_features       *feat;
0569     const struct reg_field      *fields;
0570     const struct tsens_ops      *ops;
0571 
0572     struct dentry           *debug_root;
0573     struct dentry           *debug;
0574 
0575     struct tsens_sensor     sensor[];
0576 };
0577 
0578 char *qfprom_read(struct device *dev, const char *cname);
0579 void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
0580 int init_common(struct tsens_priv *priv);
0581 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
0582 int get_temp_common(const struct tsens_sensor *s, int *temp);
0583 
0584 /* TSENS target */
0585 extern struct tsens_plat_data data_8960;
0586 
0587 /* TSENS v0.1 targets */
0588 extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607;
0589 
0590 /* TSENS v1 targets */
0591 extern struct tsens_plat_data data_tsens_v1, data_8976;
0592 
0593 /* TSENS v2 targets */
0594 extern struct tsens_plat_data data_8996, data_tsens_v2;
0595 
0596 #endif /* __QCOM_TSENS_H__ */