thermal/qcom/qcom-spmi-temp-alarm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/bitops.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/iio/consumer.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016 #include <linux/thermal.h>
0017
0018 #include "../thermal_core.h"
0019 #include "../thermal_hwmon.h"
0020
0021 #define QPNP_TM_REG_DIG_MAJOR       0x01
0022 #define QPNP_TM_REG_TYPE        0x04
0023 #define QPNP_TM_REG_SUBTYPE     0x05
0024 #define QPNP_TM_REG_STATUS      0x08
0025 #define QPNP_TM_REG_SHUTDOWN_CTRL1  0x40
0026 #define QPNP_TM_REG_ALARM_CTRL      0x46
0027
0028 #define QPNP_TM_TYPE            0x09
0029 #define QPNP_TM_SUBTYPE_GEN1        0x08
0030 #define QPNP_TM_SUBTYPE_GEN2        0x09
0031
0032 #define STATUS_GEN1_STAGE_MASK      GENMASK(1, 0)
0033 #define STATUS_GEN2_STATE_MASK      GENMASK(6, 4)
0034 #define STATUS_GEN2_STATE_SHIFT     4
0035
0036 #define SHUTDOWN_CTRL1_OVERRIDE_S2  BIT(6)
0037 #define SHUTDOWN_CTRL1_THRESHOLD_MASK   GENMASK(1, 0)
0038
0039 #define SHUTDOWN_CTRL1_RATE_25HZ    BIT(3)
0040
0041 #define ALARM_CTRL_FORCE_ENABLE     BIT(7)
0042
0043 #define THRESH_COUNT            4
0044 #define STAGE_COUNT         3
0045
0046 /* Over-temperature trip point values in mC */
0047 static const long temp_map_gen1[THRESH_COUNT][STAGE_COUNT] = {
0048     { 105000, 125000, 145000 },
0049     { 110000, 130000, 150000 },
0050     { 115000, 135000, 155000 },
0051     { 120000, 140000, 160000 },
0052 };
0053
0054 static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = {
0055     {  90000, 110000, 140000 },
0056     {  95000, 115000, 145000 },
0057     { 100000, 120000, 150000 },
0058     { 105000, 125000, 155000 },
0059 };
0060
0061 #define TEMP_THRESH_STEP        5000 /* Threshold step: 5 C */
0062
0063 #define THRESH_MIN          0
0064 #define THRESH_MAX          3
0065
0066 #define TEMP_STAGE_HYSTERESIS       2000
0067
0068 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
0069 #define DEFAULT_TEMP            37000
0070
0071 struct qpnp_tm_chip {
0072     struct regmap           *map;
0073     struct device           *dev;
0074     struct thermal_zone_device  *tz_dev;
0075     unsigned int            subtype;
0076     long                temp;
0077     unsigned int            thresh;
0078     unsigned int            stage;
0079     unsigned int            prev_stage;
0080     unsigned int            base;
0081     /* protects .thresh, .stage and chip registers */
0082     struct mutex            lock;
0083     bool                initialized;
0084
0085     struct iio_channel      *adc;
0086     const long          (*temp_map)[THRESH_COUNT][STAGE_COUNT];
0087 };
0088
0089 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
0090 static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
0091
0092 static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
0093 {
0094     unsigned int val;
0095     int ret;
0096
0097     ret = regmap_read(chip->map, chip->base + addr, &val);
0098     if (ret < 0)
0099         return ret;
0100
0101     *data = val;
0102     return 0;
0103 }
0104
0105 static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
0106 {
0107     return regmap_write(chip->map, chip->base + addr, data);
0108 }
0109
0110 /**
0111  * qpnp_tm_decode_temp() - return temperature in mC corresponding to the
0112  *      specified over-temperature stage
0113  * @chip:       Pointer to the qpnp_tm chip
0114  * @stage:      Over-temperature stage
0115  *
0116  * Return: temperature in mC
0117  */
0118 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage)
0119 {
0120     if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 ||
0121         stage > STAGE_COUNT)
0122         return 0;
0123
0124     return (*chip->temp_map)[chip->thresh][stage - 1];
0125 }
0126
0127 /**
0128  * qpnp_tm_get_temp_stage() - return over-temperature stage
0129  * @chip:       Pointer to the qpnp_tm chip
0130  *
0131  * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
0132  */
0133 static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
0134 {
0135     int ret;
0136     u8 reg = 0;
0137
0138     ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg);
0139     if (ret < 0)
0140         return ret;
0141
0142     if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
0143         ret = reg & STATUS_GEN1_STAGE_MASK;
0144     else
0145         ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
0146
0147     return ret;
0148 }
0149
0150 /*
0151  * This function updates the internal temp value based on the
0152  * current thermal stage and threshold as well as the previous stage
0153  */
0154 static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
0155 {
0156     unsigned int stage, stage_new, stage_old;
0157     int ret;
0158
0159     WARN_ON(!mutex_is_locked(&chip->lock));
0160
0161     ret = qpnp_tm_get_temp_stage(chip);
0162     if (ret < 0)
0163         return ret;
0164     stage = ret;
0165
0166     if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
0167         stage_new = stage;
0168         stage_old = chip->stage;
0169     } else {
0170         stage_new = alarm_state_map[stage];
0171         stage_old = alarm_state_map[chip->stage];
0172     }
0173
0174     if (stage_new > stage_old) {
0175         /* increasing stage, use lower bound */
0176         chip->temp = qpnp_tm_decode_temp(chip, stage_new)
0177                 + TEMP_STAGE_HYSTERESIS;
0178     } else if (stage_new < stage_old) {
0179         /* decreasing stage, use upper bound */
0180         chip->temp = qpnp_tm_decode_temp(chip, stage_new + 1)
0181                 - TEMP_STAGE_HYSTERESIS;
0182     }
0183
0184     chip->stage = stage;
0185
0186     return 0;
0187 }
0188
0189 static int qpnp_tm_get_temp(void *data, int *temp)
0190 {
0191     struct qpnp_tm_chip *chip = data;
0192     int ret, mili_celsius;
0193
0194     if (!temp)
0195         return -EINVAL;
0196
0197     if (!chip->initialized) {
0198         *temp = DEFAULT_TEMP;
0199         return 0;
0200     }
0201
0202     if (!chip->adc) {
0203         mutex_lock(&chip->lock);
0204         ret = qpnp_tm_update_temp_no_adc(chip);
0205         mutex_unlock(&chip->lock);
0206         if (ret < 0)
0207             return ret;
0208     } else {
0209         ret = iio_read_channel_processed(chip->adc, &mili_celsius);
0210         if (ret < 0)
0211             return ret;
0212
0213         chip->temp = mili_celsius;
0214     }
0215
0216     *temp = chip->temp;
0217
0218     return 0;
0219 }
0220
0221 static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
0222                          int temp)
0223 {
0224     long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1];
0225     long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1];
0226     bool disable_s2_shutdown = false;
0227     u8 reg;
0228
0229     WARN_ON(!mutex_is_locked(&chip->lock));
0230
0231     /*
0232      * Default: S2 and S3 shutdown enabled, thresholds at
0233      * lowest threshold set, monitoring at 25Hz
0234      */
0235     reg = SHUTDOWN_CTRL1_RATE_25HZ;
0236
0237     if (temp == THERMAL_TEMP_INVALID ||
0238         temp < stage2_threshold_min) {
0239         chip->thresh = THRESH_MIN;
0240         goto skip;
0241     }
0242
0243     if (temp <= stage2_threshold_max) {
0244         chip->thresh = THRESH_MAX -
0245             ((stage2_threshold_max - temp) /
0246              TEMP_THRESH_STEP);
0247         disable_s2_shutdown = true;
0248     } else {
0249         chip->thresh = THRESH_MAX;
0250
0251         if (chip->adc)
0252             disable_s2_shutdown = true;
0253         else
0254             dev_warn(chip->dev,
0255                  "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n");
0256     }
0257
0258 skip:
0259     reg |= chip->thresh;
0260     if (disable_s2_shutdown)
0261         reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
0262
0263     return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
0264 }
0265
0266 static int qpnp_tm_set_trip_temp(void *data, int trip, int temp)
0267 {
0268     struct qpnp_tm_chip *chip = data;
0269     const struct thermal_trip *trip_points;
0270     int ret;
0271
0272     trip_points = of_thermal_get_trip_points(chip->tz_dev);
0273     if (!trip_points)
0274         return -EINVAL;
0275
0276     if (trip_points[trip].type != THERMAL_TRIP_CRITICAL)
0277         return 0;
0278
0279     mutex_lock(&chip->lock);
0280     ret = qpnp_tm_update_critical_trip_temp(chip, temp);
0281     mutex_unlock(&chip->lock);
0282
0283     return ret;
0284 }
0285
0286 static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = {
0287     .get_temp = qpnp_tm_get_temp,
0288     .set_trip_temp = qpnp_tm_set_trip_temp,
0289 };
0290
0291 static irqreturn_t qpnp_tm_isr(int irq, void *data)
0292 {
0293     struct qpnp_tm_chip *chip = data;
0294
0295     thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
0296
0297     return IRQ_HANDLED;
0298 }
0299
0300 static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip)
0301 {
0302     int ntrips;
0303     const struct thermal_trip *trips;
0304     int i;
0305
0306     ntrips = of_thermal_get_ntrips(chip->tz_dev);
0307     if (ntrips <= 0)
0308         return THERMAL_TEMP_INVALID;
0309
0310     trips = of_thermal_get_trip_points(chip->tz_dev);
0311     if (!trips)
0312         return THERMAL_TEMP_INVALID;
0313
0314     for (i = 0; i < ntrips; i++) {
0315         if (of_thermal_is_trip_valid(chip->tz_dev, i) &&
0316             trips[i].type == THERMAL_TRIP_CRITICAL)
0317             return trips[i].temperature;
0318     }
0319
0320     return THERMAL_TEMP_INVALID;
0321 }
0322
0323 /*
0324  * This function initializes the internal temp value based on only the
0325  * current thermal stage and threshold. Setup threshold control and
0326  * disable shutdown override.
0327  */
0328 static int qpnp_tm_init(struct qpnp_tm_chip *chip)
0329 {
0330     unsigned int stage;
0331     int ret;
0332     u8 reg = 0;
0333     int crit_temp;
0334
0335     mutex_lock(&chip->lock);
0336
0337     ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg);
0338     if (ret < 0)
0339         goto out;
0340
0341     chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
0342     chip->temp = DEFAULT_TEMP;
0343
0344     ret = qpnp_tm_get_temp_stage(chip);
0345     if (ret < 0)
0346         goto out;
0347     chip->stage = ret;
0348
0349     stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
0350         ? chip->stage : alarm_state_map[chip->stage];
0351
0352     if (stage)
0353         chip->temp = qpnp_tm_decode_temp(chip, stage);
0354
0355     crit_temp = qpnp_tm_get_critical_trip_temp(chip);
0356     ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
0357     if (ret < 0)
0358         goto out;
0359
0360     /* Enable the thermal alarm PMIC module in always-on mode. */
0361     reg = ALARM_CTRL_FORCE_ENABLE;
0362     ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
0363
0364     chip->initialized = true;
0365
0366 out:
0367     mutex_unlock(&chip->lock);
0368     return ret;
0369 }
0370
0371 static int qpnp_tm_probe(struct platform_device *pdev)
0372 {
0373     struct qpnp_tm_chip *chip;
0374     struct device_node *node;
0375     u8 type, subtype, dig_major;
0376     u32 res;
0377     int ret, irq;
0378
0379     node = pdev->dev.of_node;
0380
0381     chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
0382     if (!chip)
0383         return -ENOMEM;
0384
0385     dev_set_drvdata(&pdev->dev, chip);
0386     chip->dev = &pdev->dev;
0387
0388     mutex_init(&chip->lock);
0389
0390     chip->map = dev_get_regmap(pdev->dev.parent, NULL);
0391     if (!chip->map)
0392         return -ENXIO;
0393
0394     ret = of_property_read_u32(node, "reg", &res);
0395     if (ret < 0)
0396         return ret;
0397
0398     irq = platform_get_irq(pdev, 0);
0399     if (irq < 0)
0400         return irq;
0401
0402     /* ADC based measurements are optional */
0403     chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
0404     if (IS_ERR(chip->adc)) {
0405         ret = PTR_ERR(chip->adc);
0406         chip->adc = NULL;
0407         if (ret == -EPROBE_DEFER)
0408             return ret;
0409     }
0410
0411     chip->base = res;
0412
0413     ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
0414     if (ret < 0) {
0415         dev_err(&pdev->dev, "could not read type\n");
0416         return ret;
0417     }
0418
0419     ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
0420     if (ret < 0) {
0421         dev_err(&pdev->dev, "could not read subtype\n");
0422         return ret;
0423     }
0424
0425     ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MAJOR, &dig_major);
0426     if (ret < 0) {
0427         dev_err(&pdev->dev, "could not read dig_major\n");
0428         return ret;
0429     }
0430
0431     if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
0432                      && subtype != QPNP_TM_SUBTYPE_GEN2)) {
0433         dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
0434             type, subtype);
0435         return -ENODEV;
0436     }
0437
0438     chip->subtype = subtype;
0439     if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1)
0440         chip->temp_map = &temp_map_gen2_v1;
0441     else
0442         chip->temp_map = &temp_map_gen1;
0443
0444     /*
0445      * Register the sensor before initializing the hardware to be able to
0446      * read the trip points. get_temp() returns the default temperature
0447      * before the hardware initialization is completed.
0448      */
0449     chip->tz_dev = devm_thermal_zone_of_sensor_register(
0450         &pdev->dev, 0, chip, &qpnp_tm_sensor_ops);
0451     if (IS_ERR(chip->tz_dev)) {
0452         dev_err(&pdev->dev, "failed to register sensor\n");
0453         return PTR_ERR(chip->tz_dev);
0454     }
0455
0456     ret = qpnp_tm_init(chip);
0457     if (ret < 0) {
0458         dev_err(&pdev->dev, "init failed\n");
0459         return ret;
0460     }
0461
0462     if (devm_thermal_add_hwmon_sysfs(chip->tz_dev))
0463         dev_warn(&pdev->dev,
0464              "Failed to add hwmon sysfs attributes\n");
0465
0466     ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
0467                     IRQF_ONESHOT, node->name, chip);
0468     if (ret < 0)
0469         return ret;
0470
0471     thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
0472
0473     return 0;
0474 }
0475
0476 static const struct of_device_id qpnp_tm_match_table[] = {
0477     { .compatible = "qcom,spmi-temp-alarm" },
0478     { }
0479 };
0480 MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
0481
0482 static struct platform_driver qpnp_tm_driver = {
0483     .driver = {
0484         .name = "spmi-temp-alarm",
0485         .of_match_table = qpnp_tm_match_table,
0486     },
0487     .probe  = qpnp_tm_probe,
0488 };
0489 module_platform_driver(qpnp_tm_driver);
0490
0491 MODULE_ALIAS("platform:spmi-temp-alarm");
0492 MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
0493 MODULE_LICENSE("GPL v2");