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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2020 Linaro Limited
0004  *
0005  * Based on original driver:
0006  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
0007  *
0008  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/iio/adc/qcom-vadc-common.h>
0013 #include <linux/iio/consumer.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regmap.h>
0020 #include <linux/thermal.h>
0021 #include <asm-generic/unaligned.h>
0022 
0023 #include "../thermal_hwmon.h"
0024 
0025 /*
0026  * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each
0027  * channel is programmed to use one of ADC channels for voltage comparison.
0028  * Voltages are programmed using ADC codes, so we have to convert temp to
0029  * voltage and then to ADC code value.
0030  *
0031  * Configuration of TM channels must match configuration of corresponding ADC
0032  * channels.
0033  */
0034 
0035 #define ADC5_MAX_CHANNEL                        0xc0
0036 #define ADC_TM5_NUM_CHANNELS        8
0037 
0038 #define ADC_TM5_STATUS_LOW          0x0a
0039 
0040 #define ADC_TM5_STATUS_HIGH         0x0b
0041 
0042 #define ADC_TM5_NUM_BTM             0x0f
0043 
0044 #define ADC_TM5_ADC_DIG_PARAM           0x42
0045 
0046 #define ADC_TM5_FAST_AVG_CTL            (ADC_TM5_ADC_DIG_PARAM + 1)
0047 #define ADC_TM5_FAST_AVG_EN             BIT(7)
0048 
0049 #define ADC_TM5_MEAS_INTERVAL_CTL       (ADC_TM5_ADC_DIG_PARAM + 2)
0050 #define ADC_TM5_TIMER1                  3 /* 3.9ms */
0051 
0052 #define ADC_TM5_MEAS_INTERVAL_CTL2      (ADC_TM5_ADC_DIG_PARAM + 3)
0053 #define ADC_TM5_MEAS_INTERVAL_CTL2_MASK         0xf0
0054 #define ADC_TM5_TIMER2                  10 /* 1 second */
0055 #define ADC_TM5_MEAS_INTERVAL_CTL3_MASK         0xf
0056 #define ADC_TM5_TIMER3                  4 /* 4 second */
0057 
0058 #define ADC_TM_EN_CTL1              0x46
0059 #define ADC_TM_EN                   BIT(7)
0060 #define ADC_TM_CONV_REQ             0x47
0061 #define ADC_TM_CONV_REQ_EN              BIT(7)
0062 
0063 #define ADC_TM5_M_CHAN_BASE         0x60
0064 
0065 #define ADC_TM5_M_ADC_CH_SEL_CTL(n)     (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0)
0066 #define ADC_TM5_M_LOW_THR0(n)           (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1)
0067 #define ADC_TM5_M_LOW_THR1(n)           (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2)
0068 #define ADC_TM5_M_HIGH_THR0(n)          (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3)
0069 #define ADC_TM5_M_HIGH_THR1(n)          (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4)
0070 #define ADC_TM5_M_MEAS_INTERVAL_CTL(n)      (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5)
0071 #define ADC_TM5_M_CTL(n)            (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6)
0072 #define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK      0xf
0073 #define ADC_TM5_M_CTL_CAL_SEL_MASK          0x30
0074 #define ADC_TM5_M_CTL_CAL_VAL               0x40
0075 #define ADC_TM5_M_EN(n)             (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7)
0076 #define ADC_TM5_M_MEAS_EN               BIT(7)
0077 #define ADC_TM5_M_HIGH_THR_INT_EN           BIT(1)
0078 #define ADC_TM5_M_LOW_THR_INT_EN            BIT(0)
0079 
0080 #define ADC_TM_GEN2_STATUS1         0x08
0081 #define ADC_TM_GEN2_STATUS_LOW_SET      0x09
0082 #define ADC_TM_GEN2_STATUS_LOW_CLR      0x0a
0083 #define ADC_TM_GEN2_STATUS_HIGH_SET     0x0b
0084 #define ADC_TM_GEN2_STATUS_HIGH_CLR     0x0c
0085 
0086 #define ADC_TM_GEN2_CFG_HS_SET          0x0d
0087 #define ADC_TM_GEN2_CFG_HS_FLAG         BIT(0)
0088 #define ADC_TM_GEN2_CFG_HS_CLR          0x0e
0089 
0090 #define ADC_TM_GEN2_SID             0x40
0091 
0092 #define ADC_TM_GEN2_CH_CTL          0x41
0093 #define ADC_TM_GEN2_TM_CH_SEL           GENMASK(7, 5)
0094 #define ADC_TM_GEN2_MEAS_INT_SEL        GENMASK(3, 2)
0095 
0096 #define ADC_TM_GEN2_ADC_DIG_PARAM       0x42
0097 #define ADC_TM_GEN2_CTL_CAL_SEL         GENMASK(5, 4)
0098 #define ADC_TM_GEN2_CTL_DEC_RATIO_MASK      GENMASK(3, 2)
0099 
0100 #define ADC_TM_GEN2_FAST_AVG_CTL        0x43
0101 #define ADC_TM_GEN2_FAST_AVG_EN         BIT(7)
0102 
0103 #define ADC_TM_GEN2_ADC_CH_SEL_CTL      0x44
0104 
0105 #define ADC_TM_GEN2_DELAY_CTL           0x45
0106 #define ADC_TM_GEN2_HW_SETTLE_DELAY     GENMASK(3, 0)
0107 
0108 #define ADC_TM_GEN2_EN_CTL1         0x46
0109 #define ADC_TM_GEN2_EN              BIT(7)
0110 
0111 #define ADC_TM_GEN2_CONV_REQ            0x47
0112 #define ADC_TM_GEN2_CONV_REQ_EN         BIT(7)
0113 
0114 #define ADC_TM_GEN2_LOW_THR0            0x49
0115 #define ADC_TM_GEN2_LOW_THR1            0x4a
0116 #define ADC_TM_GEN2_HIGH_THR0           0x4b
0117 #define ADC_TM_GEN2_HIGH_THR1           0x4c
0118 #define ADC_TM_GEN2_LOWER_MASK(n)       ((n) & GENMASK(7, 0))
0119 #define ADC_TM_GEN2_UPPER_MASK(n)       (((n) & GENMASK(15, 8)) >> 8)
0120 
0121 #define ADC_TM_GEN2_MEAS_IRQ_EN         0x4d
0122 #define ADC_TM_GEN2_MEAS_EN         BIT(7)
0123 #define ADC_TM5_GEN2_HIGH_THR_INT_EN        BIT(1)
0124 #define ADC_TM5_GEN2_LOW_THR_INT_EN     BIT(0)
0125 
0126 #define ADC_TM_GEN2_MEAS_INT_LSB        0x50
0127 #define ADC_TM_GEN2_MEAS_INT_MSB        0x51
0128 #define ADC_TM_GEN2_MEAS_INT_MODE       0x52
0129 
0130 #define ADC_TM_GEN2_Mn_DATA0(n)         ((n * 2) + 0xa0)
0131 #define ADC_TM_GEN2_Mn_DATA1(n)         ((n * 2) + 0xa1)
0132 #define ADC_TM_GEN2_DATA_SHIFT          8
0133 
0134 enum adc5_timer_select {
0135     ADC5_TIMER_SEL_1 = 0,
0136     ADC5_TIMER_SEL_2,
0137     ADC5_TIMER_SEL_3,
0138     ADC5_TIMER_SEL_NONE,
0139 };
0140 
0141 enum adc5_gen {
0142     ADC_TM5,
0143     ADC_TM_HC,
0144     ADC_TM5_GEN2,
0145     ADC_TM5_MAX
0146 };
0147 
0148 enum adc_tm5_cal_method {
0149     ADC_TM5_NO_CAL = 0,
0150     ADC_TM5_RATIOMETRIC_CAL,
0151     ADC_TM5_ABSOLUTE_CAL
0152 };
0153 
0154 enum adc_tm_gen2_time_select {
0155     MEAS_INT_50MS = 0,
0156     MEAS_INT_100MS,
0157     MEAS_INT_1S,
0158     MEAS_INT_SET,
0159     MEAS_INT_NONE,
0160 };
0161 
0162 struct adc_tm5_chip;
0163 struct adc_tm5_channel;
0164 
0165 struct adc_tm5_data {
0166     const u32 full_scale_code_volt;
0167     unsigned int *decimation;
0168     unsigned int *hw_settle;
0169     int (*disable_channel)(struct adc_tm5_channel *channel);
0170     int (*configure)(struct adc_tm5_channel *channel, int low, int high);
0171     irqreturn_t (*isr)(int irq, void *data);
0172     int (*init)(struct adc_tm5_chip *chip);
0173     char *irq_name;
0174     int gen;
0175 };
0176 
0177 /**
0178  * struct adc_tm5_channel - ADC Thermal Monitoring channel data.
0179  * @channel: channel number.
0180  * @adc_channel: corresponding ADC channel number.
0181  * @cal_method: calibration method.
0182  * @prescale: channel scaling performed on the input signal.
0183  * @hw_settle_time: the time between AMUX being configured and the
0184  *  start of conversion.
0185  * @decimation: sampling rate supported for the channel.
0186  * @avg_samples: ability to provide single result from the ADC
0187  *  that is an average of multiple measurements.
0188  * @high_thr_en: channel upper voltage threshold enable state.
0189  * @low_thr_en: channel lower voltage threshold enable state.
0190  * @meas_en: recurring measurement enable state
0191  * @iio: IIO channel instance used by this channel.
0192  * @chip: ADC TM chip instance.
0193  * @tzd: thermal zone device used by this channel.
0194  */
0195 struct adc_tm5_channel {
0196     unsigned int        channel;
0197     unsigned int        adc_channel;
0198     enum adc_tm5_cal_method cal_method;
0199     unsigned int        prescale;
0200     unsigned int        hw_settle_time;
0201     unsigned int        decimation; /* For Gen2 ADC_TM */
0202     unsigned int        avg_samples;    /* For Gen2 ADC_TM */
0203     bool            high_thr_en;    /* For Gen2 ADC_TM */
0204     bool            low_thr_en; /* For Gen2 ADC_TM */
0205     bool            meas_en;    /* For Gen2 ADC_TM */
0206     struct iio_channel  *iio;
0207     struct adc_tm5_chip *chip;
0208     struct thermal_zone_device *tzd;
0209 };
0210 
0211 /**
0212  * struct adc_tm5_chip - ADC Thermal Monitoring properties
0213  * @regmap: SPMI ADC5 Thermal Monitoring  peripheral register map field.
0214  * @dev: SPMI ADC5 device.
0215  * @data: software configuration data.
0216  * @channels: array of ADC TM channel data.
0217  * @nchannels: amount of channels defined/allocated
0218  * @decimation: sampling rate supported for the channel.
0219  *      Applies to all channels, used only on Gen1 ADC_TM.
0220  * @avg_samples: ability to provide single result from the ADC
0221  *      that is an average of multiple measurements. Applies to all
0222  *      channels, used only on Gen1 ADC_TM.
0223  * @base: base address of TM registers.
0224  * @adc_mutex_lock: ADC_TM mutex lock, used only on Gen2 ADC_TM.
0225  *      It is used to ensure only one ADC channel configuration
0226  *      is done at a time using the shared set of configuration
0227  *      registers.
0228  */
0229 struct adc_tm5_chip {
0230     struct regmap       *regmap;
0231     struct device       *dev;
0232     const struct adc_tm5_data   *data;
0233     struct adc_tm5_channel  *channels;
0234     unsigned int        nchannels;
0235     unsigned int        decimation;
0236     unsigned int        avg_samples;
0237     u16         base;
0238     struct mutex        adc_mutex_lock;
0239 };
0240 
0241 static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
0242 {
0243     return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len);
0244 }
0245 
0246 static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
0247 {
0248     return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len);
0249 }
0250 
0251 static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val)
0252 {
0253     return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val);
0254 }
0255 
0256 static irqreturn_t adc_tm5_isr(int irq, void *data)
0257 {
0258     struct adc_tm5_chip *chip = data;
0259     u8 status_low, status_high, ctl;
0260     int ret, i;
0261 
0262     ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low));
0263     if (unlikely(ret)) {
0264         dev_err(chip->dev, "read status low failed: %d\n", ret);
0265         return IRQ_HANDLED;
0266     }
0267 
0268     ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high));
0269     if (unlikely(ret)) {
0270         dev_err(chip->dev, "read status high failed: %d\n", ret);
0271         return IRQ_HANDLED;
0272     }
0273 
0274     for (i = 0; i < chip->nchannels; i++) {
0275         bool upper_set = false, lower_set = false;
0276         unsigned int ch = chip->channels[i].channel;
0277 
0278         /* No TZD, we warned at the boot time */
0279         if (!chip->channels[i].tzd)
0280             continue;
0281 
0282         ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl));
0283         if (unlikely(ret)) {
0284             dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i);
0285             continue;
0286         }
0287 
0288         if (!(ctl & ADC_TM5_M_MEAS_EN))
0289             continue;
0290 
0291         lower_set = (status_low & BIT(ch)) &&
0292             (ctl & ADC_TM5_M_LOW_THR_INT_EN);
0293 
0294         upper_set = (status_high & BIT(ch)) &&
0295             (ctl & ADC_TM5_M_HIGH_THR_INT_EN);
0296 
0297         if (upper_set || lower_set)
0298             thermal_zone_device_update(chip->channels[i].tzd,
0299                            THERMAL_EVENT_UNSPECIFIED);
0300     }
0301 
0302     return IRQ_HANDLED;
0303 }
0304 
0305 static irqreturn_t adc_tm5_gen2_isr(int irq, void *data)
0306 {
0307     struct adc_tm5_chip *chip = data;
0308     u8 status_low, status_high;
0309     int ret, i;
0310 
0311     ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low));
0312     if (ret) {
0313         dev_err(chip->dev, "read status_low failed: %d\n", ret);
0314         return IRQ_HANDLED;
0315     }
0316 
0317     ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high));
0318     if (ret) {
0319         dev_err(chip->dev, "read status_high failed: %d\n", ret);
0320         return IRQ_HANDLED;
0321     }
0322 
0323     ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low));
0324     if (ret < 0) {
0325         dev_err(chip->dev, "clear status low failed with %d\n", ret);
0326         return IRQ_HANDLED;
0327     }
0328 
0329     ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high));
0330     if (ret < 0) {
0331         dev_err(chip->dev, "clear status high failed with %d\n", ret);
0332         return IRQ_HANDLED;
0333     }
0334 
0335     for (i = 0; i < chip->nchannels; i++) {
0336         bool upper_set = false, lower_set = false;
0337         unsigned int ch = chip->channels[i].channel;
0338 
0339         /* No TZD, we warned at the boot time */
0340         if (!chip->channels[i].tzd)
0341             continue;
0342 
0343         if (!chip->channels[i].meas_en)
0344             continue;
0345 
0346         lower_set = (status_low & BIT(ch)) &&
0347             (chip->channels[i].low_thr_en);
0348 
0349         upper_set = (status_high & BIT(ch)) &&
0350             (chip->channels[i].high_thr_en);
0351 
0352         if (upper_set || lower_set)
0353             thermal_zone_device_update(chip->channels[i].tzd,
0354                            THERMAL_EVENT_UNSPECIFIED);
0355     }
0356 
0357     return IRQ_HANDLED;
0358 }
0359 
0360 static int adc_tm5_get_temp(void *data, int *temp)
0361 {
0362     struct adc_tm5_channel *channel = data;
0363     int ret;
0364 
0365     if (!channel || !channel->iio)
0366         return -EINVAL;
0367 
0368     ret = iio_read_channel_processed(channel->iio, temp);
0369     if (ret < 0)
0370         return ret;
0371 
0372     if (ret != IIO_VAL_INT)
0373         return -EINVAL;
0374 
0375     return 0;
0376 }
0377 
0378 static int adc_tm5_disable_channel(struct adc_tm5_channel *channel)
0379 {
0380     struct adc_tm5_chip *chip = channel->chip;
0381     unsigned int reg = ADC_TM5_M_EN(channel->channel);
0382 
0383     return adc_tm5_reg_update(chip, reg,
0384                   ADC_TM5_M_MEAS_EN |
0385                   ADC_TM5_M_HIGH_THR_INT_EN |
0386                   ADC_TM5_M_LOW_THR_INT_EN,
0387                   0);
0388 }
0389 
0390 #define ADC_TM_GEN2_POLL_DELAY_MIN_US       100
0391 #define ADC_TM_GEN2_POLL_DELAY_MAX_US       110
0392 #define ADC_TM_GEN2_POLL_RETRY_COUNT        3
0393 
0394 static int32_t adc_tm5_gen2_conv_req(struct adc_tm5_chip *chip)
0395 {
0396     int ret;
0397     u8 data;
0398     unsigned int count;
0399 
0400     data = ADC_TM_GEN2_EN;
0401     ret = adc_tm5_write(chip, ADC_TM_GEN2_EN_CTL1, &data, 1);
0402     if (ret < 0) {
0403         dev_err(chip->dev, "adc-tm enable failed with %d\n", ret);
0404         return ret;
0405     }
0406 
0407     data = ADC_TM_GEN2_CFG_HS_FLAG;
0408     ret = adc_tm5_write(chip, ADC_TM_GEN2_CFG_HS_SET, &data, 1);
0409     if (ret < 0) {
0410         dev_err(chip->dev, "adc-tm handshake failed with %d\n", ret);
0411         return ret;
0412     }
0413 
0414     data = ADC_TM_GEN2_CONV_REQ_EN;
0415     ret = adc_tm5_write(chip, ADC_TM_GEN2_CONV_REQ, &data, 1);
0416     if (ret < 0) {
0417         dev_err(chip->dev, "adc-tm request conversion failed with %d\n", ret);
0418         return ret;
0419     }
0420 
0421     /*
0422      * SW sets a handshake bit and waits for PBS to clear it
0423      * before the next conversion request can be queued.
0424      */
0425 
0426     for (count = 0; count < ADC_TM_GEN2_POLL_RETRY_COUNT; count++) {
0427         ret = adc_tm5_read(chip, ADC_TM_GEN2_CFG_HS_SET, &data, sizeof(data));
0428         if (ret < 0) {
0429             dev_err(chip->dev, "adc-tm read failed with %d\n", ret);
0430             return ret;
0431         }
0432 
0433         if (!(data & ADC_TM_GEN2_CFG_HS_FLAG))
0434             return ret;
0435         usleep_range(ADC_TM_GEN2_POLL_DELAY_MIN_US,
0436             ADC_TM_GEN2_POLL_DELAY_MAX_US);
0437     }
0438 
0439     dev_err(chip->dev, "adc-tm conversion request handshake timed out\n");
0440 
0441     return -ETIMEDOUT;
0442 }
0443 
0444 static int adc_tm5_gen2_disable_channel(struct adc_tm5_channel *channel)
0445 {
0446     struct adc_tm5_chip *chip = channel->chip;
0447     int ret;
0448     u8 val;
0449 
0450     mutex_lock(&chip->adc_mutex_lock);
0451 
0452     channel->meas_en = false;
0453     channel->high_thr_en = false;
0454     channel->low_thr_en = false;
0455 
0456     ret = adc_tm5_read(chip, ADC_TM_GEN2_CH_CTL, &val, sizeof(val));
0457     if (ret < 0) {
0458         dev_err(chip->dev, "adc-tm block read failed with %d\n", ret);
0459         goto disable_fail;
0460     }
0461 
0462     val &= ~ADC_TM_GEN2_TM_CH_SEL;
0463     val |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel);
0464 
0465     ret = adc_tm5_write(chip, ADC_TM_GEN2_CH_CTL, &val, 1);
0466     if (ret < 0) {
0467         dev_err(chip->dev, "adc-tm channel disable failed with %d\n", ret);
0468         goto disable_fail;
0469     }
0470 
0471     val = 0;
0472     ret = adc_tm5_write(chip, ADC_TM_GEN2_MEAS_IRQ_EN, &val, 1);
0473     if (ret < 0) {
0474         dev_err(chip->dev, "adc-tm interrupt disable failed with %d\n", ret);
0475         goto disable_fail;
0476     }
0477 
0478 
0479     ret = adc_tm5_gen2_conv_req(channel->chip);
0480     if (ret < 0)
0481         dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret);
0482 
0483 disable_fail:
0484     mutex_unlock(&chip->adc_mutex_lock);
0485     return ret;
0486 }
0487 
0488 static int adc_tm5_enable(struct adc_tm5_chip *chip)
0489 {
0490     int ret;
0491     u8 data;
0492 
0493     data = ADC_TM_EN;
0494     ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data));
0495     if (ret < 0) {
0496         dev_err(chip->dev, "adc-tm enable failed\n");
0497         return ret;
0498     }
0499 
0500     data = ADC_TM_CONV_REQ_EN;
0501     ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data));
0502     if (ret < 0) {
0503         dev_err(chip->dev, "adc-tm request conversion failed\n");
0504         return ret;
0505     }
0506 
0507     return 0;
0508 }
0509 
0510 static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high)
0511 {
0512     struct adc_tm5_chip *chip = channel->chip;
0513     u8 buf[8];
0514     u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel);
0515     int ret;
0516 
0517     ret = adc_tm5_read(chip, reg, buf, sizeof(buf));
0518     if (ret) {
0519         dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret);
0520         return ret;
0521     }
0522 
0523     buf[0] = channel->adc_channel;
0524 
0525     /* High temperature corresponds to low voltage threshold */
0526     if (high != INT_MAX) {
0527         u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
0528                 chip->data->full_scale_code_volt, high);
0529 
0530         put_unaligned_le16(adc_code, &buf[1]);
0531         buf[7] |= ADC_TM5_M_LOW_THR_INT_EN;
0532     } else {
0533         buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN;
0534     }
0535 
0536     /* Low temperature corresponds to high voltage threshold */
0537     if (low != -INT_MAX) {
0538         u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
0539                 chip->data->full_scale_code_volt, low);
0540 
0541         put_unaligned_le16(adc_code, &buf[3]);
0542         buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN;
0543     } else {
0544         buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN;
0545     }
0546 
0547     buf[5] = ADC5_TIMER_SEL_2;
0548 
0549     /* Set calibration select, hw_settle delay */
0550     buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK;
0551     buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time);
0552     buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK;
0553     buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method);
0554 
0555     buf[7] |= ADC_TM5_M_MEAS_EN;
0556 
0557     ret = adc_tm5_write(chip, reg, buf, sizeof(buf));
0558     if (ret) {
0559         dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
0560         return ret;
0561     }
0562 
0563     return adc_tm5_enable(chip);
0564 }
0565 
0566 static int adc_tm5_gen2_configure(struct adc_tm5_channel *channel, int low, int high)
0567 {
0568     struct adc_tm5_chip *chip = channel->chip;
0569     int ret;
0570     u8 buf[14];
0571     u16 adc_code;
0572 
0573     mutex_lock(&chip->adc_mutex_lock);
0574 
0575     channel->meas_en = true;
0576 
0577     ret = adc_tm5_read(chip, ADC_TM_GEN2_SID, buf, sizeof(buf));
0578     if (ret < 0) {
0579         dev_err(chip->dev, "adc-tm block read failed with %d\n", ret);
0580         goto config_fail;
0581     }
0582 
0583     /* Set SID from virtual channel number */
0584     buf[0] = channel->adc_channel >> 8;
0585 
0586     /* Set TM channel number used and measurement interval */
0587     buf[1] &= ~ADC_TM_GEN2_TM_CH_SEL;
0588     buf[1] |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel);
0589     buf[1] &= ~ADC_TM_GEN2_MEAS_INT_SEL;
0590     buf[1] |= FIELD_PREP(ADC_TM_GEN2_MEAS_INT_SEL, MEAS_INT_1S);
0591 
0592     buf[2] &= ~ADC_TM_GEN2_CTL_DEC_RATIO_MASK;
0593     buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_DEC_RATIO_MASK, channel->decimation);
0594     buf[2] &= ~ADC_TM_GEN2_CTL_CAL_SEL;
0595     buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_CAL_SEL, channel->cal_method);
0596 
0597     buf[3] = channel->avg_samples | ADC_TM_GEN2_FAST_AVG_EN;
0598 
0599     buf[4] = channel->adc_channel & 0xff;
0600 
0601     buf[5] = channel->hw_settle_time & ADC_TM_GEN2_HW_SETTLE_DELAY;
0602 
0603     /* High temperature corresponds to low voltage threshold */
0604     if (high != INT_MAX) {
0605         channel->low_thr_en = true;
0606         adc_code = qcom_adc_tm5_gen2_temp_res_scale(high);
0607         put_unaligned_le16(adc_code, &buf[9]);
0608     } else {
0609         channel->low_thr_en = false;
0610     }
0611 
0612     /* Low temperature corresponds to high voltage threshold */
0613     if (low != -INT_MAX) {
0614         channel->high_thr_en = true;
0615         adc_code = qcom_adc_tm5_gen2_temp_res_scale(low);
0616         put_unaligned_le16(adc_code, &buf[11]);
0617     } else {
0618         channel->high_thr_en = false;
0619     }
0620 
0621     buf[13] = ADC_TM_GEN2_MEAS_EN;
0622     if (channel->high_thr_en)
0623         buf[13] |= ADC_TM5_GEN2_HIGH_THR_INT_EN;
0624     if (channel->low_thr_en)
0625         buf[13] |= ADC_TM5_GEN2_LOW_THR_INT_EN;
0626 
0627     ret = adc_tm5_write(chip, ADC_TM_GEN2_SID, buf, sizeof(buf));
0628     if (ret) {
0629         dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
0630         goto config_fail;
0631     }
0632 
0633     ret = adc_tm5_gen2_conv_req(channel->chip);
0634     if (ret < 0)
0635         dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret);
0636 
0637 config_fail:
0638     mutex_unlock(&chip->adc_mutex_lock);
0639     return ret;
0640 }
0641 
0642 static int adc_tm5_set_trips(void *data, int low, int high)
0643 {
0644     struct adc_tm5_channel *channel = data;
0645     struct adc_tm5_chip *chip;
0646     int ret;
0647 
0648     if (!channel)
0649         return -EINVAL;
0650 
0651     chip = channel->chip;
0652     dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n",
0653         channel->channel, low, high);
0654 
0655     if (high == INT_MAX && low <= -INT_MAX)
0656         ret = chip->data->disable_channel(channel);
0657     else
0658         ret = chip->data->configure(channel, low, high);
0659 
0660     return ret;
0661 }
0662 
0663 static struct thermal_zone_of_device_ops adc_tm5_thermal_ops = {
0664     .get_temp = adc_tm5_get_temp,
0665     .set_trips = adc_tm5_set_trips,
0666 };
0667 
0668 static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm)
0669 {
0670     unsigned int i;
0671     struct thermal_zone_device *tzd;
0672 
0673     for (i = 0; i < adc_tm->nchannels; i++) {
0674         adc_tm->channels[i].chip = adc_tm;
0675 
0676         tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev,
0677                                adc_tm->channels[i].channel,
0678                                &adc_tm->channels[i],
0679                                &adc_tm5_thermal_ops);
0680         if (IS_ERR(tzd)) {
0681             if (PTR_ERR(tzd) == -ENODEV) {
0682                 dev_warn(adc_tm->dev, "thermal sensor on channel %d is not used\n",
0683                      adc_tm->channels[i].channel);
0684                 continue;
0685             }
0686 
0687             dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n",
0688                 adc_tm->channels[i].channel, PTR_ERR(tzd));
0689             return PTR_ERR(tzd);
0690         }
0691         adc_tm->channels[i].tzd = tzd;
0692         if (devm_thermal_add_hwmon_sysfs(tzd))
0693             dev_warn(adc_tm->dev,
0694                  "Failed to add hwmon sysfs attributes\n");
0695     }
0696 
0697     return 0;
0698 }
0699 
0700 static int adc_tm_hc_init(struct adc_tm5_chip *chip)
0701 {
0702     unsigned int i;
0703     u8 buf[2];
0704     int ret;
0705 
0706     for (i = 0; i < chip->nchannels; i++) {
0707         if (chip->channels[i].channel >= ADC_TM5_NUM_CHANNELS) {
0708             dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
0709             return -EINVAL;
0710         }
0711     }
0712 
0713     buf[0] = chip->decimation;
0714     buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
0715 
0716     ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
0717     if (ret)
0718         dev_err(chip->dev, "block write failed: %d\n", ret);
0719 
0720     return ret;
0721 }
0722 
0723 static int adc_tm5_init(struct adc_tm5_chip *chip)
0724 {
0725     u8 buf[4], channels_available;
0726     int ret;
0727     unsigned int i;
0728 
0729     ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
0730                &channels_available, sizeof(channels_available));
0731     if (ret) {
0732         dev_err(chip->dev, "read failed for BTM channels\n");
0733         return ret;
0734     }
0735 
0736     for (i = 0; i < chip->nchannels; i++) {
0737         if (chip->channels[i].channel >= channels_available) {
0738             dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
0739             return -EINVAL;
0740         }
0741     }
0742 
0743     buf[0] = chip->decimation;
0744     buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
0745     buf[2] = ADC_TM5_TIMER1;
0746     buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) |
0747          FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3);
0748 
0749     ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
0750     if (ret) {
0751         dev_err(chip->dev, "block write failed: %d\n", ret);
0752         return ret;
0753     }
0754 
0755     return ret;
0756 }
0757 
0758 static int adc_tm5_gen2_init(struct adc_tm5_chip *chip)
0759 {
0760     u8 channels_available;
0761     int ret;
0762     unsigned int i;
0763 
0764     ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
0765                &channels_available, sizeof(channels_available));
0766     if (ret) {
0767         dev_err(chip->dev, "read failed for BTM channels\n");
0768         return ret;
0769     }
0770 
0771     for (i = 0; i < chip->nchannels; i++) {
0772         if (chip->channels[i].channel >= channels_available) {
0773             dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
0774             return -EINVAL;
0775         }
0776     }
0777 
0778     mutex_init(&chip->adc_mutex_lock);
0779 
0780     return ret;
0781 }
0782 
0783 static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm,
0784                        struct adc_tm5_channel *channel,
0785                        struct device_node *node)
0786 {
0787     const char *name = node->name;
0788     u32 chan, value, adc_channel, varr[2];
0789     int ret;
0790     struct device *dev = adc_tm->dev;
0791     struct of_phandle_args args;
0792 
0793     ret = of_property_read_u32(node, "reg", &chan);
0794     if (ret) {
0795         dev_err(dev, "%s: invalid channel number %d\n", name, ret);
0796         return ret;
0797     }
0798 
0799     if (chan >= ADC_TM5_NUM_CHANNELS) {
0800         dev_err(dev, "%s: channel number too big: %d\n", name, chan);
0801         return -EINVAL;
0802     }
0803 
0804     channel->channel = chan;
0805 
0806     /*
0807      * We are tied to PMIC's ADC controller, which always use single
0808      * argument for channel number.  So don't bother parsing
0809      * #io-channel-cells, just enforce cell_count = 1.
0810      */
0811     ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args);
0812     if (ret < 0) {
0813         dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret);
0814         return ret;
0815     }
0816     of_node_put(args.np);
0817 
0818     if (args.args_count != 1) {
0819         dev_err(dev, "%s: invalid args count for ADC channel %d\n", name, chan);
0820         return -EINVAL;
0821     }
0822 
0823     adc_channel = args.args[0];
0824     if (adc_tm->data->gen == ADC_TM5_GEN2)
0825         adc_channel &= 0xff;
0826 
0827     if (adc_channel >= ADC5_MAX_CHANNEL) {
0828         dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan);
0829         return -EINVAL;
0830     }
0831     channel->adc_channel = args.args[0];
0832 
0833     channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL);
0834     if (IS_ERR(channel->iio)) {
0835         ret = PTR_ERR(channel->iio);
0836         if (ret != -EPROBE_DEFER)
0837             dev_err(dev, "%s: error getting channel: %d\n", name, ret);
0838         return ret;
0839     }
0840 
0841     ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
0842     if (!ret) {
0843         ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
0844         if (ret < 0) {
0845             dev_err(dev, "%s: invalid pre-scaling <%d %d>\n",
0846                 name, varr[0], varr[1]);
0847             return ret;
0848         }
0849         channel->prescale = ret;
0850     } else {
0851         /* 1:1 prescale is index 0 */
0852         channel->prescale = 0;
0853     }
0854 
0855     ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value);
0856     if (!ret) {
0857         ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle);
0858         if (ret < 0) {
0859             dev_err(dev, "%s invalid hw-settle-time-us %d us\n",
0860                 name, value);
0861             return ret;
0862         }
0863         channel->hw_settle_time = ret;
0864     } else {
0865         channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
0866     }
0867 
0868     if (of_property_read_bool(node, "qcom,ratiometric"))
0869         channel->cal_method = ADC_TM5_RATIOMETRIC_CAL;
0870     else
0871         channel->cal_method = ADC_TM5_ABSOLUTE_CAL;
0872 
0873     if (adc_tm->data->gen == ADC_TM5_GEN2) {
0874         ret = of_property_read_u32(node, "qcom,decimation", &value);
0875         if (!ret) {
0876             ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
0877             if (ret < 0) {
0878                 dev_err(dev, "invalid decimation %d\n", value);
0879                 return ret;
0880             }
0881             channel->decimation = ret;
0882         } else {
0883             channel->decimation = ADC5_DECIMATION_DEFAULT;
0884         }
0885 
0886         ret = of_property_read_u32(node, "qcom,avg-samples", &value);
0887         if (!ret) {
0888             ret = qcom_adc5_avg_samples_from_dt(value);
0889             if (ret < 0) {
0890                 dev_err(dev, "invalid avg-samples %d\n", value);
0891                 return ret;
0892             }
0893             channel->avg_samples = ret;
0894         } else {
0895             channel->avg_samples = VADC_DEF_AVG_SAMPLES;
0896         }
0897     }
0898 
0899     return 0;
0900 }
0901 
0902 static const struct adc_tm5_data adc_tm5_data_pmic = {
0903     .full_scale_code_volt = 0x70e4,
0904     .decimation = (unsigned int []) { 250, 420, 840 },
0905     .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
0906                      1000, 2000, 4000, 8000, 16000, 32000,
0907                      64000, 128000 },
0908     .disable_channel = adc_tm5_disable_channel,
0909     .configure = adc_tm5_configure,
0910     .isr = adc_tm5_isr,
0911     .init = adc_tm5_init,
0912     .irq_name = "pm-adc-tm5",
0913     .gen = ADC_TM5,
0914 };
0915 
0916 static const struct adc_tm5_data adc_tm_hc_data_pmic = {
0917     .full_scale_code_volt = 0x70e4,
0918     .decimation = (unsigned int []) { 256, 512, 1024 },
0919     .hw_settle = (unsigned int []) { 0, 100, 200, 300, 400, 500, 600, 700,
0920                      1000, 2000, 4000, 6000, 8000, 10000 },
0921     .disable_channel = adc_tm5_disable_channel,
0922     .configure = adc_tm5_configure,
0923     .isr = adc_tm5_isr,
0924     .init = adc_tm_hc_init,
0925     .irq_name = "pm-adc-tm5",
0926     .gen = ADC_TM_HC,
0927 };
0928 
0929 static const struct adc_tm5_data adc_tm5_gen2_data_pmic = {
0930     .full_scale_code_volt = 0x70e4,
0931     .decimation = (unsigned int []) { 85, 340, 1360 },
0932     .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
0933                      1000, 2000, 4000, 8000, 16000, 32000,
0934                      64000, 128000 },
0935     .disable_channel = adc_tm5_gen2_disable_channel,
0936     .configure = adc_tm5_gen2_configure,
0937     .isr = adc_tm5_gen2_isr,
0938     .init = adc_tm5_gen2_init,
0939     .irq_name = "pm-adc-tm5-gen2",
0940     .gen = ADC_TM5_GEN2,
0941 };
0942 
0943 static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node)
0944 {
0945     struct adc_tm5_channel *channels;
0946     struct device_node *child;
0947     u32 value;
0948     int ret;
0949     struct device *dev = adc_tm->dev;
0950 
0951     adc_tm->nchannels = of_get_available_child_count(node);
0952     if (!adc_tm->nchannels)
0953         return -EINVAL;
0954 
0955     adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels,
0956                     sizeof(*adc_tm->channels), GFP_KERNEL);
0957     if (!adc_tm->channels)
0958         return -ENOMEM;
0959 
0960     channels = adc_tm->channels;
0961 
0962     adc_tm->data = of_device_get_match_data(dev);
0963     if (!adc_tm->data)
0964         adc_tm->data = &adc_tm5_data_pmic;
0965 
0966     ret = of_property_read_u32(node, "qcom,decimation", &value);
0967     if (!ret) {
0968         ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
0969         if (ret < 0) {
0970             dev_err(dev, "invalid decimation %d\n", value);
0971             return ret;
0972         }
0973         adc_tm->decimation = ret;
0974     } else {
0975         adc_tm->decimation = ADC5_DECIMATION_DEFAULT;
0976     }
0977 
0978     ret = of_property_read_u32(node, "qcom,avg-samples", &value);
0979     if (!ret) {
0980         ret = qcom_adc5_avg_samples_from_dt(value);
0981         if (ret < 0) {
0982             dev_err(dev, "invalid avg-samples %d\n", value);
0983             return ret;
0984         }
0985         adc_tm->avg_samples = ret;
0986     } else {
0987         adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES;
0988     }
0989 
0990     for_each_available_child_of_node(node, child) {
0991         ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child);
0992         if (ret) {
0993             of_node_put(child);
0994             return ret;
0995         }
0996 
0997         channels++;
0998     }
0999 
1000     return 0;
1001 }
1002 
1003 static int adc_tm5_probe(struct platform_device *pdev)
1004 {
1005     struct device_node *node = pdev->dev.of_node;
1006     struct device *dev = &pdev->dev;
1007     struct adc_tm5_chip *adc_tm;
1008     struct regmap *regmap;
1009     int ret, irq;
1010     u32 reg;
1011 
1012     regmap = dev_get_regmap(dev->parent, NULL);
1013     if (!regmap)
1014         return -ENODEV;
1015 
1016     ret = of_property_read_u32(node, "reg", &reg);
1017     if (ret)
1018         return ret;
1019 
1020     adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL);
1021     if (!adc_tm)
1022         return -ENOMEM;
1023 
1024     adc_tm->regmap = regmap;
1025     adc_tm->dev = dev;
1026     adc_tm->base = reg;
1027 
1028     irq = platform_get_irq(pdev, 0);
1029     if (irq < 0) {
1030         dev_err(dev, "get_irq failed: %d\n", irq);
1031         return irq;
1032     }
1033 
1034     ret = adc_tm5_get_dt_data(adc_tm, node);
1035     if (ret) {
1036         dev_err(dev, "get dt data failed: %d\n", ret);
1037         return ret;
1038     }
1039 
1040     ret = adc_tm->data->init(adc_tm);
1041     if (ret) {
1042         dev_err(dev, "adc-tm init failed\n");
1043         return ret;
1044     }
1045 
1046     ret = adc_tm5_register_tzd(adc_tm);
1047     if (ret) {
1048         dev_err(dev, "tzd register failed\n");
1049         return ret;
1050     }
1051 
1052     return devm_request_threaded_irq(dev, irq, NULL, adc_tm->data->isr,
1053             IRQF_ONESHOT, adc_tm->data->irq_name, adc_tm);
1054 }
1055 
1056 static const struct of_device_id adc_tm5_match_table[] = {
1057     {
1058         .compatible = "qcom,spmi-adc-tm5",
1059         .data = &adc_tm5_data_pmic,
1060     },
1061     {
1062         .compatible = "qcom,spmi-adc-tm-hc",
1063         .data = &adc_tm_hc_data_pmic,
1064     },
1065     {
1066         .compatible = "qcom,spmi-adc-tm5-gen2",
1067         .data = &adc_tm5_gen2_data_pmic,
1068     },
1069     { }
1070 };
1071 MODULE_DEVICE_TABLE(of, adc_tm5_match_table);
1072 
1073 static struct platform_driver adc_tm5_driver = {
1074     .driver = {
1075         .name = "qcom-spmi-adc-tm5",
1076         .of_match_table = adc_tm5_match_table,
1077     },
1078     .probe = adc_tm5_probe,
1079 };
1080 module_platform_driver(adc_tm5_driver);
1081 
1082 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");
1083 MODULE_LICENSE("GPL v2");
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