staging/vt6655/rf.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
0004  * All rights reserved.
0005  *
0006  * Purpose: rf function code
0007  *
0008  * Author: Jerry Chen
0009  *
0010  * Date: Feb. 19, 2004
0011  *
0012  * Functions:
0013  *      IFRFbWriteEmbedded      - Embedded write RF register via MAC
0014  *
0015  * Revision History:
0016  *  RobertYu 2005
0017  *  chester 2008
0018  *
0019  */
0020
0021 #include "mac.h"
0022 #include "srom.h"
0023 #include "rf.h"
0024 #include "baseband.h"
0025
0026 #define BY_AL2230_REG_LEN     23 /* 24bit */
0027 #define CB_AL2230_INIT_SEQ    15
0028 #define SWITCH_CHANNEL_DELAY_AL2230 200 /* us */
0029 #define AL2230_PWR_IDX_LEN    64
0030
0031 #define BY_AL7230_REG_LEN     23 /* 24bit */
0032 #define CB_AL7230_INIT_SEQ    16
0033 #define SWITCH_CHANNEL_DELAY_AL7230 200 /* us */
0034 #define AL7230_PWR_IDX_LEN    64
0035
0036 static const unsigned long al2230_init_table[CB_AL2230_INIT_SEQ] = {
0037     0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0038     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0039     0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0040     0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0041     0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0042     0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0043     0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0044     0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0045     0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0046     0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0047     0x00DBBA00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0048     0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0049     0x0BDFFC00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0050     0x00000D00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0051     0x00580F00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
0052 };
0053
0054 static const unsigned long al2230_channel_table0[CB_MAX_CHANNEL] = {
0055     0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
0056     0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
0057     0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
0058     0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
0059     0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
0060     0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
0061     0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
0062     0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
0063     0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
0064     0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
0065     0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
0066     0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
0067     0x03F7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
0068     0x03E7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 14, Tf = 2412M */
0069 };
0070
0071 static const unsigned long al2230_channel_table1[CB_MAX_CHANNEL] = {
0072     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
0073     0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
0074     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
0075     0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
0076     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
0077     0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
0078     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
0079     0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
0080     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
0081     0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
0082     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
0083     0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
0084     0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
0085     0x06666100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 14, Tf = 2412M */
0086 };
0087
0088 static unsigned long al2230_power_table[AL2230_PWR_IDX_LEN] = {
0089     0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0090     0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0091     0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0092     0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0093     0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0094     0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0095     0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0096     0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0097     0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0098     0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0099     0x0404A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0100     0x0404B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0101     0x0404C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0102     0x0404D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0103     0x0404E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0104     0x0404F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0105     0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0106     0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0107     0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0108     0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0109     0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0110     0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0111     0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0112     0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0113     0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0114     0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0115     0x0405A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0116     0x0405B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0117     0x0405C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0118     0x0405D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0119     0x0405E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0120     0x0405F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0121     0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0122     0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0123     0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0124     0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0125     0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0126     0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0127     0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0128     0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0129     0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0130     0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0131     0x0406A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0132     0x0406B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0133     0x0406C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0134     0x0406D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0135     0x0406E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0136     0x0406F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0137     0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0138     0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0139     0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0140     0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0141     0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0142     0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0143     0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0144     0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0145     0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0146     0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0147     0x0407A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0148     0x0407B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0149     0x0407C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0150     0x0407D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0151     0x0407E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
0152     0x0407F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
0153 };
0154
0155 /*
0156  * Description: Write to IF/RF, by embedded programming
0157  *
0158  * Parameters:
0159  *  In:
0160  *      iobase      - I/O base address
0161  *      dwData      - data to write
0162  *  Out:
0163  *      none
0164  *
0165  * Return Value: true if succeeded; false if failed.
0166  *
0167  */
0168 bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)
0169 {
0170     void __iomem *iobase = priv->port_offset;
0171     unsigned short ww;
0172     unsigned long dwValue;
0173
0174     iowrite32((u32)dwData, iobase + MAC_REG_IFREGCTL);
0175
0176     /* W_MAX_TIMEOUT is the timeout period */
0177     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0178         dwValue = ioread32(iobase + MAC_REG_IFREGCTL);
0179         if (dwValue & IFREGCTL_DONE)
0180             break;
0181     }
0182
0183     if (ww == W_MAX_TIMEOUT)
0184         return false;
0185
0186     return true;
0187 }
0188
0189 /*
0190  * Description: AIROHA IFRF chip init function
0191  *
0192  * Parameters:
0193  *  In:
0194  *      iobase      - I/O base address
0195  *  Out:
0196  *      none
0197  *
0198  * Return Value: true if succeeded; false if failed.
0199  *
0200  */
0201 static bool RFbAL2230Init(struct vnt_private *priv)
0202 {
0203     void __iomem *iobase = priv->port_offset;
0204     int     ii;
0205     bool ret;
0206
0207     ret = true;
0208
0209     /* 3-wire control for normal mode */
0210     iowrite8(0, iobase + MAC_REG_SOFTPWRCTL);
0211
0212     vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL,
0213                     (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV));
0214     /* PLL  Off */
0215     vt6655_mac_word_reg_bits_off(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
0216
0217     /* patch abnormal AL2230 frequency output */
0218     IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
0219
0220     for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
0221         ret &= IFRFbWriteEmbedded(priv, al2230_init_table[ii]);
0222     MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */
0223
0224     /* PLL On */
0225     vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
0226
0227     MACvTimer0MicroSDelay(priv, 150);/* 150us */
0228     ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
0229     MACvTimer0MicroSDelay(priv, 30);/* 30us */
0230     ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
0231     MACvTimer0MicroSDelay(priv, 30);/* 30us */
0232     ret &= IFRFbWriteEmbedded(priv,
0233                   al2230_init_table[CB_AL2230_INIT_SEQ - 1]);
0234
0235     vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |
0236                                  SOFTPWRCTL_SWPE2    |
0237                                  SOFTPWRCTL_SWPECTI  |
0238                                  SOFTPWRCTL_TXPEINV));
0239
0240     /* 3-wire control for power saving mode */
0241     iowrite8(PSSIG_WPE3 | PSSIG_WPE2, iobase + MAC_REG_PSPWRSIG);
0242
0243     return ret;
0244 }
0245
0246 static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel)
0247 {
0248     void __iomem *iobase = priv->port_offset;
0249     bool ret;
0250
0251     ret = true;
0252
0253     ret &= IFRFbWriteEmbedded(priv, al2230_channel_table0[byChannel - 1]);
0254     ret &= IFRFbWriteEmbedded(priv, al2230_channel_table1[byChannel - 1]);
0255
0256     /* Set Channel[7] = 0 to tell H/W channel is changing now. */
0257     iowrite8(byChannel & 0x7F, iobase + MAC_REG_CHANNEL);
0258     MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230);
0259     /* Set Channel[7] = 1 to tell H/W channel change is done. */
0260     iowrite8(byChannel | 0x80, iobase + MAC_REG_CHANNEL);
0261
0262     return ret;
0263 }
0264
0265 /*
0266  * Description: RF init function
0267  *
0268  * Parameters:
0269  *  In:
0270  *      byBBType
0271  *      byRFType
0272  *  Out:
0273  *      none
0274  *
0275  * Return Value: true if succeeded; false if failed.
0276  *
0277  */
0278 bool RFbInit(struct vnt_private *priv)
0279 {
0280     bool ret = true;
0281
0282     switch (priv->byRFType) {
0283     case RF_AIROHA:
0284     case RF_AL2230S:
0285         priv->max_pwr_level = AL2230_PWR_IDX_LEN;
0286         ret = RFbAL2230Init(priv);
0287         break;
0288     case RF_NOTHING:
0289         ret = true;
0290         break;
0291     default:
0292         ret = false;
0293         break;
0294     }
0295     return ret;
0296 }
0297
0298 /*
0299  * Description: Select channel
0300  *
0301  * Parameters:
0302  *  In:
0303  *      byRFType
0304  *      byChannel    - Channel number
0305  *  Out:
0306  *      none
0307  *
0308  * Return Value: true if succeeded; false if failed.
0309  *
0310  */
0311 bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType,
0312               u16 byChannel)
0313 {
0314     bool ret = true;
0315
0316     switch (byRFType) {
0317     case RF_AIROHA:
0318     case RF_AL2230S:
0319         ret = RFbAL2230SelectChannel(priv, byChannel);
0320         break;
0321         /*{{ RobertYu: 20050104 */
0322     case RF_NOTHING:
0323         ret = true;
0324         break;
0325     default:
0326         ret = false;
0327         break;
0328     }
0329     return ret;
0330 }
0331
0332 /*
0333  * Description: Write WakeProgSyn
0334  *
0335  * Parameters:
0336  *  In:
0337  *      priv        - Device Structure
0338  *      rf_type     - RF type
0339  *      channel     - Channel number
0340  *
0341  * Return Value: true if succeeded; false if failed.
0342  *
0343  */
0344 bool rf_write_wake_prog_syn(struct vnt_private *priv, unsigned char rf_type,
0345                 u16 channel)
0346 {
0347     void __iomem *iobase = priv->port_offset;
0348     int i;
0349     unsigned char init_count = 0;
0350     unsigned char sleep_count = 0;
0351     unsigned short idx = MISCFIFO_SYNDATA_IDX;
0352
0353     iowrite16(0, iobase + MAC_REG_MISCFFNDEX);
0354     switch (rf_type) {
0355     case RF_AIROHA:
0356     case RF_AL2230S:
0357
0358         if (channel > CB_MAX_CHANNEL_24G)
0359             return false;
0360
0361          /* Init Reg + Channel Reg (2) */
0362         init_count = CB_AL2230_INIT_SEQ + 2;
0363         sleep_count = 0;
0364
0365         for (i = 0; i < CB_AL2230_INIT_SEQ; i++)
0366             MACvSetMISCFifo(priv, idx++, al2230_init_table[i]);
0367
0368         MACvSetMISCFifo(priv, idx++, al2230_channel_table0[channel - 1]);
0369         MACvSetMISCFifo(priv, idx++, al2230_channel_table1[channel - 1]);
0370         break;
0371
0372         /* Need to check, PLLON need to be low for channel setting */
0373
0374     case RF_NOTHING:
0375         return true;
0376
0377     default:
0378         return false;
0379     }
0380
0381     MACvSetMISCFifo(priv, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(sleep_count, init_count));
0382
0383     return true;
0384 }
0385
0386 /*
0387  * Description: Set Tx power
0388  *
0389  * Parameters:
0390  *  In:
0391  *      iobase         - I/O base address
0392  *      dwRFPowerTable - RF Tx Power Setting
0393  *  Out:
0394  *      none
0395  *
0396  * Return Value: true if succeeded; false if failed.
0397  *
0398  */
0399 bool RFbSetPower(struct vnt_private *priv, unsigned int rate, u16 uCH)
0400 {
0401     bool ret;
0402     unsigned char byPwr = 0;
0403     unsigned char byDec = 0;
0404
0405     if (priv->dwDiagRefCount != 0)
0406         return true;
0407
0408     if ((uCH < 1) || (uCH > CB_MAX_CHANNEL))
0409         return false;
0410
0411     switch (rate) {
0412     case RATE_1M:
0413     case RATE_2M:
0414     case RATE_5M:
0415     case RATE_11M:
0416         if (uCH > CB_MAX_CHANNEL_24G)
0417             return false;
0418
0419         byPwr = priv->abyCCKPwrTbl[uCH];
0420         break;
0421     case RATE_6M:
0422     case RATE_9M:
0423     case RATE_12M:
0424     case RATE_18M:
0425         byPwr = priv->abyOFDMPwrTbl[uCH];
0426         byDec = byPwr + 10;
0427
0428         if (byDec >= priv->max_pwr_level)
0429             byDec = priv->max_pwr_level - 1;
0430
0431         byPwr = byDec;
0432         break;
0433     case RATE_24M:
0434     case RATE_36M:
0435     case RATE_48M:
0436     case RATE_54M:
0437         byPwr = priv->abyOFDMPwrTbl[uCH];
0438         break;
0439     }
0440
0441     if (priv->byCurPwr == byPwr)
0442         return true;
0443
0444     ret = RFbRawSetPower(priv, byPwr, rate);
0445     if (ret)
0446         priv->byCurPwr = byPwr;
0447
0448     return ret;
0449 }
0450
0451 /*
0452  * Description: Set Tx power
0453  *
0454  * Parameters:
0455  *  In:
0456  *      iobase         - I/O base address
0457  *      dwRFPowerTable - RF Tx Power Setting
0458  *  Out:
0459  *      none
0460  *
0461  * Return Value: true if succeeded; false if failed.
0462  *
0463  */
0464
0465 bool RFbRawSetPower(struct vnt_private *priv, unsigned char byPwr,
0466             unsigned int rate)
0467 {
0468     bool ret = true;
0469
0470     if (byPwr >= priv->max_pwr_level)
0471         return false;
0472
0473     switch (priv->byRFType) {
0474     case RF_AIROHA:
0475         ret &= IFRFbWriteEmbedded(priv, al2230_power_table[byPwr]);
0476         if (rate <= RATE_11M)
0477             ret &= IFRFbWriteEmbedded(priv, 0x0001B400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
0478         else
0479             ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
0480
0481         break;
0482
0483     case RF_AL2230S:
0484         ret &= IFRFbWriteEmbedded(priv, al2230_power_table[byPwr]);
0485         if (rate <= RATE_11M) {
0486             ret &= IFRFbWriteEmbedded(priv, 0x040C1400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
0487             ret &= IFRFbWriteEmbedded(priv, 0x00299B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
0488         } else {
0489             ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
0490             ret &= IFRFbWriteEmbedded(priv, 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
0491         }
0492
0493         break;
0494
0495     default:
0496         break;
0497     }
0498     return ret;
0499 }
0500
0501 /*
0502  *
0503  * Routine Description:
0504  *     Translate RSSI to dBm
0505  *
0506  * Parameters:
0507  *  In:
0508  *      priv         - The adapter to be translated
0509  *      byCurrRSSI      - RSSI to be translated
0510  *  Out:
0511  *      pdwdbm          - Translated dbm number
0512  *
0513  * Return Value: none
0514  *
0515  */
0516 void
0517 RFvRSSITodBm(struct vnt_private *priv, unsigned char byCurrRSSI, long *pldBm)
0518 {
0519     unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
0520     long b = (byCurrRSSI & 0x3F);
0521     long a = 0;
0522     unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
0523
0524     switch (priv->byRFType) {
0525     case RF_AIROHA:
0526     case RF_AL2230S:
0527         a = abyAIROHARF[byIdx];
0528         break;
0529     default:
0530         break;
0531     }
0532
0533     *pldBm = -1 * (a + b * 2);
0534 }
0535