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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
0004  * All rights reserved.
0005  *
0006  * Purpose: MAC routines
0007  *
0008  * Author: Tevin Chen
0009  *
0010  * Date: May 21, 1996
0011  *
0012  * Revision History:
0013  *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
0014  *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
0015  *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
0016  */
0017 
0018 #ifndef __MAC_H__
0019 #define __MAC_H__
0020 
0021 #include "device.h"
0022 
0023 /*---------------------  Export Definitions -------------------------*/
0024 /* Registers in the MAC */
0025 #define MAC_MAX_CONTEXT_SIZE_PAGE0  256
0026 #define MAC_MAX_CONTEXT_SIZE_PAGE1  128
0027 
0028 /* Registers not related to 802.11b */
0029 #define MAC_REG_BCFG0       0x00
0030 #define MAC_REG_BCFG1       0x01
0031 #define MAC_REG_FCR0        0x02
0032 #define MAC_REG_FCR1        0x03
0033 #define MAC_REG_BISTCMD     0x04
0034 #define MAC_REG_BISTSR0     0x05
0035 #define MAC_REG_BISTSR1     0x06
0036 #define MAC_REG_BISTSR2     0x07
0037 #define MAC_REG_I2MCSR      0x08
0038 #define MAC_REG_I2MTGID     0x09
0039 #define MAC_REG_I2MTGAD     0x0A
0040 #define MAC_REG_I2MCFG      0x0B
0041 #define MAC_REG_I2MDIPT     0x0C
0042 #define MAC_REG_I2MDOPT     0x0E
0043 #define MAC_REG_PMC0        0x10
0044 #define MAC_REG_PMC1        0x11
0045 #define MAC_REG_STICKHW     0x12
0046 #define MAC_REG_LOCALID     0x14
0047 #define MAC_REG_TESTCFG     0x15
0048 #define MAC_REG_JUMPER0     0x16
0049 #define MAC_REG_JUMPER1     0x17
0050 #define MAC_REG_TMCTL0      0x18
0051 #define MAC_REG_TMCTL1      0x19
0052 #define MAC_REG_TMDATA0     0x1C
0053 
0054 /* MAC Parameter related */
0055 #define MAC_REG_LRT         0x20
0056 #define MAC_REG_SRT         0x21
0057 #define MAC_REG_SIFS        0x22
0058 #define MAC_REG_DIFS        0x23
0059 #define MAC_REG_EIFS        0x24
0060 #define MAC_REG_SLOT        0x25
0061 #define MAC_REG_BI          0x26
0062 #define MAC_REG_CWMAXMIN0   0x28
0063 #define MAC_REG_LINKOFFTOTM 0x2A
0064 #define MAC_REG_SWTMOT      0x2B
0065 #define MAC_REG_MIBCNTR     0x2C
0066 #define MAC_REG_RTSOKCNT    0x2C
0067 #define MAC_REG_RTSFAILCNT  0x2D
0068 #define MAC_REG_ACKFAILCNT  0x2E
0069 #define MAC_REG_FCSERRCNT   0x2F
0070 
0071 /* TSF Related */
0072 #define MAC_REG_TSFCNTR     0x30
0073 #define MAC_REG_NEXTTBTT    0x38
0074 #define MAC_REG_TSFOFST     0x40
0075 #define MAC_REG_TFTCTL      0x48
0076 
0077 /* WMAC Control/Status Related */
0078 #define MAC_REG_ENCFG       0x4C
0079 #define MAC_REG_PAGE1SEL    0x4F
0080 #define MAC_REG_CFG         0x50
0081 #define MAC_REG_TEST        0x52
0082 #define MAC_REG_HOSTCR      0x54
0083 #define MAC_REG_MACCR       0x55
0084 #define MAC_REG_RCR         0x56
0085 #define MAC_REG_TCR         0x57
0086 #define MAC_REG_IMR         0x58
0087 #define MAC_REG_ISR         0x5C
0088 
0089 /* Power Saving Related */
0090 #define MAC_REG_PSCFG       0x60
0091 #define MAC_REG_PSCTL       0x61
0092 #define MAC_REG_PSPWRSIG    0x62
0093 #define MAC_REG_BBCR13      0x63
0094 #define MAC_REG_AIDATIM     0x64
0095 #define MAC_REG_PWBT        0x66
0096 #define MAC_REG_WAKEOKTMR   0x68
0097 #define MAC_REG_CALTMR      0x69
0098 #define MAC_REG_SYNSPACCNT  0x6A
0099 #define MAC_REG_WAKSYNOPT   0x6B
0100 
0101 /* Baseband/IF Control Group */
0102 #define MAC_REG_BBREGCTL    0x6C
0103 #define MAC_REG_CHANNEL     0x6D
0104 #define MAC_REG_BBREGADR    0x6E
0105 #define MAC_REG_BBREGDATA   0x6F
0106 #define MAC_REG_IFREGCTL    0x70
0107 #define MAC_REG_IFDATA      0x71
0108 #define MAC_REG_ITRTMSET    0x74
0109 #define MAC_REG_PAPEDELAY   0x77
0110 #define MAC_REG_SOFTPWRCTL  0x78
0111 #define MAC_REG_GPIOCTL0    0x7A
0112 #define MAC_REG_GPIOCTL1    0x7B
0113 
0114 /* MAC DMA Related Group */
0115 #define MAC_REG_TXDMACTL0   0x7C
0116 #define MAC_REG_TXDMAPTR0   0x80
0117 #define MAC_REG_AC0DMACTL   0x84
0118 #define MAC_REG_AC0DMAPTR   0x88
0119 #define MAC_REG_BCNDMACTL   0x8C
0120 #define MAC_REG_BCNDMAPTR   0x90
0121 #define MAC_REG_RXDMACTL0   0x94
0122 #define MAC_REG_RXDMAPTR0   0x98
0123 #define MAC_REG_RXDMACTL1   0x9C
0124 #define MAC_REG_RXDMAPTR1   0xA0
0125 #define MAC_REG_SYNCDMACTL  0xA4
0126 #define MAC_REG_SYNCDMAPTR  0xA8
0127 #define MAC_REG_ATIMDMACTL  0xAC
0128 #define MAC_REG_ATIMDMAPTR  0xB0
0129 
0130 /* MiscFF PIO related */
0131 #define MAC_REG_MISCFFNDEX  0xB4
0132 #define MAC_REG_MISCFFCTL   0xB6
0133 #define MAC_REG_MISCFFDATA  0xB8
0134 
0135 /* Extend SW Timer */
0136 #define MAC_REG_TMDATA1     0xBC
0137 
0138 /* WOW Related Group */
0139 #define MAC_REG_WAKEUPEN0   0xC0
0140 #define MAC_REG_WAKEUPEN1   0xC1
0141 #define MAC_REG_WAKEUPSR0   0xC2
0142 #define MAC_REG_WAKEUPSR1   0xC3
0143 #define MAC_REG_WAKE128_0   0xC4
0144 #define MAC_REG_WAKE128_1   0xD4
0145 #define MAC_REG_WAKE128_2   0xE4
0146 #define MAC_REG_WAKE128_3   0xF4
0147 
0148 /************** Page 1 ******************/
0149 #define MAC_REG_CRC_128_0   0x04
0150 #define MAC_REG_CRC_128_1   0x06
0151 #define MAC_REG_CRC_128_2   0x08
0152 #define MAC_REG_CRC_128_3   0x0A
0153 
0154 /* MAC Configuration Group */
0155 #define MAC_REG_PAR0        0x0C
0156 #define MAC_REG_PAR4        0x10
0157 #define MAC_REG_BSSID0      0x14
0158 #define MAC_REG_BSSID4      0x18
0159 #define MAC_REG_MAR0        0x1C
0160 #define MAC_REG_MAR4        0x20
0161 
0162 /* MAC RSPPKT INFO Group */
0163 #define MAC_REG_RSPINF_B_1  0x24
0164 #define MAC_REG_RSPINF_B_2  0x28
0165 #define MAC_REG_RSPINF_B_5  0x2C
0166 #define MAC_REG_RSPINF_B_11 0x30
0167 #define MAC_REG_RSPINF_A_6  0x34
0168 #define MAC_REG_RSPINF_A_9  0x36
0169 #define MAC_REG_RSPINF_A_12 0x38
0170 #define MAC_REG_RSPINF_A_18 0x3A
0171 #define MAC_REG_RSPINF_A_24 0x3C
0172 #define MAC_REG_RSPINF_A_36 0x3E
0173 #define MAC_REG_RSPINF_A_48 0x40
0174 #define MAC_REG_RSPINF_A_54 0x42
0175 #define MAC_REG_RSPINF_A_72 0x44
0176 
0177 /* 802.11h relative */
0178 #define MAC_REG_QUIETINIT   0x60
0179 #define MAC_REG_QUIETGAP    0x62
0180 #define MAC_REG_QUIETDUR    0x64
0181 #define MAC_REG_MSRCTL      0x66
0182 #define MAC_REG_MSRBBSTS    0x67
0183 #define MAC_REG_MSRSTART    0x68
0184 #define MAC_REG_MSRDURATION 0x70
0185 #define MAC_REG_CCAFRACTION 0x72
0186 #define MAC_REG_PWRCCK      0x73
0187 #define MAC_REG_PWROFDM     0x7C
0188 
0189 /* Bits in the BCFG0 register */
0190 #define BCFG0_PERROFF       0x40
0191 #define BCFG0_MRDMDIS       0x20
0192 #define BCFG0_MRDLDIS       0x10
0193 #define BCFG0_MWMEN         0x08
0194 #define BCFG0_VSERREN       0x02
0195 #define BCFG0_LATMEN        0x01
0196 
0197 /* Bits in the BCFG1 register */
0198 #define BCFG1_CFUNOPT       0x80
0199 #define BCFG1_CREQOPT       0x40
0200 #define BCFG1_DMA8          0x10
0201 #define BCFG1_ARBITOPT      0x08
0202 #define BCFG1_PCIMEN        0x04
0203 #define BCFG1_MIOEN         0x02
0204 #define BCFG1_CISDLYEN      0x01
0205 
0206 /* Bits in RAMBIST registers */
0207 #define BISTCMD_TSTPAT5     0x00
0208 #define BISTCMD_TSTPATA     0x80
0209 #define BISTCMD_TSTERR      0x20
0210 #define BISTCMD_TSTPATF     0x18
0211 #define BISTCMD_TSTPAT0     0x10
0212 #define BISTCMD_TSTMODE     0x04
0213 #define BISTCMD_TSTITTX     0x03
0214 #define BISTCMD_TSTATRX     0x02
0215 #define BISTCMD_TSTATTX     0x01
0216 #define BISTCMD_TSTRX       0x00
0217 #define BISTSR0_BISTGO      0x01
0218 #define BISTSR1_TSTSR       0x01
0219 #define BISTSR2_CMDPRTEN    0x02
0220 #define BISTSR2_RAMTSTEN    0x01
0221 
0222 /* Bits in the I2MCFG EEPROM register */
0223 #define I2MCFG_BOUNDCTL     0x80
0224 #define I2MCFG_WAITCTL      0x20
0225 #define I2MCFG_SCLOECTL     0x10
0226 #define I2MCFG_WBUSYCTL     0x08
0227 #define I2MCFG_NORETRY      0x04
0228 #define I2MCFG_I2MLDSEQ     0x02
0229 #define I2MCFG_I2CMFAST     0x01
0230 
0231 /* Bits in the I2MCSR EEPROM register */
0232 #define I2MCSR_EEMW         0x80
0233 #define I2MCSR_EEMR         0x40
0234 #define I2MCSR_AUTOLD       0x08
0235 #define I2MCSR_NACK         0x02
0236 #define I2MCSR_DONE         0x01
0237 
0238 /* Bits in the PMC1 register */
0239 #define SPS_RST             0x80
0240 #define PCISTIKY            0x40
0241 #define PME_OVR             0x02
0242 
0243 /* Bits in the STICKYHW register */
0244 #define STICKHW_DS1_SHADOW  0x02
0245 #define STICKHW_DS0_SHADOW  0x01
0246 
0247 /* Bits in the TMCTL register */
0248 #define TMCTL_TSUSP         0x04
0249 #define TMCTL_TMD           0x02
0250 #define TMCTL_TE            0x01
0251 
0252 /* Bits in the TFTCTL register */
0253 #define TFTCTL_HWUTSF       0x80
0254 #define TFTCTL_TBTTSYNC     0x40
0255 #define TFTCTL_HWUTSFEN     0x20
0256 #define TFTCTL_TSFCNTRRD    0x10
0257 #define TFTCTL_TBTTSYNCEN   0x08
0258 #define TFTCTL_TSFSYNCEN    0x04
0259 #define TFTCTL_TSFCNTRST    0x02
0260 #define TFTCTL_TSFCNTREN    0x01
0261 
0262 /* Bits in the EnhanceCFG register */
0263 #define ENCFG_BARKERPREAM   0x00020000
0264 #define ENCFG_NXTBTTCFPSTR  0x00010000
0265 #define ENCFG_BCNSUSCLR     0x00000200
0266 #define ENCFG_BCNSUSIND     0x00000100
0267 #define ENCFG_CFP_PROTECTEN 0x00000040
0268 #define ENCFG_PROTECTMD     0x00000020
0269 #define ENCFG_HWPARCFP      0x00000010
0270 #define ENCFG_CFNULRSP      0x00000004
0271 #define ENCFG_BBTYPE_MASK   0x00000003
0272 #define ENCFG_BBTYPE_G      0x00000002
0273 #define ENCFG_BBTYPE_B      0x00000001
0274 #define ENCFG_BBTYPE_A      0x00000000
0275 
0276 /* Bits in the Page1Sel register */
0277 #define PAGE1_SEL           0x01
0278 
0279 /* Bits in the CFG register */
0280 #define CFG_TKIPOPT         0x80
0281 #define CFG_RXDMAOPT        0x40
0282 #define CFG_TMOT_SW         0x20
0283 #define CFG_TMOT_HWLONG     0x10
0284 #define CFG_TMOT_HW         0x00
0285 #define CFG_CFPENDOPT       0x08
0286 #define CFG_BCNSUSEN        0x04
0287 #define CFG_NOTXTIMEOUT     0x02
0288 #define CFG_NOBUFOPT        0x01
0289 
0290 /* Bits in the TEST register */
0291 #define TEST_LBEXT          0x80
0292 #define TEST_LBINT          0x40
0293 #define TEST_LBNONE         0x00
0294 #define TEST_SOFTINT        0x20
0295 #define TEST_CONTTX         0x10
0296 #define TEST_TXPE           0x08
0297 #define TEST_NAVDIS         0x04
0298 #define TEST_NOCTS          0x02
0299 #define TEST_NOACK          0x01
0300 
0301 /* Bits in the HOSTCR register */
0302 #define HOSTCR_TXONST       0x80
0303 #define HOSTCR_RXONST       0x40
0304 #define HOSTCR_ADHOC        0x20 /* Network Type 1 = Ad-hoc */
0305 #define HOSTCR_AP           0x10 /* Port Type 1 = AP */
0306 #define HOSTCR_TXON         0x08 /* 0000 1000 */
0307 #define HOSTCR_RXON         0x04 /* 0000 0100 */
0308 #define HOSTCR_MACEN        0x02 /* 0000 0010 */
0309 #define HOSTCR_SOFTRST      0x01 /* 0000 0001 */
0310 
0311 /* Bits in the MACCR register */
0312 #define MACCR_SYNCFLUSHOK   0x04
0313 #define MACCR_SYNCFLUSH     0x02
0314 #define MACCR_CLRNAV        0x01
0315 
0316 /* Bits in the MAC_REG_GPIOCTL0 register */
0317 #define LED_ACTSET           0x01
0318 #define LED_RFOFF            0x02
0319 #define LED_NOCONNECT        0x04
0320 
0321 /* Bits in the RCR register */
0322 #define RCR_SSID            0x80
0323 #define RCR_RXALLTYPE       0x40
0324 #define RCR_UNICAST         0x20
0325 #define RCR_BROADCAST       0x10
0326 #define RCR_MULTICAST       0x08
0327 #define RCR_WPAERR          0x04
0328 #define RCR_ERRCRC          0x02
0329 #define RCR_BSSID           0x01
0330 
0331 /* Bits in the TCR register */
0332 #define TCR_SYNCDCFOPT      0x02
0333 #define TCR_AUTOBCNTX       0x01 /* Beacon automatically transmit enable */
0334 
0335 /* Bits in the IMR register */
0336 #define IMR_MEASURESTART    0x80000000
0337 #define IMR_QUIETSTART      0x20000000
0338 #define IMR_RADARDETECT     0x10000000
0339 #define IMR_MEASUREEND      0x08000000
0340 #define IMR_SOFTTIMER1      0x00200000
0341 #define IMR_RXDMA1          0x00001000 /* 0000 0000 0001 0000 0000 0000 */
0342 #define IMR_RXNOBUF         0x00000800
0343 #define IMR_MIBNEARFULL     0x00000400
0344 #define IMR_SOFTINT         0x00000200
0345 #define IMR_FETALERR        0x00000100
0346 #define IMR_WATCHDOG        0x00000080
0347 #define IMR_SOFTTIMER       0x00000040
0348 #define IMR_GPIO            0x00000020
0349 #define IMR_TBTT            0x00000010
0350 #define IMR_RXDMA0          0x00000008
0351 #define IMR_BNTX            0x00000004
0352 #define IMR_AC0DMA          0x00000002
0353 #define IMR_TXDMA0          0x00000001
0354 
0355 /* Bits in the ISR register */
0356 #define ISR_MEASURESTART    0x80000000
0357 #define ISR_QUIETSTART      0x20000000
0358 #define ISR_RADARDETECT     0x10000000
0359 #define ISR_MEASUREEND      0x08000000
0360 #define ISR_SOFTTIMER1      0x00200000
0361 #define ISR_RXDMA1          0x00001000 /* 0000 0000 0001 0000 0000 0000 */
0362 #define ISR_RXNOBUF         0x00000800 /* 0000 0000 0000 1000 0000 0000 */
0363 #define ISR_MIBNEARFULL     0x00000400 /* 0000 0000 0000 0100 0000 0000 */
0364 #define ISR_SOFTINT         0x00000200
0365 #define ISR_FETALERR        0x00000100
0366 #define ISR_WATCHDOG        0x00000080
0367 #define ISR_SOFTTIMER       0x00000040
0368 #define ISR_GPIO            0x00000020
0369 #define ISR_TBTT            0x00000010
0370 #define ISR_RXDMA0          0x00000008
0371 #define ISR_BNTX            0x00000004
0372 #define ISR_AC0DMA          0x00000002
0373 #define ISR_TXDMA0          0x00000001
0374 
0375 /* Bits in the PSCFG register */
0376 #define PSCFG_PHILIPMD      0x40
0377 #define PSCFG_WAKECALEN     0x20
0378 #define PSCFG_WAKETMREN     0x10
0379 #define PSCFG_BBPSPROG      0x08
0380 #define PSCFG_WAKESYN       0x04
0381 #define PSCFG_SLEEPSYN      0x02
0382 #define PSCFG_AUTOSLEEP     0x01
0383 
0384 /* Bits in the PSCTL register */
0385 #define PSCTL_WAKEDONE      0x20
0386 #define PSCTL_PS            0x10
0387 #define PSCTL_GO2DOZE       0x08
0388 #define PSCTL_LNBCN         0x04
0389 #define PSCTL_ALBCN         0x02
0390 #define PSCTL_PSEN          0x01
0391 
0392 /* Bits in the PSPWSIG register */
0393 #define PSSIG_WPE3          0x80
0394 #define PSSIG_WPE2          0x40
0395 #define PSSIG_WPE1          0x20
0396 #define PSSIG_WRADIOPE      0x10
0397 #define PSSIG_SPE3          0x08
0398 #define PSSIG_SPE2          0x04
0399 #define PSSIG_SPE1          0x02
0400 #define PSSIG_SRADIOPE      0x01
0401 
0402 /* Bits in the BBREGCTL register */
0403 #define BBREGCTL_DONE       0x04
0404 #define BBREGCTL_REGR       0x02
0405 #define BBREGCTL_REGW       0x01
0406 
0407 /* Bits in the IFREGCTL register */
0408 #define IFREGCTL_DONE       0x04
0409 #define IFREGCTL_IFRF       0x02
0410 #define IFREGCTL_REGW       0x01
0411 
0412 /* Bits in the SOFTPWRCTL register */
0413 #define SOFTPWRCTL_RFLEOPT      0x0800
0414 #define SOFTPWRCTL_TXPEINV      0x0200
0415 #define SOFTPWRCTL_SWPECTI      0x0100
0416 #define SOFTPWRCTL_SWPAPE       0x0020
0417 #define SOFTPWRCTL_SWCALEN      0x0010
0418 #define SOFTPWRCTL_SWRADIO_PE   0x0008
0419 #define SOFTPWRCTL_SWPE2        0x0004
0420 #define SOFTPWRCTL_SWPE1        0x0002
0421 #define SOFTPWRCTL_SWPE3        0x0001
0422 
0423 /* Bits in the GPIOCTL1 register */
0424 #define GPIO1_DATA1             0x20
0425 #define GPIO1_MD1               0x10
0426 #define GPIO1_DATA0             0x02
0427 #define GPIO1_MD0               0x01
0428 
0429 /* Bits in the DMACTL register */
0430 #define DMACTL_CLRRUN       0x00080000
0431 #define DMACTL_RUN          0x00000008
0432 #define DMACTL_WAKE         0x00000004
0433 #define DMACTL_DEAD         0x00000002
0434 #define DMACTL_ACTIVE       0x00000001
0435 
0436 /* Bits in the RXDMACTL0 register */
0437 #define RX_PERPKT           0x00000100
0438 #define RX_PERPKTCLR        0x01000000
0439 
0440 /* Bits in the BCNDMACTL register */
0441 #define BEACON_READY        0x01
0442 
0443 /* Bits in the MISCFFCTL register */
0444 #define MISCFFCTL_WRITE     0x0001
0445 
0446 /* Bits in WAKEUPEN0 */
0447 #define WAKEUPEN0_DIRPKT    0x10
0448 #define WAKEUPEN0_LINKOFF   0x08
0449 #define WAKEUPEN0_ATIMEN    0x04
0450 #define WAKEUPEN0_TIMEN     0x02
0451 #define WAKEUPEN0_MAGICEN   0x01
0452 
0453 /* Bits in WAKEUPEN1 */
0454 #define WAKEUPEN1_128_3     0x08
0455 #define WAKEUPEN1_128_2     0x04
0456 #define WAKEUPEN1_128_1     0x02
0457 #define WAKEUPEN1_128_0     0x01
0458 
0459 /* Bits in WAKEUPSR0 */
0460 #define WAKEUPSR0_DIRPKT    0x10
0461 #define WAKEUPSR0_LINKOFF   0x08
0462 #define WAKEUPSR0_ATIMEN    0x04
0463 #define WAKEUPSR0_TIMEN     0x02
0464 #define WAKEUPSR0_MAGICEN   0x01
0465 
0466 /* Bits in WAKEUPSR1 */
0467 #define WAKEUPSR1_128_3     0x08
0468 #define WAKEUPSR1_128_2     0x04
0469 #define WAKEUPSR1_128_1     0x02
0470 #define WAKEUPSR1_128_0     0x01
0471 
0472 /* Bits in the MAC_REG_GPIOCTL register */
0473 #define GPIO0_MD            0x01
0474 #define GPIO0_DATA          0x02
0475 #define GPIO0_INTMD         0x04
0476 #define GPIO1_MD            0x10
0477 #define GPIO1_DATA          0x20
0478 
0479 /* Bits in the MSRCTL register */
0480 #define MSRCTL_FINISH       0x80
0481 #define MSRCTL_READY        0x40
0482 #define MSRCTL_RADARDETECT  0x20
0483 #define MSRCTL_EN           0x10
0484 #define MSRCTL_QUIETTXCHK   0x08
0485 #define MSRCTL_QUIETRPT     0x04
0486 #define MSRCTL_QUIETINT     0x02
0487 #define MSRCTL_QUIETEN      0x01
0488 
0489 /* Bits in the MSRCTL1 register */
0490 #define MSRCTL1_TXPWR       0x08
0491 #define MSRCTL1_CSAPAREN    0x04
0492 #define MSRCTL1_TXPAUSE     0x01
0493 
0494 /* Loopback mode */
0495 #define MAC_LB_EXT          0x02
0496 #define MAC_LB_INTERNAL     0x01
0497 #define MAC_LB_NONE         0x00
0498 
0499 #define DEFAULT_BI          0x200
0500 
0501 /* MiscFIFO Offset */
0502 #define MISCFIFO_KEYETRY0       32
0503 #define MISCFIFO_KEYENTRYSIZE   22
0504 #define MISCFIFO_SYNINFO_IDX    10
0505 #define MISCFIFO_SYNDATA_IDX    11
0506 #define MISCFIFO_SYNDATASIZE    21
0507 
0508 /* enabled mask value of irq */
0509 #define IMR_MASK_VALUE     (IMR_SOFTTIMER1 |    \
0510                 IMR_RXDMA1 |    \
0511                 IMR_RXNOBUF |   \
0512                 IMR_MIBNEARFULL |   \
0513                 IMR_SOFTINT |   \
0514                 IMR_FETALERR |  \
0515                 IMR_WATCHDOG |  \
0516                 IMR_SOFTTIMER | \
0517                 IMR_GPIO |      \
0518                 IMR_TBTT |      \
0519                 IMR_RXDMA0 |    \
0520                 IMR_BNTX |      \
0521                 IMR_AC0DMA |    \
0522                 IMR_TXDMA0)
0523 
0524 /* max time out delay time */
0525 #define W_MAX_TIMEOUT       0xFFF0U
0526 
0527 /* wait time within loop */
0528 #define CB_DELAY_LOOP_WAIT  10 /* 10ms */
0529 
0530 /* revision id */
0531 #define REV_ID_VT3253_A0    0x00
0532 #define REV_ID_VT3253_A1    0x01
0533 #define REV_ID_VT3253_B0    0x08
0534 #define REV_ID_VT3253_B1    0x09
0535 
0536 /*---------------------  Export Types  ------------------------------*/
0537 
0538 /*---------------------  Export Macros ------------------------------*/
0539 
0540 #define MACvReceive0(iobase)                        \
0541 do {                                    \
0542     unsigned long dwData;                       \
0543     dwData = ioread32(iobase + MAC_REG_RXDMACTL0);          \
0544     if (dwData & DMACTL_RUN)                    \
0545         iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL0); \
0546     else                                \
0547         iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL0);  \
0548 } while (0)
0549 
0550 #define MACvReceive1(iobase)                        \
0551 do {                                    \
0552     unsigned long dwData;                       \
0553     dwData = ioread32(iobase + MAC_REG_RXDMACTL1);          \
0554     if (dwData & DMACTL_RUN)                    \
0555         iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL1); \
0556     else                                \
0557         iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL1);  \
0558 } while (0)
0559 
0560 #define MACvTransmit0(iobase)                       \
0561 do {                                    \
0562     unsigned long dwData;                       \
0563     dwData = ioread32(iobase + MAC_REG_TXDMACTL0);          \
0564     if (dwData & DMACTL_RUN)                    \
0565         iowrite32(DMACTL_WAKE, iobase + MAC_REG_TXDMACTL0); \
0566     else                                \
0567         iowrite32(DMACTL_RUN, iobase + MAC_REG_TXDMACTL0);  \
0568 } while (0)
0569 
0570 #define MACvTransmitAC0(iobase)                 \
0571 do {                                    \
0572     unsigned long dwData;                       \
0573     dwData = ioread32(iobase + MAC_REG_AC0DMACTL);          \
0574     if (dwData & DMACTL_RUN)                    \
0575         iowrite32(DMACTL_WAKE, iobase + MAC_REG_AC0DMACTL); \
0576     else                                \
0577         iowrite32(DMACTL_RUN, iobase + MAC_REG_AC0DMACTL);  \
0578 } while (0)
0579 
0580 #define MACvSelectPage0(iobase)             \
0581     iowrite8(0, iobase + MAC_REG_PAGE1SEL)
0582 
0583 #define MACvSelectPage1(iobase)             \
0584     iowrite8(1, iobase + MAC_REG_PAGE1SEL)
0585 
0586 #define MACvEnableProtectMD(iobase)                 \
0587 do {                                    \
0588     unsigned long dwOrgValue;                   \
0589     dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);          \
0590     dwOrgValue = dwOrgValue | ENCFG_PROTECTMD;          \
0591     iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);     \
0592 } while (0)
0593 
0594 #define MACvDisableProtectMD(iobase)                    \
0595 do {                                    \
0596     unsigned long dwOrgValue;                   \
0597     dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);          \
0598     dwOrgValue = dwOrgValue & ~ENCFG_PROTECTMD;         \
0599     iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);     \
0600 } while (0)
0601 
0602 #define MACvEnableBarkerPreambleMd(iobase)              \
0603 do {                                    \
0604     unsigned long dwOrgValue;                   \
0605     dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);          \
0606     dwOrgValue = dwOrgValue | ENCFG_BARKERPREAM;            \
0607     iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);     \
0608 } while (0)
0609 
0610 #define MACvDisableBarkerPreambleMd(iobase)             \
0611 do {                                    \
0612     unsigned long dwOrgValue;                   \
0613     dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);          \
0614     dwOrgValue = dwOrgValue & ~ENCFG_BARKERPREAM;           \
0615     iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);     \
0616 } while (0)
0617 
0618 #define MACvSetBBType(iobase, byTyp)                    \
0619 do {                                    \
0620     unsigned long dwOrgValue;                   \
0621     dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);          \
0622     dwOrgValue = dwOrgValue & ~ENCFG_BBTYPE_MASK;           \
0623     dwOrgValue = dwOrgValue | (unsigned long)byTyp;         \
0624     iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);     \
0625 } while (0)
0626 
0627 #define MACvSetRFLE_LatchBase(iobase)                                 \
0628     vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
0629 
0630 #define MAKEWORD(lb, hb) \
0631     ((unsigned short)(((unsigned char)(lb)) | (((unsigned short)((unsigned char)(hb))) << 8)))
0632 
0633 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask);
0634 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask);
0635 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask);
0636 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask);
0637 
0638 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
0639               unsigned char byTestBits);
0640 
0641 bool MACbIsIntDisable(struct vnt_private *priv);
0642 
0643 void MACvSetShortRetryLimit(struct vnt_private *priv,
0644                 unsigned char byRetryLimit);
0645 
0646 void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit);
0647 
0648 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode);
0649 
0650 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf);
0651 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf);
0652 
0653 bool MACbSoftwareReset(struct vnt_private *priv);
0654 bool MACbSafeSoftwareReset(struct vnt_private *priv);
0655 bool MACbSafeRxOff(struct vnt_private *priv);
0656 bool MACbSafeTxOff(struct vnt_private *priv);
0657 bool MACbSafeStop(struct vnt_private *priv);
0658 bool MACbShutdown(struct vnt_private *priv);
0659 void MACvInitialize(struct vnt_private *priv);
0660 void MACvSetCurrRx0DescAddr(struct vnt_private *priv,
0661                 u32 curr_desc_addr);
0662 void MACvSetCurrRx1DescAddr(struct vnt_private *priv,
0663                 u32 curr_desc_addr);
0664 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
0665                u32 curr_desc_addr);
0666 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
0667                   u32 curr_desc_addr);
0668 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
0669                   u32 curr_desc_addr);
0670 void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv,
0671                    u32 curr_desc_addr);
0672 void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv,
0673                    u32 curr_desc_addr);
0674 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay);
0675 void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime);
0676 
0677 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset,
0678              u32 dwData);
0679 
0680 bool MACbPSWakeup(struct vnt_private *priv);
0681 
0682 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
0683              unsigned int uEntryIdx, unsigned int uKeyIdx,
0684              unsigned char *pbyAddr, u32 *pdwKey,
0685              unsigned char local_id);
0686 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx);
0687 
0688 #endif /* __MAC_H__ */
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