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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
0004  * All rights reserved.
0005  *
0006  * Purpose:  MAC routines
0007  *
0008  * Author: Tevin Chen
0009  *
0010  * Date: May 21, 1996
0011  *
0012  * Functions:
0013  *      MACbIsRegBitsOff - Test if All test Bits Off
0014  *      MACbIsIntDisable - Test if MAC interrupt disable
0015  *      MACvSetShortRetryLimit - Set 802.11 Short Retry limit
0016  *      MACvSetLongRetryLimit - Set 802.11 Long Retry limit
0017  *      MACvSetLoopbackMode - Set MAC Loopback Mode
0018  *      MACvSaveContext - Save Context of MAC Registers
0019  *      MACvRestoreContext - Restore Context of MAC Registers
0020  *      MACbSoftwareReset - Software Reset MAC
0021  *      MACbSafeRxOff - Turn Off MAC Rx
0022  *      MACbSafeTxOff - Turn Off MAC Tx
0023  *      MACbSafeStop - Stop MAC function
0024  *      MACbShutdown - Shut down MAC
0025  *      MACvInitialize - Initialize MAC
0026  *      MACvSetCurrRxDescAddr - Set Rx Descriptors Address
0027  *      MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
0028  *      MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
0029  *      MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
0030  *
0031  * Revision History:
0032  *      08-22-2003 Kyle Hsu     :  Porting MAC functions from sim53
0033  *      09-03-2003 Bryan YC Fan :  Add MACvClearBusSusInd()&
0034  *                 MACvEnableBusSusEn()
0035  *      09-18-2003 Jerry Chen   :  Add MACvSetKeyEntry & MACvDisableKeyEntry
0036  *
0037  */
0038 
0039 #include "mac.h"
0040 
0041 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask)
0042 {
0043     unsigned char reg_value;
0044 
0045     reg_value = ioread8(iobase + reg_offset);
0046     iowrite8(reg_value | bit_mask, iobase + reg_offset);
0047 }
0048 
0049 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask)
0050 {
0051     unsigned short reg_value;
0052 
0053     reg_value = ioread16(iobase + reg_offset);
0054     iowrite16(reg_value | (bit_mask), iobase + reg_offset);
0055 }
0056 
0057 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask)
0058 {
0059     unsigned char reg_value;
0060 
0061     reg_value = ioread8(iobase + reg_offset);
0062     iowrite8(reg_value & ~(bit_mask), iobase + reg_offset);
0063 }
0064 
0065 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask)
0066 {
0067     unsigned short reg_value;
0068 
0069     reg_value = ioread16(iobase + reg_offset);
0070     iowrite16(reg_value & ~(bit_mask), iobase + reg_offset);
0071 }
0072 
0073 static void vt6655_mac_clear_stck_ds(void __iomem *iobase)
0074 {
0075     u8 reg_value;
0076 
0077     reg_value = ioread8(iobase + MAC_REG_STICKHW);
0078     reg_value = reg_value & 0xFC;
0079     iowrite8(reg_value, iobase + MAC_REG_STICKHW);
0080 }
0081 
0082 /*
0083  * Description:
0084  *      Test if all test bits off
0085  *
0086  * Parameters:
0087  *  In:
0088  *      io_base    - Base Address for MAC
0089  *      byRegOfs    - Offset of MAC Register
0090  *      byTestBits  - Test bits
0091  *  Out:
0092  *      none
0093  *
0094  * Return Value: true if all test bits Off; otherwise false
0095  *
0096  */
0097 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
0098               unsigned char byTestBits)
0099 {
0100     void __iomem *io_base = priv->port_offset;
0101 
0102     return !(ioread8(io_base + byRegOfs) & byTestBits);
0103 }
0104 
0105 /*
0106  * Description:
0107  *      Test if MAC interrupt disable
0108  *
0109  * Parameters:
0110  *  In:
0111  *      io_base    - Base Address for MAC
0112  *  Out:
0113  *      none
0114  *
0115  * Return Value: true if interrupt is disable; otherwise false
0116  *
0117  */
0118 bool MACbIsIntDisable(struct vnt_private *priv)
0119 {
0120     void __iomem *io_base = priv->port_offset;
0121 
0122     if (ioread32(io_base + MAC_REG_IMR))
0123         return false;
0124 
0125     return true;
0126 }
0127 
0128 /*
0129  * Description:
0130  *      Set 802.11 Short Retry Limit
0131  *
0132  * Parameters:
0133  *  In:
0134  *      io_base    - Base Address for MAC
0135  *      byRetryLimit- Retry Limit
0136  *  Out:
0137  *      none
0138  *
0139  * Return Value: none
0140  *
0141  */
0142 void MACvSetShortRetryLimit(struct vnt_private *priv,
0143                 unsigned char byRetryLimit)
0144 {
0145     void __iomem *io_base = priv->port_offset;
0146     /* set SRT */
0147     iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
0148 }
0149 
0150 /*
0151  * Description:
0152  *      Set 802.11 Long Retry Limit
0153  *
0154  * Parameters:
0155  *  In:
0156  *      io_base    - Base Address for MAC
0157  *      byRetryLimit- Retry Limit
0158  *  Out:
0159  *      none
0160  *
0161  * Return Value: none
0162  *
0163  */
0164 void MACvSetLongRetryLimit(struct vnt_private *priv,
0165                unsigned char byRetryLimit)
0166 {
0167     void __iomem *io_base = priv->port_offset;
0168     /* set LRT */
0169     iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
0170 }
0171 
0172 /*
0173  * Description:
0174  *      Set MAC Loopback mode
0175  *
0176  * Parameters:
0177  *  In:
0178  *      io_base        - Base Address for MAC
0179  *      byLoopbackMode  - Loopback Mode
0180  *  Out:
0181  *      none
0182  *
0183  * Return Value: none
0184  *
0185  */
0186 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
0187 {
0188     void __iomem *io_base = priv->port_offset;
0189 
0190     byLoopbackMode <<= 6;
0191     /* set TCR */
0192     iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
0193          io_base + MAC_REG_TEST);
0194 }
0195 
0196 /*
0197  * Description:
0198  *      Save MAC registers to context buffer
0199  *
0200  * Parameters:
0201  *  In:
0202  *      io_base    - Base Address for MAC
0203  *  Out:
0204  *      cxt_buf   - Context buffer
0205  *
0206  * Return Value: none
0207  *
0208  */
0209 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
0210 {
0211     void __iomem *io_base = priv->port_offset;
0212 
0213     /* read page0 register */
0214     memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
0215 
0216     MACvSelectPage1(io_base);
0217 
0218     /* read page1 register */
0219     memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
0220               MAC_MAX_CONTEXT_SIZE_PAGE1);
0221 
0222     MACvSelectPage0(io_base);
0223 }
0224 
0225 /*
0226  * Description:
0227  *      Restore MAC registers from context buffer
0228  *
0229  * Parameters:
0230  *  In:
0231  *      io_base    - Base Address for MAC
0232  *      cxt_buf   - Context buffer
0233  *  Out:
0234  *      none
0235  *
0236  * Return Value: none
0237  *
0238  */
0239 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
0240 {
0241     void __iomem *io_base = priv->port_offset;
0242 
0243     MACvSelectPage1(io_base);
0244     /* restore page1 */
0245     memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
0246             MAC_MAX_CONTEXT_SIZE_PAGE1);
0247 
0248     MACvSelectPage0(io_base);
0249 
0250     /* restore RCR,TCR,IMR... */
0251     memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
0252             MAC_REG_ISR - MAC_REG_RCR);
0253 
0254     /* restore MAC Config. */
0255     memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
0256             MAC_REG_PAGE1SEL - MAC_REG_LRT);
0257 
0258     iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
0259 
0260     /* restore PS Config. */
0261     memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
0262             MAC_REG_BBREGCTL - MAC_REG_PSCFG);
0263 
0264     /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
0265     iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
0266           io_base + MAC_REG_TXDMAPTR0);
0267     iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
0268           io_base + MAC_REG_AC0DMAPTR);
0269     iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
0270           io_base + MAC_REG_BCNDMAPTR);
0271     iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
0272           io_base + MAC_REG_RXDMAPTR0);
0273     iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
0274           io_base + MAC_REG_RXDMAPTR1);
0275 }
0276 
0277 /*
0278  * Description:
0279  *      Software Reset MAC
0280  *
0281  * Parameters:
0282  *  In:
0283  *      io_base    - Base Address for MAC
0284  *  Out:
0285  *      none
0286  *
0287  * Return Value: true if Reset Success; otherwise false
0288  *
0289  */
0290 bool MACbSoftwareReset(struct vnt_private *priv)
0291 {
0292     void __iomem *io_base = priv->port_offset;
0293     unsigned short ww;
0294 
0295     /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
0296     iowrite8(0x01, io_base + MAC_REG_HOSTCR);
0297 
0298     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0299         if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
0300             break;
0301     }
0302     if (ww == W_MAX_TIMEOUT)
0303         return false;
0304     return true;
0305 }
0306 
0307 /*
0308  * Description:
0309  *      save some important register's value, then do reset, then restore
0310  *  register's value
0311  *
0312  * Parameters:
0313  *  In:
0314  *      io_base    - Base Address for MAC
0315  *  Out:
0316  *      none
0317  *
0318  * Return Value: true if success; otherwise false
0319  *
0320  */
0321 bool MACbSafeSoftwareReset(struct vnt_private *priv)
0322 {
0323     unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
0324     bool bRetVal;
0325 
0326     /* PATCH....
0327      * save some important register's value, then do
0328      * reset, then restore register's value
0329      */
0330     /* save MAC context */
0331     MACvSaveContext(priv, abyTmpRegData);
0332     /* do reset */
0333     bRetVal = MACbSoftwareReset(priv);
0334     /* restore MAC context, except CR0 */
0335     MACvRestoreContext(priv, abyTmpRegData);
0336 
0337     return bRetVal;
0338 }
0339 
0340 /*
0341  * Description:
0342  *      Turn Off MAC Rx
0343  *
0344  * Parameters:
0345  *  In:
0346  *      io_base    - Base Address for MAC
0347  *  Out:
0348  *      none
0349  *
0350  * Return Value: true if success; otherwise false
0351  *
0352  */
0353 bool MACbSafeRxOff(struct vnt_private *priv)
0354 {
0355     void __iomem *io_base = priv->port_offset;
0356     unsigned short ww;
0357 
0358     /* turn off wow temp for turn off Rx safely */
0359 
0360     /* Clear RX DMA0,1 */
0361     iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
0362     iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
0363     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0364         if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
0365             break;
0366     }
0367     if (ww == W_MAX_TIMEOUT) {
0368         pr_debug(" DBG_PORT80(0x10)\n");
0369         return false;
0370     }
0371     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0372         if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
0373             break;
0374     }
0375     if (ww == W_MAX_TIMEOUT) {
0376         pr_debug(" DBG_PORT80(0x11)\n");
0377         return false;
0378     }
0379 
0380     /* try to safe shutdown RX */
0381     vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
0382     /* W_MAX_TIMEOUT is the timeout period */
0383     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0384         if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
0385             break;
0386     }
0387     if (ww == W_MAX_TIMEOUT) {
0388         pr_debug(" DBG_PORT80(0x12)\n");
0389         return false;
0390     }
0391     return true;
0392 }
0393 
0394 /*
0395  * Description:
0396  *      Turn Off MAC Tx
0397  *
0398  * Parameters:
0399  *  In:
0400  *      io_base    - Base Address for MAC
0401  *  Out:
0402  *      none
0403  *
0404  * Return Value: true if success; otherwise false
0405  *
0406  */
0407 bool MACbSafeTxOff(struct vnt_private *priv)
0408 {
0409     void __iomem *io_base = priv->port_offset;
0410     unsigned short ww;
0411 
0412     /* Clear TX DMA */
0413     /* Tx0 */
0414     iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
0415     /* AC0 */
0416     iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
0417 
0418     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0419         if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
0420             break;
0421     }
0422     if (ww == W_MAX_TIMEOUT) {
0423         pr_debug(" DBG_PORT80(0x20)\n");
0424         return false;
0425     }
0426     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0427         if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
0428             break;
0429     }
0430     if (ww == W_MAX_TIMEOUT) {
0431         pr_debug(" DBG_PORT80(0x21)\n");
0432         return false;
0433     }
0434 
0435     /* try to safe shutdown TX */
0436     vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
0437 
0438     /* W_MAX_TIMEOUT is the timeout period */
0439     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0440         if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
0441             break;
0442     }
0443     if (ww == W_MAX_TIMEOUT) {
0444         pr_debug(" DBG_PORT80(0x24)\n");
0445         return false;
0446     }
0447     return true;
0448 }
0449 
0450 /*
0451  * Description:
0452  *      Stop MAC function
0453  *
0454  * Parameters:
0455  *  In:
0456  *      io_base    - Base Address for MAC
0457  *  Out:
0458  *      none
0459  *
0460  * Return Value: true if success; otherwise false
0461  *
0462  */
0463 bool MACbSafeStop(struct vnt_private *priv)
0464 {
0465     void __iomem *io_base = priv->port_offset;
0466 
0467     vt6655_mac_reg_bits_off(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
0468 
0469     if (!MACbSafeRxOff(priv)) {
0470         pr_debug(" MACbSafeRxOff == false)\n");
0471         MACbSafeSoftwareReset(priv);
0472         return false;
0473     }
0474     if (!MACbSafeTxOff(priv)) {
0475         pr_debug(" MACbSafeTxOff == false)\n");
0476         MACbSafeSoftwareReset(priv);
0477         return false;
0478     }
0479 
0480     vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
0481 
0482     return true;
0483 }
0484 
0485 /*
0486  * Description:
0487  *      Shut Down MAC
0488  *
0489  * Parameters:
0490  *  In:
0491  *      io_base    - Base Address for MAC
0492  *  Out:
0493  *      none
0494  *
0495  * Return Value: true if success; otherwise false
0496  *
0497  */
0498 bool MACbShutdown(struct vnt_private *priv)
0499 {
0500     void __iomem *io_base = priv->port_offset;
0501     /* disable MAC IMR */
0502     iowrite32(0, io_base + MAC_REG_IMR);
0503     MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
0504     /* stop the adapter */
0505     if (!MACbSafeStop(priv)) {
0506         MACvSetLoopbackMode(priv, MAC_LB_NONE);
0507         return false;
0508     }
0509     MACvSetLoopbackMode(priv, MAC_LB_NONE);
0510     return true;
0511 }
0512 
0513 /*
0514  * Description:
0515  *      Initialize MAC
0516  *
0517  * Parameters:
0518  *  In:
0519  *      io_base    - Base Address for MAC
0520  *  Out:
0521  *      none
0522  *
0523  * Return Value: none
0524  *
0525  */
0526 void MACvInitialize(struct vnt_private *priv)
0527 {
0528     void __iomem *io_base = priv->port_offset;
0529     /* clear sticky bits */
0530     vt6655_mac_clear_stck_ds(io_base);
0531     /* disable force PME-enable */
0532     iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
0533     /* only 3253 A */
0534 
0535     /* do reset */
0536     MACbSoftwareReset(priv);
0537 
0538     /* reset TSF counter */
0539     iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
0540     /* enable TSF counter */
0541     iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
0542 }
0543 
0544 /*
0545  * Description:
0546  *      Set the chip with current rx descriptor address
0547  *
0548  * Parameters:
0549  *  In:
0550  *      io_base        - Base Address for MAC
0551  *      curr_desc_addr  - Descriptor Address
0552  *  Out:
0553  *      none
0554  *
0555  * Return Value: none
0556  *
0557  */
0558 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
0559 {
0560     void __iomem *io_base = priv->port_offset;
0561     unsigned short ww;
0562     unsigned char org_dma_ctl;
0563 
0564     org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
0565     if (org_dma_ctl & DMACTL_RUN)
0566         iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
0567 
0568     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0569         if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
0570             break;
0571     }
0572 
0573     iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
0574     if (org_dma_ctl & DMACTL_RUN)
0575         iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
0576 }
0577 
0578 /*
0579  * Description:
0580  *      Set the chip with current rx descriptor address
0581  *
0582  * Parameters:
0583  *  In:
0584  *      io_base        - Base Address for MAC
0585  *      curr_desc_addr  - Descriptor Address
0586  *  Out:
0587  *      none
0588  *
0589  * Return Value: none
0590  *
0591  */
0592 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
0593 {
0594     void __iomem *io_base = priv->port_offset;
0595     unsigned short ww;
0596     unsigned char org_dma_ctl;
0597 
0598     org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
0599     if (org_dma_ctl & DMACTL_RUN)
0600         iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
0601 
0602     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0603         if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
0604             break;
0605     }
0606 
0607     iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
0608     if (org_dma_ctl & DMACTL_RUN)
0609         iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
0610 }
0611 
0612 /*
0613  * Description:
0614  *      Set the chip with current tx0 descriptor address
0615  *
0616  * Parameters:
0617  *  In:
0618  *      io_base        - Base Address for MAC
0619  *      curr_desc_addr  - Descriptor Address
0620  *  Out:
0621  *      none
0622  *
0623  * Return Value: none
0624  *
0625  */
0626 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
0627                   u32 curr_desc_addr)
0628 {
0629     void __iomem *io_base = priv->port_offset;
0630     unsigned short ww;
0631     unsigned char org_dma_ctl;
0632 
0633     org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
0634     if (org_dma_ctl & DMACTL_RUN)
0635         iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
0636 
0637     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0638         if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
0639             break;
0640     }
0641 
0642     iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
0643     if (org_dma_ctl & DMACTL_RUN)
0644         iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
0645 }
0646 
0647 /*
0648  * Description:
0649  *      Set the chip with current AC0 descriptor address
0650  *
0651  * Parameters:
0652  *  In:
0653  *      io_base        - Base Address for MAC
0654  *      curr_desc_addr  - Descriptor Address
0655  *  Out:
0656  *      none
0657  *
0658  * Return Value: none
0659  *
0660  */
0661 /* TxDMA1 = AC0DMA */
0662 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
0663                   u32 curr_desc_addr)
0664 {
0665     void __iomem *io_base = priv->port_offset;
0666     unsigned short ww;
0667     unsigned char org_dma_ctl;
0668 
0669     org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
0670     if (org_dma_ctl & DMACTL_RUN)
0671         iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
0672 
0673     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0674         if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
0675             break;
0676     }
0677     if (ww == W_MAX_TIMEOUT)
0678         pr_debug(" DBG_PORT80(0x26)\n");
0679     iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
0680     if (org_dma_ctl & DMACTL_RUN)
0681         iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
0682 }
0683 
0684 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
0685                u32 curr_desc_addr)
0686 {
0687     if (iTxType == TYPE_AC0DMA)
0688         MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
0689     else if (iTxType == TYPE_TXDMA0)
0690         MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
0691 }
0692 
0693 /*
0694  * Description:
0695  *      Micro Second Delay via MAC
0696  *
0697  * Parameters:
0698  *  In:
0699  *      io_base    - Base Address for MAC
0700  *      uDelay      - Delay time (timer resolution is 4 us)
0701  *  Out:
0702  *      none
0703  *
0704  * Return Value: none
0705  *
0706  */
0707 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
0708 {
0709     void __iomem *io_base = priv->port_offset;
0710     unsigned char byValue;
0711     unsigned int uu, ii;
0712 
0713     iowrite8(0, io_base + MAC_REG_TMCTL0);
0714     iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
0715     iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
0716     for (ii = 0; ii < 66; ii++) {  /* assume max PCI clock is 66Mhz */
0717         for (uu = 0; uu < uDelay; uu++) {
0718             byValue = ioread8(io_base + MAC_REG_TMCTL0);
0719             if ((byValue == 0) ||
0720                 (byValue & TMCTL_TSUSP)) {
0721                 iowrite8(0, io_base + MAC_REG_TMCTL0);
0722                 return;
0723             }
0724         }
0725     }
0726     iowrite8(0, io_base + MAC_REG_TMCTL0);
0727 }
0728 
0729 /*
0730  * Description:
0731  *      Micro Second One shot timer via MAC
0732  *
0733  * Parameters:
0734  *  In:
0735  *      io_base    - Base Address for MAC
0736  *      uDelay      - Delay time
0737  *  Out:
0738  *      none
0739  *
0740  * Return Value: none
0741  *
0742  */
0743 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
0744                    unsigned int uDelayTime)
0745 {
0746     void __iomem *io_base = priv->port_offset;
0747 
0748     iowrite8(0, io_base + MAC_REG_TMCTL1);
0749     iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
0750     iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
0751 }
0752 
0753 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
0754              u32 data)
0755 {
0756     void __iomem *io_base = priv->port_offset;
0757 
0758     if (offset > 273)
0759         return;
0760     iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
0761     iowrite32(data, io_base + MAC_REG_MISCFFDATA);
0762     iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
0763 }
0764 
0765 bool MACbPSWakeup(struct vnt_private *priv)
0766 {
0767     void __iomem *io_base = priv->port_offset;
0768     unsigned int ww;
0769     /* Read PSCTL */
0770     if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
0771         return true;
0772 
0773     /* Disable PS */
0774     vt6655_mac_reg_bits_off(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
0775 
0776     /* Check if SyncFlushOK */
0777     for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
0778         if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
0779             break;
0780     }
0781     if (ww == W_MAX_TIMEOUT) {
0782         pr_debug(" DBG_PORT80(0x33)\n");
0783         return false;
0784     }
0785     return true;
0786 }
0787 
0788 /*
0789  * Description:
0790  *      Set the Key by MISCFIFO
0791  *
0792  * Parameters:
0793  *  In:
0794  *      io_base        - Base Address for MAC
0795  *
0796  *  Out:
0797  *      none
0798  *
0799  * Return Value: none
0800  *
0801  */
0802 
0803 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
0804              unsigned int uEntryIdx, unsigned int uKeyIdx,
0805              unsigned char *pbyAddr, u32 *pdwKey,
0806              unsigned char local_id)
0807 {
0808     void __iomem *io_base = priv->port_offset;
0809     unsigned short offset;
0810     u32 data;
0811     int     ii;
0812 
0813     if (local_id <= 1)
0814         return;
0815 
0816     offset = MISCFIFO_KEYETRY0;
0817     offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
0818 
0819     data = 0;
0820     data |= wKeyCtl;
0821     data <<= 16;
0822     data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
0823     pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
0824          offset, data, wKeyCtl);
0825 
0826     iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
0827     iowrite32(data, io_base + MAC_REG_MISCFFDATA);
0828     iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
0829     offset++;
0830 
0831     data = 0;
0832     data |= *(pbyAddr + 3);
0833     data <<= 8;
0834     data |= *(pbyAddr + 2);
0835     data <<= 8;
0836     data |= *(pbyAddr + 1);
0837     data <<= 8;
0838     data |= *pbyAddr;
0839     pr_debug("2. offset: %d, Data: %X\n", offset, data);
0840 
0841     iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
0842     iowrite32(data, io_base + MAC_REG_MISCFFDATA);
0843     iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
0844     offset++;
0845 
0846     offset += (uKeyIdx * 4);
0847     for (ii = 0; ii < 4; ii++) {
0848         /* always push 128 bits */
0849         pr_debug("3.(%d) offset: %d, Data: %X\n",
0850              ii, offset + ii, *pdwKey);
0851         iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
0852         iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
0853         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
0854     }
0855 }
0856 
0857 /*
0858  * Description:
0859  *      Disable the Key Entry by MISCFIFO
0860  *
0861  * Parameters:
0862  *  In:
0863  *      io_base        - Base Address for MAC
0864  *
0865  *  Out:
0866  *      none
0867  *
0868  * Return Value: none
0869  *
0870  */
0871 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
0872 {
0873     void __iomem *io_base = priv->port_offset;
0874     unsigned short offset;
0875 
0876     offset = MISCFIFO_KEYETRY0;
0877     offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
0878 
0879     iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
0880     iowrite32(0, io_base + MAC_REG_MISCFFDATA);
0881     iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
0882 }
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