staging/rts5208/xd.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Driver for Realtek PCI-Express card reader
0004  *
0005  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0006  *
0007  * Author:
0008  *   Wei WANG (wei_wang@realsil.com.cn)
0009  *   Micky Ching (micky_ching@realsil.com.cn)
0010  */
0011
0012 #ifndef __REALTEK_RTSX_XD_H
0013 #define __REALTEK_RTSX_XD_H
0014
0015 #define XD_DELAY_WRITE
0016
0017 /* Error Codes */
0018 #define XD_NO_ERROR         0x00
0019 #define XD_NO_MEMORY            0x80
0020 #define XD_PRG_ERROR            0x40
0021 #define XD_NO_CARD          0x20
0022 #define XD_READ_FAIL            0x10
0023 #define XD_ERASE_FAIL           0x08
0024 #define XD_WRITE_FAIL           0x04
0025 #define XD_ECC_ERROR            0x02
0026 #define XD_TO_ERROR         0x01
0027
0028 /* XD Commands */
0029 #define READ1_1             0x00
0030 #define READ1_2             0x01
0031 #define READ2               0x50
0032 #define READ_ID             0x90
0033 #define RESET               0xff
0034 #define PAGE_PRG_1          0x80
0035 #define PAGE_PRG_2          0x10
0036 #define BLK_ERASE_1         0x60
0037 #define BLK_ERASE_2         0xD0
0038 #define READ_STS            0x70
0039 #define READ_XD_ID          0x9A
0040 #define COPY_BACK_512           0x8A
0041 #define COPY_BACK_2K            0x85
0042 #define READ1_1_2           0x30
0043 #define READ1_1_3           0x35
0044 #define CHG_DAT_OUT_1           0x05
0045 #define RDM_DAT_OUT_1           0x05
0046 #define CHG_DAT_OUT_2           0xE0
0047 #define RDM_DAT_OUT_2           0xE0
0048 #define CHG_DAT_OUT_2           0xE0
0049 #define CHG_DAT_IN_1            0x85
0050 #define CACHE_PRG           0x15
0051
0052 /* Redundant Area Related */
0053 #define XD_EXTRA_SIZE           0x10
0054 #define XD_2K_EXTRA_SIZE        0x40
0055
0056 #define NOT_WRITE_PROTECTED     0x80
0057 #define READY_STATE         0x40
0058 #define PROGRAM_ERROR           0x01
0059 #define PROGRAM_ERROR_N_1       0x02
0060 #define INTERNAL_READY          0x20
0061 #define READY_FLAG          0x5F
0062
0063 #define XD_8M_X8_512            0xE6
0064 #define XD_16M_X8_512           0x73
0065 #define XD_32M_X8_512           0x75
0066 #define XD_64M_X8_512           0x76
0067 #define XD_128M_X8_512          0x79
0068 #define XD_256M_X8_512          0x71
0069 #define XD_128M_X8_2048         0xF1
0070 #define XD_256M_X8_2048         0xDA
0071 #define XD_512M_X8          0xDC
0072 #define XD_128M_X16_2048        0xC1
0073 #define XD_4M_X8_512_1          0xE3
0074 #define XD_4M_X8_512_2          0xE5
0075 #define XD_1G_X8_512            0xD3
0076 #define XD_2G_X8_512            0xD5
0077
0078 #define XD_ID_CODE          0xB5
0079
0080 #define VENDOR_BLOCK            0xEFFF
0081 #define CIS_BLOCK           0xDFFF
0082
0083 #define BLK_NOT_FOUND           0xFFFFFFFF
0084
0085 #define NO_NEW_BLK          0xFFFFFFFF
0086
0087 #define PAGE_CORRECTABLE        0x0
0088 #define PAGE_NOTCORRECTABLE     0x1
0089
0090 #define NO_OFFSET           0x0
0091 #define WITH_OFFSET         0x1
0092
0093 #define SECT_PER_PAGE           4
0094 #define XD_ADDR_MODE_2C         XD_ADDR_MODE_2A
0095
0096 #define ZONE0_BAD_BLOCK         23
0097 #define NOT_ZONE0_BAD_BLOCK     24
0098
0099 #define XD_RW_ADDR          0x01
0100 #define XD_ERASE_ADDR           0x02
0101
0102 #define XD_PAGE_512(xd_card)        \
0103 do {                    \
0104     (xd_card)->block_shift = 5; \
0105     (xd_card)->page_off = 0x1F; \
0106 } while (0)
0107
0108 #define XD_SET_BAD_NEWBLK(xd_card)  ((xd_card)->multi_flag |= 0x01)
0109 #define XD_CLR_BAD_NEWBLK(xd_card)  ((xd_card)->multi_flag &= ~0x01)
0110 #define XD_CHK_BAD_NEWBLK(xd_card)  ((xd_card)->multi_flag & 0x01)
0111
0112 #define XD_SET_BAD_OLDBLK(xd_card)  ((xd_card)->multi_flag |= 0x02)
0113 #define XD_CLR_BAD_OLDBLK(xd_card)  ((xd_card)->multi_flag &= ~0x02)
0114 #define XD_CHK_BAD_OLDBLK(xd_card)  ((xd_card)->multi_flag & 0x02)
0115
0116 #define XD_SET_MBR_FAIL(xd_card)    ((xd_card)->multi_flag |= 0x04)
0117 #define XD_CLR_MBR_FAIL(xd_card)    ((xd_card)->multi_flag &= ~0x04)
0118 #define XD_CHK_MBR_FAIL(xd_card)    ((xd_card)->multi_flag & 0x04)
0119
0120 #define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08)
0121 #define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08)
0122 #define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08)
0123
0124 #define XD_SET_4MB(xd_card)     ((xd_card)->multi_flag |= 0x10)
0125 #define XD_CLR_4MB(xd_card)     ((xd_card)->multi_flag &= ~0x10)
0126 #define XD_CHK_4MB(xd_card)     ((xd_card)->multi_flag & 0x10)
0127
0128 #define XD_SET_ECC_ERR(xd_card)     ((xd_card)->multi_flag |= 0x40)
0129 #define XD_CLR_ECC_ERR(xd_card)     ((xd_card)->multi_flag &= ~0x40)
0130 #define XD_CHK_ECC_ERR(xd_card)     ((xd_card)->multi_flag & 0x40)
0131
0132 #define PAGE_STATUS     0
0133 #define BLOCK_STATUS        1
0134 #define BLOCK_ADDR1_L       2
0135 #define BLOCK_ADDR1_H       3
0136 #define BLOCK_ADDR2_L       4
0137 #define BLOCK_ADDR2_H       5
0138 #define RESERVED0       6
0139 #define RESERVED1       7
0140 #define RESERVED2       8
0141 #define RESERVED3       9
0142 #define PARITY          10
0143
0144 #define CIS0_0          0
0145 #define CIS0_1          1
0146 #define CIS0_2          2
0147 #define CIS0_3          3
0148 #define CIS0_4          4
0149 #define CIS0_5          5
0150 #define CIS0_6          6
0151 #define CIS0_7          7
0152 #define CIS0_8          8
0153 #define CIS0_9          9
0154 #define CIS1_0          256
0155 #define CIS1_1          (256 + 1)
0156 #define CIS1_2          (256 + 2)
0157 #define CIS1_3          (256 + 3)
0158 #define CIS1_4          (256 + 4)
0159 #define CIS1_5          (256 + 5)
0160 #define CIS1_6          (256 + 6)
0161 #define CIS1_7          (256 + 7)
0162 #define CIS1_8          (256 + 8)
0163 #define CIS1_9          (256 + 9)
0164
0165 int reset_xd_card(struct rtsx_chip *chip);
0166 #ifdef XD_DELAY_WRITE
0167 int xd_delay_write(struct rtsx_chip *chip);
0168 #endif
0169 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
0170       u32 start_sector, u16 sector_cnt);
0171 void xd_free_l2p_tbl(struct rtsx_chip *chip);
0172 void xd_cleanup_work(struct rtsx_chip *chip);
0173 int xd_power_off_card3v3(struct rtsx_chip *chip);
0174 int release_xd_card(struct rtsx_chip *chip);
0175
0176 #endif  /* __REALTEK_RTSX_XD_H */