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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for Realtek PCI-Express card reader
0004  *
0005  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0006  *
0007  * Author:
0008  *   Wei WANG (wei_wang@realsil.com.cn)
0009  *   Micky Ching (micky_ching@realsil.com.cn)
0010  */
0011 
0012 #include <linux/blkdev.h>
0013 #include <linux/kthread.h>
0014 #include <linux/sched.h>
0015 #include <linux/vmalloc.h>
0016 
0017 #include "rtsx.h"
0018 #include "rtsx_transport.h"
0019 #include "rtsx_scsi.h"
0020 #include "rtsx_card.h"
0021 #include "xd.h"
0022 
0023 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
0024 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff,
0025             u8 start_page, u8 end_page);
0026 
0027 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
0028 {
0029     struct xd_info *xd_card = &chip->xd_card;
0030 
0031     xd_card->err_code = err_code;
0032 }
0033 
0034 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
0035 {
0036     struct xd_info *xd_card = &chip->xd_card;
0037 
0038     return (xd_card->err_code == err_code);
0039 }
0040 
0041 static int xd_set_init_para(struct rtsx_chip *chip)
0042 {
0043     struct xd_info *xd_card = &chip->xd_card;
0044     int retval;
0045 
0046     if (chip->asic_code)
0047         xd_card->xd_clock = 47;
0048     else
0049         xd_card->xd_clock = CLK_50;
0050 
0051     retval = switch_clock(chip, xd_card->xd_clock);
0052     if (retval != STATUS_SUCCESS)
0053         return STATUS_FAIL;
0054 
0055     return STATUS_SUCCESS;
0056 }
0057 
0058 static int xd_switch_clock(struct rtsx_chip *chip)
0059 {
0060     struct xd_info *xd_card = &chip->xd_card;
0061     int retval;
0062 
0063     retval = select_card(chip, XD_CARD);
0064     if (retval != STATUS_SUCCESS)
0065         return STATUS_FAIL;
0066 
0067     retval = switch_clock(chip, xd_card->xd_clock);
0068     if (retval != STATUS_SUCCESS)
0069         return STATUS_FAIL;
0070 
0071     return STATUS_SUCCESS;
0072 }
0073 
0074 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
0075 {
0076     int retval, i;
0077     u8 *ptr;
0078 
0079     rtsx_init_cmd(chip);
0080 
0081     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
0082     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
0083              XD_TRANSFER_START | XD_READ_ID);
0084     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
0085              XD_TRANSFER_END);
0086 
0087     for (i = 0; i < 4; i++)
0088         rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
0089 
0090     retval = rtsx_send_cmd(chip, XD_CARD, 20);
0091     if (retval < 0)
0092         return STATUS_FAIL;
0093 
0094     ptr = rtsx_get_cmd_data(chip) + 1;
0095     if (id_buf && buf_len) {
0096         if (buf_len > 4)
0097             buf_len = 4;
0098         memcpy(id_buf, ptr, buf_len);
0099     }
0100 
0101     return STATUS_SUCCESS;
0102 }
0103 
0104 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
0105 {
0106     struct xd_info *xd_card = &chip->xd_card;
0107 
0108     switch (mode) {
0109     case XD_RW_ADDR:
0110         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
0111         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
0112         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
0113                  0xFF, (u8)(addr >> 8));
0114         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3,
0115                  0xFF, (u8)(addr >> 16));
0116         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
0117                  xd_card->addr_cycle |
0118                  XD_CALC_ECC |
0119                  XD_BA_NO_TRANSFORM);
0120         break;
0121 
0122     case XD_ERASE_ADDR:
0123         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
0124         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1,
0125                  0xFF, (u8)(addr >> 8));
0126         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
0127                  0xFF, (u8)(addr >> 16));
0128         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
0129                  (xd_card->addr_cycle - 1) | XD_CALC_ECC |
0130             XD_BA_NO_TRANSFORM);
0131         break;
0132 
0133     default:
0134         break;
0135     }
0136 }
0137 
0138 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr,
0139                  u8 *buf, int buf_len)
0140 {
0141     int retval, i;
0142 
0143     rtsx_init_cmd(chip);
0144 
0145     xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
0146 
0147     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
0148              0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
0149     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
0150              XD_TRANSFER_END, XD_TRANSFER_END);
0151 
0152     for (i = 0; i < 6; i++)
0153         rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i),
0154                  0, 0);
0155     for (i = 0; i < 4; i++)
0156         rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i),
0157                  0, 0);
0158     rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
0159 
0160     retval = rtsx_send_cmd(chip, XD_CARD, 500);
0161     if (retval < 0)
0162         return STATUS_FAIL;
0163 
0164     if (buf && buf_len) {
0165         u8 *ptr = rtsx_get_cmd_data(chip) + 1;
0166 
0167         if (buf_len > 11)
0168             buf_len = 11;
0169         memcpy(buf, ptr, buf_len);
0170     }
0171 
0172     return STATUS_SUCCESS;
0173 }
0174 
0175 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset,
0176                  u8 *buf, int buf_len)
0177 {
0178     int retval, i;
0179 
0180     if (!buf || buf_len < 0)
0181         return STATUS_FAIL;
0182 
0183     rtsx_init_cmd(chip);
0184 
0185     for (i = 0; i < buf_len; i++)
0186         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i,
0187                  0, 0);
0188 
0189     retval = rtsx_send_cmd(chip, 0, 250);
0190     if (retval < 0) {
0191         rtsx_clear_xd_error(chip);
0192         return STATUS_FAIL;
0193     }
0194 
0195     memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
0196 
0197     return STATUS_SUCCESS;
0198 }
0199 
0200 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf,
0201                int buf_len)
0202 {
0203     int retval;
0204     u8 reg;
0205 
0206     if (!buf || buf_len < 10)
0207         return STATUS_FAIL;
0208 
0209     rtsx_init_cmd(chip);
0210 
0211     xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
0212 
0213     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
0214              0x01, PINGPONG_BUFFER);
0215     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
0216     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
0217              XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
0218 
0219     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
0220              XD_TRANSFER_START | XD_READ_PAGES);
0221     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
0222              XD_TRANSFER_END);
0223 
0224     retval = rtsx_send_cmd(chip, XD_CARD, 250);
0225     if (retval == -ETIMEDOUT) {
0226         rtsx_clear_xd_error(chip);
0227         return STATUS_FAIL;
0228     }
0229 
0230     retval = rtsx_read_register(chip, XD_PAGE_STATUS, &reg);
0231     if (retval)
0232         return retval;
0233     if (reg != XD_GPG) {
0234         rtsx_clear_xd_error(chip);
0235         return STATUS_FAIL;
0236     }
0237 
0238     retval = rtsx_read_register(chip, XD_CTL, &reg);
0239     if (retval)
0240         return retval;
0241     if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
0242         retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
0243         if (retval != STATUS_SUCCESS)
0244             return STATUS_FAIL;
0245         if (reg & XD_ECC1_ERROR) {
0246             u8 ecc_bit, ecc_byte;
0247 
0248             retval = rtsx_read_register(chip, XD_ECC_BIT1,
0249                             &ecc_bit);
0250             if (retval)
0251                 return retval;
0252             retval = rtsx_read_register(chip, XD_ECC_BYTE1,
0253                             &ecc_byte);
0254             if (retval)
0255                 return retval;
0256 
0257             dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
0258                 ecc_bit, ecc_byte);
0259             if (ecc_byte < buf_len) {
0260                 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
0261                     buf[ecc_byte]);
0262                 buf[ecc_byte] ^= (1 << ecc_bit);
0263                 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
0264                     buf[ecc_byte]);
0265             }
0266         }
0267     } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
0268         rtsx_clear_xd_error(chip);
0269 
0270         retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
0271         if (retval != STATUS_SUCCESS)
0272             return STATUS_FAIL;
0273         if (reg & XD_ECC2_ERROR) {
0274             u8 ecc_bit, ecc_byte;
0275 
0276             retval = rtsx_read_register(chip, XD_ECC_BIT2,
0277                             &ecc_bit);
0278             if (retval)
0279                 return retval;
0280             retval = rtsx_read_register(chip, XD_ECC_BYTE2,
0281                             &ecc_byte);
0282             if (retval)
0283                 return retval;
0284 
0285             dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
0286                 ecc_bit, ecc_byte);
0287             if (ecc_byte < buf_len) {
0288                 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
0289                     buf[ecc_byte]);
0290                 buf[ecc_byte] ^= (1 << ecc_bit);
0291                 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
0292                     buf[ecc_byte]);
0293             }
0294         }
0295     } else {
0296         rtsx_clear_xd_error(chip);
0297         return STATUS_FAIL;
0298     }
0299 
0300     return STATUS_SUCCESS;
0301 }
0302 
0303 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
0304 {
0305     if (CHECK_PID(chip, 0x5208)) {
0306         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
0307                  XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
0308         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
0309                  XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
0310         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
0311                  XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
0312         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
0313                  XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
0314         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
0315                  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
0316         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
0317                  MS_D5_PD | MS_D4_PD);
0318     } else if (CHECK_PID(chip, 0x5288)) {
0319         if (CHECK_BARO_PKG(chip, QFN)) {
0320             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
0321                      0xFF, 0x55);
0322             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
0323                      0xFF, 0x55);
0324             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
0325                      0xFF, 0x4B);
0326             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
0327                      0xFF, 0x69);
0328         }
0329     }
0330 }
0331 
0332 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
0333 {
0334     if (CHECK_BARO_PKG(chip, QFN)) {
0335         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
0336         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
0337         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
0338         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
0339     }
0340 }
0341 
0342 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
0343 {
0344     if (CHECK_PID(chip, 0x5208)) {
0345         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
0346                  XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
0347         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
0348                  XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
0349         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
0350                  XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
0351         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
0352                  XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
0353         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
0354                  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
0355         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
0356                  MS_D5_PD | MS_D4_PD);
0357     } else if (CHECK_PID(chip, 0x5288)) {
0358         if (CHECK_BARO_PKG(chip, QFN)) {
0359             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
0360                      0xFF, 0x55);
0361             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
0362                      0xFF, 0x55);
0363             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
0364                      0xFF, 0x53);
0365             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
0366                      0xFF, 0xA9);
0367         }
0368     }
0369 }
0370 
0371 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
0372 {
0373     int retval;
0374 
0375     if (CHECK_PID(chip, 0x5208)) {
0376         retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
0377                          XD_D3_PD |
0378                          XD_D2_PD |
0379                          XD_D1_PD |
0380                          XD_D0_PD);
0381         if (retval)
0382             return retval;
0383         retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
0384                          XD_D7_PD |
0385                          XD_D6_PD |
0386                          XD_D5_PD |
0387                          XD_D4_PD);
0388         if (retval)
0389             return retval;
0390         retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
0391                          XD_WP_PD |
0392                          XD_CE_PD |
0393                          XD_CLE_PD |
0394                          XD_CD_PU);
0395         if (retval)
0396             return retval;
0397         retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
0398                          XD_RDY_PD |
0399                          XD_WE_PD |
0400                          XD_RE_PD |
0401                          XD_ALE_PD);
0402         if (retval)
0403             return retval;
0404         retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
0405                          MS_INS_PU |
0406                          SD_WP_PD |
0407                          SD_CD_PU |
0408                          SD_CMD_PD);
0409         if (retval)
0410             return retval;
0411         retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
0412                          MS_D5_PD | MS_D4_PD);
0413         if (retval)
0414             return retval;
0415     } else if (CHECK_PID(chip, 0x5288)) {
0416         if (CHECK_BARO_PKG(chip, QFN)) {
0417             retval = rtsx_write_register(chip, CARD_PULL_CTL1,
0418                              0xFF, 0x55);
0419             if (retval)
0420                 return retval;
0421             retval = rtsx_write_register(chip, CARD_PULL_CTL2,
0422                              0xFF, 0x55);
0423             if (retval)
0424                 return retval;
0425             retval = rtsx_write_register(chip, CARD_PULL_CTL3,
0426                              0xFF, 0x4B);
0427             if (retval)
0428                 return retval;
0429             retval = rtsx_write_register(chip, CARD_PULL_CTL4,
0430                              0xFF, 0x69);
0431             if (retval)
0432                 return retval;
0433         }
0434     }
0435 
0436     return STATUS_SUCCESS;
0437 }
0438 
0439 static int reset_xd(struct rtsx_chip *chip)
0440 {
0441     struct xd_info *xd_card = &chip->xd_card;
0442     int retval, i, j;
0443     u8 *ptr, id_buf[4], redunt[11];
0444 
0445     retval = select_card(chip, XD_CARD);
0446     if (retval != STATUS_SUCCESS)
0447         return STATUS_FAIL;
0448 
0449     rtsx_init_cmd(chip);
0450 
0451     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
0452              XD_PGSTS_NOT_FF);
0453     if (chip->asic_code) {
0454         if (!CHECK_PID(chip, 0x5288))
0455             xd_fill_pull_ctl_disable(chip);
0456         else
0457             xd_fill_pull_ctl_stage1_barossa(chip);
0458     } else {
0459         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
0460                  (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) |
0461                  0x20);
0462     }
0463 
0464     if (!chip->ft2_fast_mode)
0465         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT,
0466                  XD_NO_AUTO_PWR_OFF, 0);
0467 
0468     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
0469 
0470     retval = rtsx_send_cmd(chip, XD_CARD, 100);
0471     if (retval < 0)
0472         return STATUS_FAIL;
0473 
0474     if (!chip->ft2_fast_mode) {
0475         retval = card_power_off(chip, XD_CARD);
0476         if (retval != STATUS_SUCCESS)
0477             return STATUS_FAIL;
0478 
0479         wait_timeout(250);
0480 
0481         rtsx_init_cmd(chip);
0482 
0483         if (chip->asic_code) {
0484             xd_fill_pull_ctl_enable(chip);
0485         } else {
0486             rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
0487                      (FPGA_XD_PULL_CTL_EN1 &
0488                       FPGA_XD_PULL_CTL_EN2) |
0489                      0x20);
0490         }
0491 
0492         retval = rtsx_send_cmd(chip, XD_CARD, 100);
0493         if (retval < 0)
0494             return STATUS_FAIL;
0495 
0496         retval = card_power_on(chip, XD_CARD);
0497         if (retval != STATUS_SUCCESS)
0498             return STATUS_FAIL;
0499 
0500 #ifdef SUPPORT_OCP
0501         wait_timeout(50);
0502         if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
0503             dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
0504                 chip->ocp_stat);
0505             return STATUS_FAIL;
0506         }
0507 #endif
0508     }
0509 
0510     rtsx_init_cmd(chip);
0511 
0512     if (chip->ft2_fast_mode) {
0513         if (chip->asic_code) {
0514             xd_fill_pull_ctl_enable(chip);
0515         } else {
0516             rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
0517                      (FPGA_XD_PULL_CTL_EN1 &
0518                       FPGA_XD_PULL_CTL_EN2) |
0519                      0x20);
0520         }
0521     }
0522 
0523     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
0524     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
0525 
0526     retval = rtsx_send_cmd(chip, XD_CARD, 100);
0527     if (retval < 0)
0528         return STATUS_FAIL;
0529 
0530     if (!chip->ft2_fast_mode)
0531         wait_timeout(200);
0532 
0533     retval = xd_set_init_para(chip);
0534     if (retval != STATUS_SUCCESS)
0535         return STATUS_FAIL;
0536 
0537     /* Read ID to check if the timing setting is right */
0538     for (i = 0; i < 4; i++) {
0539         rtsx_init_cmd(chip);
0540 
0541         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
0542                  XD_TIME_SETUP_STEP * 3 +
0543                  XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
0544         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
0545                  XD_TIME_SETUP_STEP * 3 +
0546                  XD_TIME_RW_STEP * (4 + i) +
0547                  XD_TIME_RWN_STEP * (3 + i));
0548 
0549         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
0550                  XD_TRANSFER_START | XD_RESET);
0551         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
0552                  XD_TRANSFER_END, XD_TRANSFER_END);
0553 
0554         rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
0555         rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
0556 
0557         retval = rtsx_send_cmd(chip, XD_CARD, 100);
0558         if (retval < 0)
0559             return STATUS_FAIL;
0560 
0561         ptr = rtsx_get_cmd_data(chip) + 1;
0562 
0563         dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n",
0564             ptr[0], ptr[1]);
0565 
0566         if (((ptr[0] & READY_FLAG) != READY_STATE) ||
0567             !(ptr[1] & XD_RDY))
0568             continue;
0569 
0570         retval = xd_read_id(chip, READ_ID, id_buf, 4);
0571         if (retval != STATUS_SUCCESS)
0572             return STATUS_FAIL;
0573 
0574         dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
0575             id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
0576 
0577         xd_card->device_code = id_buf[1];
0578 
0579         /* Check if the xD card is supported */
0580         switch (xd_card->device_code) {
0581         case XD_4M_X8_512_1:
0582         case XD_4M_X8_512_2:
0583             xd_card->block_shift = 4;
0584             xd_card->page_off = 0x0F;
0585             xd_card->addr_cycle = 3;
0586             xd_card->zone_cnt = 1;
0587             xd_card->capacity = 8000;
0588             XD_SET_4MB(xd_card);
0589             break;
0590         case XD_8M_X8_512:
0591             xd_card->block_shift = 4;
0592             xd_card->page_off = 0x0F;
0593             xd_card->addr_cycle = 3;
0594             xd_card->zone_cnt = 1;
0595             xd_card->capacity = 16000;
0596             break;
0597         case XD_16M_X8_512:
0598             XD_PAGE_512(xd_card);
0599             xd_card->addr_cycle = 3;
0600             xd_card->zone_cnt = 1;
0601             xd_card->capacity = 32000;
0602             break;
0603         case XD_32M_X8_512:
0604             XD_PAGE_512(xd_card);
0605             xd_card->addr_cycle = 3;
0606             xd_card->zone_cnt = 2;
0607             xd_card->capacity = 64000;
0608             break;
0609         case XD_64M_X8_512:
0610             XD_PAGE_512(xd_card);
0611             xd_card->addr_cycle = 4;
0612             xd_card->zone_cnt = 4;
0613             xd_card->capacity = 128000;
0614             break;
0615         case XD_128M_X8_512:
0616             XD_PAGE_512(xd_card);
0617             xd_card->addr_cycle = 4;
0618             xd_card->zone_cnt = 8;
0619             xd_card->capacity = 256000;
0620             break;
0621         case XD_256M_X8_512:
0622             XD_PAGE_512(xd_card);
0623             xd_card->addr_cycle = 4;
0624             xd_card->zone_cnt = 16;
0625             xd_card->capacity = 512000;
0626             break;
0627         case XD_512M_X8:
0628             XD_PAGE_512(xd_card);
0629             xd_card->addr_cycle = 4;
0630             xd_card->zone_cnt = 32;
0631             xd_card->capacity = 1024000;
0632             break;
0633         case XD_1G_X8_512:
0634             XD_PAGE_512(xd_card);
0635             xd_card->addr_cycle = 4;
0636             xd_card->zone_cnt = 64;
0637             xd_card->capacity = 2048000;
0638             break;
0639         case XD_2G_X8_512:
0640             XD_PAGE_512(xd_card);
0641             xd_card->addr_cycle = 4;
0642             xd_card->zone_cnt = 128;
0643             xd_card->capacity = 4096000;
0644             break;
0645         default:
0646             continue;
0647         }
0648 
0649         /* Confirm timing setting */
0650         for (j = 0; j < 10; j++) {
0651             retval = xd_read_id(chip, READ_ID, id_buf, 4);
0652             if (retval != STATUS_SUCCESS)
0653                 return STATUS_FAIL;
0654 
0655             if (id_buf[1] != xd_card->device_code)
0656                 break;
0657         }
0658 
0659         if (j == 10)
0660             break;
0661     }
0662 
0663     if (i == 4) {
0664         xd_card->block_shift = 0;
0665         xd_card->page_off = 0;
0666         xd_card->addr_cycle = 0;
0667         xd_card->capacity = 0;
0668 
0669         return STATUS_FAIL;
0670     }
0671 
0672     retval = xd_read_id(chip, READ_XD_ID, id_buf, 4);
0673     if (retval != STATUS_SUCCESS)
0674         return STATUS_FAIL;
0675     dev_dbg(rtsx_dev(chip), "READ_XD_ID: 0x%x 0x%x 0x%x 0x%x\n",
0676         id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
0677     if (id_buf[2] != XD_ID_CODE)
0678         return STATUS_FAIL;
0679 
0680     /* Search CIS block */
0681     for (i = 0; i < 24; i++) {
0682         u32 page_addr;
0683 
0684         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS)
0685             return STATUS_FAIL;
0686 
0687         page_addr = (u32)i << xd_card->block_shift;
0688 
0689         for (j = 0; j < 3; j++) {
0690             retval = xd_read_redundant(chip, page_addr, redunt, 11);
0691             if (retval == STATUS_SUCCESS)
0692                 break;
0693         }
0694         if (j == 3)
0695             continue;
0696 
0697         if (redunt[BLOCK_STATUS] != XD_GBLK)
0698             continue;
0699 
0700         j = 0;
0701         if (redunt[PAGE_STATUS] != XD_GPG) {
0702             for (j = 1; j <= 8; j++) {
0703                 retval = xd_read_redundant(chip, page_addr + j,
0704                                redunt, 11);
0705                 if (retval == STATUS_SUCCESS) {
0706                     if (redunt[PAGE_STATUS] == XD_GPG)
0707                         break;
0708                 }
0709             }
0710 
0711             if (j == 9)
0712                 break;
0713         }
0714 
0715         /* Check CIS data */
0716         if (redunt[BLOCK_STATUS] == XD_GBLK &&
0717             (redunt[PARITY] & XD_BA1_ALL0)) {
0718             u8 buf[10];
0719 
0720             page_addr += j;
0721 
0722             retval = xd_read_cis(chip, page_addr, buf, 10);
0723             if (retval != STATUS_SUCCESS)
0724                 return STATUS_FAIL;
0725 
0726             if (buf[0] == 0x01 && buf[1] == 0x03 &&
0727                 buf[2] == 0xD9 &&
0728                 buf[3] == 0x01 && buf[4] == 0xFF &&
0729                 buf[5] == 0x18 && buf[6] == 0x02 &&
0730                 buf[7] == 0xDF && buf[8] == 0x01 &&
0731                 buf[9] == 0x20) {
0732                 xd_card->cis_block = (u16)i;
0733             }
0734         }
0735 
0736         break;
0737     }
0738 
0739     dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block);
0740     if (xd_card->cis_block == 0xFFFF)
0741         return STATUS_FAIL;
0742 
0743     chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
0744 
0745     return STATUS_SUCCESS;
0746 }
0747 
0748 static int xd_check_data_blank(u8 *redunt)
0749 {
0750     int i;
0751 
0752     for (i = 0; i < 6; i++) {
0753         if (redunt[PAGE_STATUS + i] != 0xFF)
0754             return 0;
0755     }
0756 
0757     if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1))
0758         != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
0759         return 0;
0760 
0761     for (i = 0; i < 4; i++) {
0762         if (redunt[RESERVED0 + i] != 0xFF)
0763             return 0;
0764     }
0765 
0766     return 1;
0767 }
0768 
0769 static u16 xd_load_log_block_addr(u8 *redunt)
0770 {
0771     u16 addr = 0xFFFF;
0772 
0773     if (redunt[PARITY] & XD_BA1_BA2_EQL)
0774         addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
0775             redunt[BLOCK_ADDR1_L];
0776     else if (redunt[PARITY] & XD_BA1_VALID)
0777         addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
0778             redunt[BLOCK_ADDR1_L];
0779     else if (redunt[PARITY] & XD_BA2_VALID)
0780         addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) |
0781             redunt[BLOCK_ADDR2_L];
0782 
0783     return addr;
0784 }
0785 
0786 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
0787 {
0788     struct xd_info *xd_card = &chip->xd_card;
0789     int size, i;
0790 
0791     dev_dbg(rtsx_dev(chip), "%s: zone_cnt = %d\n", __func__,
0792         xd_card->zone_cnt);
0793 
0794     if (xd_card->zone_cnt < 1)
0795         return STATUS_FAIL;
0796 
0797     size = xd_card->zone_cnt * sizeof(struct zone_entry);
0798     dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size);
0799 
0800     xd_card->zone = vmalloc(size);
0801     if (!xd_card->zone)
0802         return STATUS_ERROR;
0803 
0804     for (i = 0; i < xd_card->zone_cnt; i++) {
0805         xd_card->zone[i].build_flag = 0;
0806         xd_card->zone[i].l2p_table = NULL;
0807         xd_card->zone[i].free_table = NULL;
0808         xd_card->zone[i].get_index = 0;
0809         xd_card->zone[i].set_index = 0;
0810         xd_card->zone[i].unused_blk_cnt = 0;
0811     }
0812 
0813     return STATUS_SUCCESS;
0814 }
0815 
0816 static inline void free_zone(struct zone_entry *zone)
0817 {
0818     if (!zone)
0819         return;
0820 
0821     zone->build_flag = 0;
0822     zone->set_index = 0;
0823     zone->get_index = 0;
0824     zone->unused_blk_cnt = 0;
0825     vfree(zone->l2p_table);
0826     zone->l2p_table = NULL;
0827     vfree(zone->free_table);
0828     zone->free_table = NULL;
0829 }
0830 
0831 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
0832 {
0833     struct xd_info *xd_card = &chip->xd_card;
0834     struct zone_entry *zone;
0835     int zone_no;
0836 
0837     zone_no = (int)phy_blk >> 10;
0838     if (zone_no >= xd_card->zone_cnt) {
0839         dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
0840             zone_no, xd_card->zone_cnt);
0841         return;
0842     }
0843     zone = &xd_card->zone[zone_no];
0844 
0845     if (!zone->free_table) {
0846         if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
0847             return;
0848     }
0849 
0850     if (zone->set_index >= XD_FREE_TABLE_CNT ||
0851         zone->set_index < 0) {
0852         free_zone(zone);
0853         dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n");
0854         return;
0855     }
0856 
0857     dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n",
0858         zone->set_index);
0859 
0860     zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff);
0861     if (zone->set_index >= XD_FREE_TABLE_CNT)
0862         zone->set_index = 0;
0863     zone->unused_blk_cnt++;
0864 }
0865 
0866 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
0867 {
0868     struct xd_info *xd_card = &chip->xd_card;
0869     struct zone_entry *zone;
0870     u32 phy_blk;
0871 
0872     if (zone_no >= xd_card->zone_cnt) {
0873         dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
0874             zone_no, xd_card->zone_cnt);
0875         return BLK_NOT_FOUND;
0876     }
0877     zone = &xd_card->zone[zone_no];
0878 
0879     if (zone->unused_blk_cnt == 0 ||
0880         zone->set_index == zone->get_index) {
0881         free_zone(zone);
0882         dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n");
0883         return BLK_NOT_FOUND;
0884     }
0885     if (zone->get_index >= XD_FREE_TABLE_CNT || zone->get_index < 0) {
0886         free_zone(zone);
0887         dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n");
0888         return BLK_NOT_FOUND;
0889     }
0890 
0891     dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n",
0892         zone->get_index);
0893 
0894     phy_blk = zone->free_table[zone->get_index];
0895     zone->free_table[zone->get_index++] = 0xFFFF;
0896     if (zone->get_index >= XD_FREE_TABLE_CNT)
0897         zone->get_index = 0;
0898     zone->unused_blk_cnt--;
0899 
0900     phy_blk += ((u32)(zone_no) << 10);
0901     return phy_blk;
0902 }
0903 
0904 static void xd_set_l2p_tbl(struct rtsx_chip *chip,
0905                int zone_no, u16 log_off, u16 phy_off)
0906 {
0907     struct xd_info *xd_card = &chip->xd_card;
0908     struct zone_entry *zone;
0909 
0910     zone = &xd_card->zone[zone_no];
0911     zone->l2p_table[log_off] = phy_off;
0912 }
0913 
0914 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
0915 {
0916     struct xd_info *xd_card = &chip->xd_card;
0917     struct zone_entry *zone;
0918     int retval;
0919 
0920     zone = &xd_card->zone[zone_no];
0921     if (zone->l2p_table[log_off] == 0xFFFF) {
0922         u32 phy_blk = 0;
0923         int i;
0924 
0925 #ifdef XD_DELAY_WRITE
0926         retval = xd_delay_write(chip);
0927         if (retval != STATUS_SUCCESS) {
0928             dev_dbg(rtsx_dev(chip), "In %s, delay write fail!\n",
0929                 __func__);
0930             return BLK_NOT_FOUND;
0931         }
0932 #endif
0933 
0934         if (zone->unused_blk_cnt <= 0) {
0935             dev_dbg(rtsx_dev(chip), "No unused block!\n");
0936             return BLK_NOT_FOUND;
0937         }
0938 
0939         for (i = 0; i < zone->unused_blk_cnt; i++) {
0940             phy_blk = xd_get_unused_block(chip, zone_no);
0941             if (phy_blk == BLK_NOT_FOUND) {
0942                 dev_dbg(rtsx_dev(chip), "No unused block available!\n");
0943                 return BLK_NOT_FOUND;
0944             }
0945 
0946             retval = xd_init_page(chip, phy_blk, log_off,
0947                           0, xd_card->page_off + 1);
0948             if (retval == STATUS_SUCCESS)
0949                 break;
0950         }
0951         if (i >= zone->unused_blk_cnt) {
0952             dev_dbg(rtsx_dev(chip), "No good unused block available!\n");
0953             return BLK_NOT_FOUND;
0954         }
0955 
0956         xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
0957         return phy_blk;
0958     }
0959 
0960     return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
0961 }
0962 
0963 int reset_xd_card(struct rtsx_chip *chip)
0964 {
0965     struct xd_info *xd_card = &chip->xd_card;
0966     int retval;
0967 
0968     memset(xd_card, 0, sizeof(struct xd_info));
0969 
0970     xd_card->block_shift = 0;
0971     xd_card->page_off = 0;
0972     xd_card->addr_cycle = 0;
0973     xd_card->capacity = 0;
0974     xd_card->zone_cnt = 0;
0975     xd_card->cis_block = 0xFFFF;
0976     xd_card->delay_write.delay_write_flag = 0;
0977 
0978     retval = enable_card_clock(chip, XD_CARD);
0979     if (retval != STATUS_SUCCESS)
0980         return STATUS_FAIL;
0981 
0982     retval = reset_xd(chip);
0983     if (retval != STATUS_SUCCESS)
0984         return STATUS_FAIL;
0985 
0986     retval = xd_init_l2p_tbl(chip);
0987     if (retval != STATUS_SUCCESS)
0988         return STATUS_FAIL;
0989 
0990     return STATUS_SUCCESS;
0991 }
0992 
0993 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
0994 {
0995     struct xd_info *xd_card = &chip->xd_card;
0996     int retval;
0997     u32 page_addr;
0998     u8 reg = 0;
0999 
1000     dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk);
1001 
1002     if (phy_blk == BLK_NOT_FOUND)
1003         return STATUS_FAIL;
1004 
1005     rtsx_init_cmd(chip);
1006 
1007     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1008     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
1009     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
1010     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
1011     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
1012     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
1013     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
1014     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1015     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1016     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1017 
1018     page_addr = phy_blk << xd_card->block_shift;
1019 
1020     xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1021 
1022     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1023              xd_card->page_off + 1);
1024 
1025     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1026              XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1027     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1028              XD_TRANSFER_END, XD_TRANSFER_END);
1029 
1030     retval = rtsx_send_cmd(chip, XD_CARD, 500);
1031     if (retval < 0) {
1032         rtsx_clear_xd_error(chip);
1033         rtsx_read_register(chip, XD_DAT, &reg);
1034         if (reg & PROGRAM_ERROR)
1035             xd_set_err_code(chip, XD_PRG_ERROR);
1036         else
1037             xd_set_err_code(chip, XD_TO_ERROR);
1038         return STATUS_FAIL;
1039     }
1040 
1041     return STATUS_SUCCESS;
1042 }
1043 
1044 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk,
1045             u16 logoff, u8 start_page, u8 end_page)
1046 {
1047     struct xd_info *xd_card = &chip->xd_card;
1048     int retval;
1049     u32 page_addr;
1050     u8 reg = 0;
1051 
1052     dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk);
1053 
1054     if (start_page > end_page)
1055         return STATUS_FAIL;
1056     if (phy_blk == BLK_NOT_FOUND)
1057         return STATUS_FAIL;
1058 
1059     rtsx_init_cmd(chip);
1060 
1061     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1062     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1063     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1064              0xFF, (u8)(logoff >> 8));
1065     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1066 
1067     page_addr = (phy_blk << xd_card->block_shift) + start_page;
1068 
1069     xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1070 
1071     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1072              XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1073 
1074     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT,
1075              0xFF, (end_page - start_page));
1076 
1077     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1078              0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1079     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1080              XD_TRANSFER_END, XD_TRANSFER_END);
1081 
1082     retval = rtsx_send_cmd(chip, XD_CARD, 500);
1083     if (retval < 0) {
1084         rtsx_clear_xd_error(chip);
1085         rtsx_read_register(chip, XD_DAT, &reg);
1086         if (reg & PROGRAM_ERROR) {
1087             xd_mark_bad_block(chip, phy_blk);
1088             xd_set_err_code(chip, XD_PRG_ERROR);
1089         } else {
1090             xd_set_err_code(chip, XD_TO_ERROR);
1091         }
1092         return STATUS_FAIL;
1093     }
1094 
1095     return STATUS_SUCCESS;
1096 }
1097 
1098 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk,
1099             u8 start_page, u8 end_page)
1100 {
1101     struct xd_info *xd_card = &chip->xd_card;
1102     u32 old_page, new_page;
1103     u8 i, reg = 0;
1104     int retval;
1105 
1106     dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n",
1107         old_blk, new_blk);
1108 
1109     if (start_page > end_page)
1110         return STATUS_FAIL;
1111 
1112     if (old_blk == BLK_NOT_FOUND || new_blk == BLK_NOT_FOUND)
1113         return STATUS_FAIL;
1114 
1115     old_page = (old_blk << xd_card->block_shift) + start_page;
1116     new_page = (new_blk << xd_card->block_shift) + start_page;
1117 
1118     XD_CLR_BAD_NEWBLK(xd_card);
1119 
1120     retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01,
1121                      PINGPONG_BUFFER);
1122     if (retval)
1123         return retval;
1124 
1125     for (i = start_page; i < end_page; i++) {
1126         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1127             rtsx_clear_xd_error(chip);
1128             xd_set_err_code(chip, XD_NO_CARD);
1129             return STATUS_FAIL;
1130         }
1131 
1132         rtsx_init_cmd(chip);
1133 
1134         xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1135 
1136         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1137         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1138                  XD_AUTO_CHK_DATA_STATUS, 0);
1139         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1140                  XD_TRANSFER_START | XD_READ_PAGES);
1141         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1142                  XD_TRANSFER_END, XD_TRANSFER_END);
1143 
1144         retval = rtsx_send_cmd(chip, XD_CARD, 500);
1145         if (retval < 0) {
1146             rtsx_clear_xd_error(chip);
1147             reg = 0;
1148             rtsx_read_register(chip, XD_CTL, &reg);
1149             if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1150                 mdelay(100);
1151 
1152                 if (detect_card_cd(chip,
1153                            XD_CARD) != STATUS_SUCCESS) {
1154                     xd_set_err_code(chip, XD_NO_CARD);
1155                     return STATUS_FAIL;
1156                 }
1157 
1158                 if (((reg & XD_ECC1_ERROR) &&
1159                      (reg & XD_ECC1_UNCORRECTABLE)) ||
1160                     ((reg & XD_ECC2_ERROR) &&
1161                      (reg & XD_ECC2_UNCORRECTABLE))) {
1162                     rtsx_write_register(chip,
1163                                 XD_PAGE_STATUS,
1164                                 0xFF,
1165                                 XD_BPG);
1166                     rtsx_write_register(chip,
1167                                 XD_BLOCK_STATUS,
1168                                 0xFF,
1169                                 XD_GBLK);
1170                     XD_SET_BAD_OLDBLK(xd_card);
1171                     dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n",
1172                         old_blk);
1173                 }
1174             } else {
1175                 xd_set_err_code(chip, XD_TO_ERROR);
1176                 return STATUS_FAIL;
1177             }
1178         }
1179 
1180         if (XD_CHK_BAD_OLDBLK(xd_card))
1181             rtsx_clear_xd_error(chip);
1182 
1183         rtsx_init_cmd(chip);
1184 
1185         xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1186         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1187         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1188                  XD_TRANSFER_START | XD_WRITE_PAGES);
1189         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1190                  XD_TRANSFER_END, XD_TRANSFER_END);
1191 
1192         retval = rtsx_send_cmd(chip, XD_CARD, 300);
1193         if (retval < 0) {
1194             rtsx_clear_xd_error(chip);
1195             reg = 0;
1196             rtsx_read_register(chip, XD_DAT, &reg);
1197             if (reg & PROGRAM_ERROR) {
1198                 xd_mark_bad_block(chip, new_blk);
1199                 xd_set_err_code(chip, XD_PRG_ERROR);
1200                 XD_SET_BAD_NEWBLK(xd_card);
1201             } else {
1202                 xd_set_err_code(chip, XD_TO_ERROR);
1203             }
1204             return STATUS_FAIL;
1205         }
1206 
1207         old_page++;
1208         new_page++;
1209     }
1210 
1211     return STATUS_SUCCESS;
1212 }
1213 
1214 static int xd_reset_cmd(struct rtsx_chip *chip)
1215 {
1216     int retval;
1217     u8 *ptr;
1218 
1219     rtsx_init_cmd(chip);
1220 
1221     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1222              0xFF, XD_TRANSFER_START | XD_RESET);
1223     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1224              XD_TRANSFER_END, XD_TRANSFER_END);
1225     rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1226     rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1227 
1228     retval = rtsx_send_cmd(chip, XD_CARD, 100);
1229     if (retval < 0)
1230         return STATUS_FAIL;
1231 
1232     ptr = rtsx_get_cmd_data(chip) + 1;
1233     if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1234         return STATUS_SUCCESS;
1235 
1236     return STATUS_FAIL;
1237 }
1238 
1239 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1240 {
1241     struct xd_info *xd_card = &chip->xd_card;
1242     u32 page_addr;
1243     u8 reg = 0, *ptr;
1244     int i, retval;
1245 
1246     if (phy_blk == BLK_NOT_FOUND)
1247         return STATUS_FAIL;
1248 
1249     page_addr = phy_blk << xd_card->block_shift;
1250 
1251     for (i = 0; i < 3; i++) {
1252         rtsx_init_cmd(chip);
1253 
1254         xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1255 
1256         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1257                  XD_TRANSFER_START | XD_ERASE);
1258         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1259                  XD_TRANSFER_END, XD_TRANSFER_END);
1260         rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1261 
1262         retval = rtsx_send_cmd(chip, XD_CARD, 250);
1263         if (retval < 0) {
1264             rtsx_clear_xd_error(chip);
1265             rtsx_read_register(chip, XD_DAT, &reg);
1266             if (reg & PROGRAM_ERROR) {
1267                 xd_mark_bad_block(chip, phy_blk);
1268                 xd_set_err_code(chip, XD_PRG_ERROR);
1269                 return STATUS_FAIL;
1270             }
1271             xd_set_err_code(chip, XD_ERASE_FAIL);
1272             retval = xd_reset_cmd(chip);
1273             if (retval != STATUS_SUCCESS)
1274                 return STATUS_FAIL;
1275             continue;
1276         }
1277 
1278         ptr = rtsx_get_cmd_data(chip) + 1;
1279         if (*ptr & PROGRAM_ERROR) {
1280             xd_mark_bad_block(chip, phy_blk);
1281             xd_set_err_code(chip, XD_PRG_ERROR);
1282             return STATUS_FAIL;
1283         }
1284 
1285         return STATUS_SUCCESS;
1286     }
1287 
1288     xd_mark_bad_block(chip, phy_blk);
1289     xd_set_err_code(chip, XD_ERASE_FAIL);
1290     return STATUS_FAIL;
1291 }
1292 
1293 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1294 {
1295     struct xd_info *xd_card = &chip->xd_card;
1296     struct zone_entry *zone;
1297     int retval;
1298     u32 start, end, i;
1299     u16 max_logoff, cur_fst_page_logoff;
1300     u16 cur_lst_page_logoff, ent_lst_page_logoff;
1301     u8 redunt[11];
1302 
1303     dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, zone_no);
1304 
1305     if (!xd_card->zone) {
1306         retval = xd_init_l2p_tbl(chip);
1307         if (retval != STATUS_SUCCESS)
1308             return retval;
1309     }
1310 
1311     if (xd_card->zone[zone_no].build_flag) {
1312         dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n",
1313             zone_no);
1314         return STATUS_SUCCESS;
1315     }
1316 
1317     zone = &xd_card->zone[zone_no];
1318 
1319     if (!zone->l2p_table) {
1320         zone->l2p_table = vmalloc(2000);
1321         if (!zone->l2p_table)
1322             goto build_fail;
1323     }
1324     memset((u8 *)(zone->l2p_table), 0xff, 2000);
1325 
1326     if (!zone->free_table) {
1327         zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1328         if (!zone->free_table)
1329             goto build_fail;
1330     }
1331     memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1332 
1333     if (zone_no == 0) {
1334         if (xd_card->cis_block == 0xFFFF)
1335             start = 0;
1336         else
1337             start = xd_card->cis_block + 1;
1338         if (XD_CHK_4MB(xd_card)) {
1339             end = 0x200;
1340             max_logoff = 499;
1341         } else {
1342             end = 0x400;
1343             max_logoff = 999;
1344         }
1345     } else {
1346         start = (u32)(zone_no) << 10;
1347         end = (u32)(zone_no + 1) << 10;
1348         max_logoff = 999;
1349     }
1350 
1351     dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n",
1352         start, end);
1353 
1354     zone->set_index = 0;
1355     zone->get_index = 0;
1356     zone->unused_blk_cnt = 0;
1357 
1358     for (i = start; i < end; i++) {
1359         u32 page_addr = i << xd_card->block_shift;
1360         u32 phy_block;
1361 
1362         retval = xd_read_redundant(chip, page_addr, redunt, 11);
1363         if (retval != STATUS_SUCCESS)
1364             continue;
1365 
1366         if (redunt[BLOCK_STATUS] != 0xFF) {
1367             dev_dbg(rtsx_dev(chip), "bad block\n");
1368             continue;
1369         }
1370 
1371         if (xd_check_data_blank(redunt)) {
1372             dev_dbg(rtsx_dev(chip), "blank block\n");
1373             xd_set_unused_block(chip, i);
1374             continue;
1375         }
1376 
1377         cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1378         if (cur_fst_page_logoff == 0xFFFF ||
1379             cur_fst_page_logoff > max_logoff) {
1380             retval = xd_erase_block(chip, i);
1381             if (retval == STATUS_SUCCESS)
1382                 xd_set_unused_block(chip, i);
1383             continue;
1384         }
1385 
1386         if (zone_no == 0 && cur_fst_page_logoff == 0 &&
1387             redunt[PAGE_STATUS] != XD_GPG)
1388             XD_SET_MBR_FAIL(xd_card);
1389 
1390         if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1391             zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1392             continue;
1393         }
1394 
1395         phy_block = zone->l2p_table[cur_fst_page_logoff] +
1396             ((u32)((zone_no) << 10));
1397 
1398         page_addr = ((i + 1) << xd_card->block_shift) - 1;
1399 
1400         retval = xd_read_redundant(chip, page_addr, redunt, 11);
1401         if (retval != STATUS_SUCCESS)
1402             continue;
1403 
1404         cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1405         if (cur_lst_page_logoff == cur_fst_page_logoff) {
1406             int m;
1407 
1408             page_addr = ((phy_block + 1) <<
1409                 xd_card->block_shift) - 1;
1410 
1411             for (m = 0; m < 3; m++) {
1412                 retval = xd_read_redundant(chip, page_addr,
1413                                redunt, 11);
1414                 if (retval == STATUS_SUCCESS)
1415                     break;
1416             }
1417 
1418             if (m == 3) {
1419                 zone->l2p_table[cur_fst_page_logoff] =
1420                     (u16)(i & 0x3FF);
1421                 retval = xd_erase_block(chip, phy_block);
1422                 if (retval == STATUS_SUCCESS)
1423                     xd_set_unused_block(chip, phy_block);
1424                 continue;
1425             }
1426 
1427             ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1428             if (ent_lst_page_logoff != cur_fst_page_logoff) {
1429                 zone->l2p_table[cur_fst_page_logoff] =
1430                     (u16)(i & 0x3FF);
1431                 retval = xd_erase_block(chip, phy_block);
1432                 if (retval == STATUS_SUCCESS)
1433                     xd_set_unused_block(chip, phy_block);
1434                 continue;
1435             } else {
1436                 retval = xd_erase_block(chip, i);
1437                 if (retval == STATUS_SUCCESS)
1438                     xd_set_unused_block(chip, i);
1439             }
1440         } else {
1441             retval = xd_erase_block(chip, i);
1442             if (retval == STATUS_SUCCESS)
1443                 xd_set_unused_block(chip, i);
1444         }
1445     }
1446 
1447     if (XD_CHK_4MB(xd_card))
1448         end = 500;
1449     else
1450         end = 1000;
1451 
1452     i = 0;
1453     for (start = 0; start < end; start++) {
1454         if (zone->l2p_table[start] == 0xFFFF)
1455             i++;
1456     }
1457 
1458     dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n",
1459         end, i);
1460     dev_dbg(rtsx_dev(chip), "Total unused block: %d\n",
1461         zone->unused_blk_cnt);
1462 
1463     if ((zone->unused_blk_cnt - i) < 1)
1464         chip->card_wp |= XD_CARD;
1465 
1466     zone->build_flag = 1;
1467 
1468     return STATUS_SUCCESS;
1469 
1470 build_fail:
1471     vfree(zone->l2p_table);
1472     zone->l2p_table = NULL;
1473     vfree(zone->free_table);
1474     zone->free_table = NULL;
1475 
1476     return STATUS_FAIL;
1477 }
1478 
1479 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1480 {
1481     int retval;
1482 
1483     rtsx_init_cmd(chip);
1484 
1485     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1486     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1487              XD_TRANSFER_START | XD_SET_CMD);
1488     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1489              XD_TRANSFER_END, XD_TRANSFER_END);
1490 
1491     retval = rtsx_send_cmd(chip, XD_CARD, 200);
1492     if (retval < 0)
1493         return STATUS_FAIL;
1494 
1495     return STATUS_SUCCESS;
1496 }
1497 
1498 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk,
1499                   u32 log_blk, u8 start_page, u8 end_page,
1500                   u8 *buf, unsigned int *index,
1501                   unsigned int *offset)
1502 {
1503     struct xd_info *xd_card = &chip->xd_card;
1504     u32 page_addr, new_blk;
1505     u16 log_off;
1506     u8 reg_val, page_cnt;
1507     int zone_no, retval, i;
1508 
1509     if (start_page > end_page)
1510         goto status_fail;
1511 
1512     page_cnt = end_page - start_page;
1513     zone_no = (int)(log_blk / 1000);
1514     log_off = (u16)(log_blk % 1000);
1515 
1516     if ((phy_blk & 0x3FF) == 0x3FF) {
1517         for (i = 0; i < 256; i++) {
1518             page_addr = ((u32)i) << xd_card->block_shift;
1519 
1520             retval = xd_read_redundant(chip, page_addr, NULL, 0);
1521             if (retval == STATUS_SUCCESS)
1522                 break;
1523 
1524             if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1525                 xd_set_err_code(chip, XD_NO_CARD);
1526                 goto status_fail;
1527             }
1528         }
1529     }
1530 
1531     page_addr = (phy_blk << xd_card->block_shift) + start_page;
1532 
1533     rtsx_init_cmd(chip);
1534 
1535     xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1536     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1537     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1538     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1539     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1540              XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1541 
1542     trans_dma_enable(chip->srb->sc_data_direction, chip,
1543              page_cnt * 512, DMA_512);
1544 
1545     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1546              XD_TRANSFER_START | XD_READ_PAGES);
1547     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1548              XD_TRANSFER_END | XD_PPB_EMPTY,
1549              XD_TRANSFER_END | XD_PPB_EMPTY);
1550 
1551     rtsx_send_cmd_no_wait(chip);
1552 
1553     retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1554                         scsi_sg_count(chip->srb),
1555                         index, offset, DMA_FROM_DEVICE,
1556                         chip->xd_timeout);
1557     if (retval < 0) {
1558         rtsx_clear_xd_error(chip);
1559 
1560         if (retval == -ETIMEDOUT) {
1561             xd_set_err_code(chip, XD_TO_ERROR);
1562             goto status_fail;
1563         } else {
1564             goto fail;
1565         }
1566     }
1567 
1568     return STATUS_SUCCESS;
1569 
1570 fail:
1571     retval = rtsx_read_register(chip, XD_PAGE_STATUS, &reg_val);
1572     if (retval)
1573         return retval;
1574 
1575     if (reg_val !=  XD_GPG)
1576         xd_set_err_code(chip, XD_PRG_ERROR);
1577 
1578     retval = rtsx_read_register(chip, XD_CTL, &reg_val);
1579     if (retval)
1580         return retval;
1581 
1582     if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1583                 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ||
1584         ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1585             (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1586         wait_timeout(100);
1587 
1588         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1589             xd_set_err_code(chip, XD_NO_CARD);
1590             goto status_fail;
1591         }
1592 
1593         xd_set_err_code(chip, XD_ECC_ERROR);
1594 
1595         new_blk = xd_get_unused_block(chip, zone_no);
1596         if (new_blk == NO_NEW_BLK) {
1597             XD_CLR_BAD_OLDBLK(xd_card);
1598             goto status_fail;
1599         }
1600 
1601         retval = xd_copy_page(chip, phy_blk, new_blk, 0,
1602                       xd_card->page_off + 1);
1603         if (retval != STATUS_SUCCESS) {
1604             if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1605                 retval = xd_erase_block(chip, new_blk);
1606                 if (retval == STATUS_SUCCESS)
1607                     xd_set_unused_block(chip, new_blk);
1608             } else {
1609                 XD_CLR_BAD_NEWBLK(xd_card);
1610             }
1611             XD_CLR_BAD_OLDBLK(xd_card);
1612             goto status_fail;
1613         }
1614         xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1615         xd_erase_block(chip, phy_blk);
1616         xd_mark_bad_block(chip, phy_blk);
1617         XD_CLR_BAD_OLDBLK(xd_card);
1618     }
1619 
1620 status_fail:
1621     return STATUS_FAIL;
1622 }
1623 
1624 static int xd_finish_write(struct rtsx_chip *chip,
1625                u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1626 {
1627     struct xd_info *xd_card = &chip->xd_card;
1628     int retval, zone_no;
1629     u16 log_off;
1630 
1631     dev_dbg(rtsx_dev(chip), "old_blk = 0x%x, ", old_blk);
1632     dev_dbg(rtsx_dev(chip), "new_blk = 0x%x, ", new_blk);
1633     dev_dbg(rtsx_dev(chip), "log_blk = 0x%x\n", log_blk);
1634 
1635     if (page_off > xd_card->page_off)
1636         return STATUS_FAIL;
1637 
1638     zone_no = (int)(log_blk / 1000);
1639     log_off = (u16)(log_blk % 1000);
1640 
1641     if (old_blk == BLK_NOT_FOUND) {
1642         retval = xd_init_page(chip, new_blk, log_off,
1643                       page_off, xd_card->page_off + 1);
1644         if (retval != STATUS_SUCCESS) {
1645             retval = xd_erase_block(chip, new_blk);
1646             if (retval == STATUS_SUCCESS)
1647                 xd_set_unused_block(chip, new_blk);
1648             return STATUS_FAIL;
1649         }
1650     } else {
1651         retval = xd_copy_page(chip, old_blk, new_blk,
1652                       page_off, xd_card->page_off + 1);
1653         if (retval != STATUS_SUCCESS) {
1654             if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1655                 retval = xd_erase_block(chip, new_blk);
1656                 if (retval == STATUS_SUCCESS)
1657                     xd_set_unused_block(chip, new_blk);
1658             }
1659             XD_CLR_BAD_NEWBLK(xd_card);
1660             return STATUS_FAIL;
1661         }
1662 
1663         retval = xd_erase_block(chip, old_blk);
1664         if (retval == STATUS_SUCCESS) {
1665             if (XD_CHK_BAD_OLDBLK(xd_card)) {
1666                 xd_mark_bad_block(chip, old_blk);
1667                 XD_CLR_BAD_OLDBLK(xd_card);
1668             } else {
1669                 xd_set_unused_block(chip, old_blk);
1670             }
1671         } else {
1672             xd_set_err_code(chip, XD_NO_ERROR);
1673             XD_CLR_BAD_OLDBLK(xd_card);
1674         }
1675     }
1676 
1677     xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1678 
1679     return STATUS_SUCCESS;
1680 }
1681 
1682 static int xd_prepare_write(struct rtsx_chip *chip,
1683                 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1684 {
1685     int retval;
1686 
1687     dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1688         __func__, old_blk, new_blk, log_blk, (int)page_off);
1689 
1690     if (page_off) {
1691         retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1692         if (retval != STATUS_SUCCESS)
1693             return STATUS_FAIL;
1694     }
1695 
1696     return STATUS_SUCCESS;
1697 }
1698 
1699 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk,
1700                    u32 new_blk, u32 log_blk, u8 start_page,
1701                    u8 end_page, u8 *buf, unsigned int *index,
1702                    unsigned int *offset)
1703 {
1704     struct xd_info *xd_card = &chip->xd_card;
1705     u32 page_addr;
1706     int zone_no, retval;
1707     u16 log_off;
1708     u8 page_cnt, reg_val;
1709 
1710     dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1711         __func__, old_blk, new_blk, log_blk);
1712 
1713     if (start_page > end_page)
1714         goto status_fail;
1715 
1716     page_cnt = end_page - start_page;
1717     zone_no = (int)(log_blk / 1000);
1718     log_off = (u16)(log_blk % 1000);
1719 
1720     page_addr = (new_blk << xd_card->block_shift) + start_page;
1721 
1722     retval = xd_send_cmd(chip, READ1_1);
1723     if (retval != STATUS_SUCCESS)
1724         goto status_fail;
1725 
1726     rtsx_init_cmd(chip);
1727 
1728     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1729              0xFF, (u8)(log_off >> 8));
1730     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1731     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1732     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1733 
1734     xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1735 
1736     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1737              XD_BA_TRANSFORM);
1738     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1739     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1740 
1741     trans_dma_enable(chip->srb->sc_data_direction, chip,
1742              page_cnt * 512, DMA_512);
1743 
1744     rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1745              0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1746     rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1747              XD_TRANSFER_END, XD_TRANSFER_END);
1748 
1749     rtsx_send_cmd_no_wait(chip);
1750 
1751     retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1752                         scsi_sg_count(chip->srb),
1753                         index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1754     if (retval < 0) {
1755         rtsx_clear_xd_error(chip);
1756 
1757         if (retval == -ETIMEDOUT) {
1758             xd_set_err_code(chip, XD_TO_ERROR);
1759             goto status_fail;
1760         } else {
1761             goto fail;
1762         }
1763     }
1764 
1765     if (end_page == (xd_card->page_off + 1)) {
1766         xd_card->delay_write.delay_write_flag = 0;
1767 
1768         if (old_blk != BLK_NOT_FOUND) {
1769             retval = xd_erase_block(chip, old_blk);
1770             if (retval == STATUS_SUCCESS) {
1771                 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1772                     xd_mark_bad_block(chip, old_blk);
1773                     XD_CLR_BAD_OLDBLK(xd_card);
1774                 } else {
1775                     xd_set_unused_block(chip, old_blk);
1776                 }
1777             } else {
1778                 xd_set_err_code(chip, XD_NO_ERROR);
1779                 XD_CLR_BAD_OLDBLK(xd_card);
1780             }
1781         }
1782         xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1783     }
1784 
1785     return STATUS_SUCCESS;
1786 
1787 fail:
1788     retval = rtsx_read_register(chip, XD_DAT, &reg_val);
1789     if (retval)
1790         return retval;
1791     if (reg_val & PROGRAM_ERROR) {
1792         xd_set_err_code(chip, XD_PRG_ERROR);
1793         xd_mark_bad_block(chip, new_blk);
1794     }
1795 
1796 status_fail:
1797     return STATUS_FAIL;
1798 }
1799 
1800 #ifdef XD_DELAY_WRITE
1801 int xd_delay_write(struct rtsx_chip *chip)
1802 {
1803     struct xd_info *xd_card = &chip->xd_card;
1804     struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1805     int retval;
1806 
1807     if (delay_write->delay_write_flag) {
1808         retval = xd_switch_clock(chip);
1809         if (retval != STATUS_SUCCESS)
1810             return STATUS_FAIL;
1811 
1812         delay_write->delay_write_flag = 0;
1813         retval = xd_finish_write(chip,
1814                      delay_write->old_phyblock,
1815                      delay_write->new_phyblock,
1816                      delay_write->logblock,
1817                      delay_write->pageoff);
1818         if (retval != STATUS_SUCCESS)
1819             return STATUS_FAIL;
1820     }
1821 
1822     return STATUS_SUCCESS;
1823 }
1824 #endif
1825 
1826 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
1827       u32 start_sector, u16 sector_cnt)
1828 {
1829     struct xd_info *xd_card = &chip->xd_card;
1830     unsigned int lun = SCSI_LUN(srb);
1831 #ifdef XD_DELAY_WRITE
1832     struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1833 #endif
1834     int retval, zone_no;
1835     unsigned int index = 0, offset = 0;
1836     u32 log_blk, old_blk = 0, new_blk = 0;
1837     u16 log_off, total_sec_cnt = sector_cnt;
1838     u8 start_page, end_page = 0, page_cnt;
1839     u8 *ptr;
1840 
1841     xd_set_err_code(chip, XD_NO_ERROR);
1842 
1843     xd_card->cleanup_counter = 0;
1844 
1845     dev_dbg(rtsx_dev(chip), "%s: scsi_sg_count = %d\n", __func__,
1846         scsi_sg_count(srb));
1847 
1848     ptr = (u8 *)scsi_sglist(srb);
1849 
1850     retval = xd_switch_clock(chip);
1851     if (retval != STATUS_SUCCESS)
1852         return STATUS_FAIL;
1853 
1854     if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1855         chip->card_fail |= XD_CARD;
1856         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1857         return STATUS_FAIL;
1858     }
1859 
1860     log_blk = start_sector >> xd_card->block_shift;
1861     start_page = (u8)start_sector & xd_card->page_off;
1862     zone_no = (int)(log_blk / 1000);
1863     log_off = (u16)(log_blk % 1000);
1864 
1865     if (xd_card->zone[zone_no].build_flag == 0) {
1866         retval = xd_build_l2p_tbl(chip, zone_no);
1867         if (retval != STATUS_SUCCESS) {
1868             chip->card_fail |= XD_CARD;
1869             set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1870             return STATUS_FAIL;
1871         }
1872     }
1873 
1874     if (srb->sc_data_direction == DMA_TO_DEVICE) {
1875 #ifdef XD_DELAY_WRITE
1876         if (delay_write->delay_write_flag &&
1877             delay_write->logblock == log_blk &&
1878             start_page > delay_write->pageoff) {
1879             delay_write->delay_write_flag = 0;
1880             if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1881                 retval = xd_copy_page(chip,
1882                               delay_write->old_phyblock,
1883                               delay_write->new_phyblock,
1884                               delay_write->pageoff,
1885                               start_page);
1886                 if (retval != STATUS_SUCCESS) {
1887                     set_sense_type(chip, lun,
1888                                SENSE_TYPE_MEDIA_WRITE_ERR);
1889                     return STATUS_FAIL;
1890                 }
1891             }
1892             old_blk = delay_write->old_phyblock;
1893             new_blk = delay_write->new_phyblock;
1894         } else if (delay_write->delay_write_flag &&
1895                 (delay_write->logblock == log_blk) &&
1896                 (start_page == delay_write->pageoff)) {
1897             delay_write->delay_write_flag = 0;
1898             old_blk = delay_write->old_phyblock;
1899             new_blk = delay_write->new_phyblock;
1900         } else {
1901             retval = xd_delay_write(chip);
1902             if (retval != STATUS_SUCCESS) {
1903                 set_sense_type(chip, lun,
1904                            SENSE_TYPE_MEDIA_WRITE_ERR);
1905                 return STATUS_FAIL;
1906             }
1907 #endif
1908             old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1909             new_blk  = xd_get_unused_block(chip, zone_no);
1910             if (old_blk == BLK_NOT_FOUND ||
1911                 new_blk == BLK_NOT_FOUND) {
1912                 set_sense_type(chip, lun,
1913                            SENSE_TYPE_MEDIA_WRITE_ERR);
1914                 return STATUS_FAIL;
1915             }
1916 
1917             retval = xd_prepare_write(chip, old_blk, new_blk,
1918                           log_blk, start_page);
1919             if (retval != STATUS_SUCCESS) {
1920                 if (detect_card_cd(chip, XD_CARD) !=
1921                     STATUS_SUCCESS) {
1922                     set_sense_type(chip, lun,
1923                                SENSE_TYPE_MEDIA_NOT_PRESENT);
1924                     return STATUS_FAIL;
1925                 }
1926                 set_sense_type(chip, lun,
1927                            SENSE_TYPE_MEDIA_WRITE_ERR);
1928                 return STATUS_FAIL;
1929             }
1930 #ifdef XD_DELAY_WRITE
1931         }
1932 #endif
1933     } else {
1934 #ifdef XD_DELAY_WRITE
1935         retval = xd_delay_write(chip);
1936         if (retval != STATUS_SUCCESS) {
1937             if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1938                 set_sense_type(chip, lun,
1939                            SENSE_TYPE_MEDIA_NOT_PRESENT);
1940                 return STATUS_FAIL;
1941             }
1942             set_sense_type(chip, lun,
1943                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1944             return STATUS_FAIL;
1945         }
1946 #endif
1947 
1948         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1949         if (old_blk == BLK_NOT_FOUND) {
1950             set_sense_type(chip, lun,
1951                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1952             return STATUS_FAIL;
1953         }
1954     }
1955 
1956     dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk);
1957 
1958     while (total_sec_cnt) {
1959         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1960             chip->card_fail |= XD_CARD;
1961             set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1962             return STATUS_FAIL;
1963         }
1964 
1965         if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1966             end_page = xd_card->page_off + 1;
1967         else
1968             end_page = start_page + (u8)total_sec_cnt;
1969 
1970         page_cnt = end_page - start_page;
1971         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1972             retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1973                             start_page, end_page,
1974                             ptr, &index, &offset);
1975             if (retval != STATUS_SUCCESS) {
1976                 set_sense_type(chip, lun,
1977                            SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1978                 return STATUS_FAIL;
1979             }
1980         } else {
1981             retval = xd_write_multiple_pages(chip, old_blk,
1982                              new_blk, log_blk,
1983                              start_page, end_page,
1984                              ptr, &index, &offset);
1985             if (retval != STATUS_SUCCESS) {
1986                 set_sense_type(chip, lun,
1987                            SENSE_TYPE_MEDIA_WRITE_ERR);
1988                 return STATUS_FAIL;
1989             }
1990         }
1991 
1992         total_sec_cnt -= page_cnt;
1993         if (scsi_sg_count(srb) == 0)
1994             ptr += page_cnt * 512;
1995 
1996         if (total_sec_cnt == 0)
1997             break;
1998 
1999         log_blk++;
2000         zone_no = (int)(log_blk / 1000);
2001         log_off = (u16)(log_blk % 1000);
2002 
2003         if (xd_card->zone[zone_no].build_flag == 0) {
2004             retval = xd_build_l2p_tbl(chip, zone_no);
2005             if (retval != STATUS_SUCCESS) {
2006                 chip->card_fail |= XD_CARD;
2007                 set_sense_type(chip, lun,
2008                            SENSE_TYPE_MEDIA_NOT_PRESENT);
2009                 return STATUS_FAIL;
2010             }
2011         }
2012 
2013         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2014         if (old_blk == BLK_NOT_FOUND) {
2015             if (srb->sc_data_direction == DMA_FROM_DEVICE)
2016                 set_sense_type(chip, lun,
2017                            SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2018             else
2019                 set_sense_type(chip, lun,
2020                            SENSE_TYPE_MEDIA_WRITE_ERR);
2021 
2022             return STATUS_FAIL;
2023         }
2024 
2025         if (srb->sc_data_direction == DMA_TO_DEVICE) {
2026             new_blk = xd_get_unused_block(chip, zone_no);
2027             if (new_blk == BLK_NOT_FOUND) {
2028                 set_sense_type(chip, lun,
2029                            SENSE_TYPE_MEDIA_WRITE_ERR);
2030                 return STATUS_FAIL;
2031             }
2032         }
2033 
2034         start_page = 0;
2035     }
2036 
2037     if (srb->sc_data_direction == DMA_TO_DEVICE &&
2038         (end_page != (xd_card->page_off + 1))) {
2039 #ifdef XD_DELAY_WRITE
2040         delay_write->delay_write_flag = 1;
2041         delay_write->old_phyblock = old_blk;
2042         delay_write->new_phyblock = new_blk;
2043         delay_write->logblock = log_blk;
2044         delay_write->pageoff = end_page;
2045 #else
2046         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2047             chip->card_fail |= XD_CARD;
2048             set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2049             return STATUS_FAIL;
2050         }
2051 
2052         retval = xd_finish_write(chip, old_blk, new_blk,
2053                      log_blk, end_page);
2054         if (retval != STATUS_SUCCESS) {
2055             if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2056                 set_sense_type(chip, lun,
2057                            SENSE_TYPE_MEDIA_NOT_PRESENT);
2058                 return STATUS_FAIL;
2059             }
2060             set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2061             return STATUS_FAIL;
2062         }
2063 #endif
2064     }
2065 
2066     scsi_set_resid(srb, 0);
2067 
2068     return STATUS_SUCCESS;
2069 }
2070 
2071 void xd_free_l2p_tbl(struct rtsx_chip *chip)
2072 {
2073     struct xd_info *xd_card = &chip->xd_card;
2074     int i = 0;
2075 
2076     if (xd_card->zone) {
2077         for (i = 0; i < xd_card->zone_cnt; i++) {
2078             vfree(xd_card->zone[i].l2p_table);
2079             xd_card->zone[i].l2p_table = NULL;
2080             vfree(xd_card->zone[i].free_table);
2081             xd_card->zone[i].free_table = NULL;
2082         }
2083         vfree(xd_card->zone);
2084         xd_card->zone = NULL;
2085     }
2086 }
2087 
2088 void xd_cleanup_work(struct rtsx_chip *chip)
2089 {
2090 #ifdef XD_DELAY_WRITE
2091     struct xd_info *xd_card = &chip->xd_card;
2092 
2093     if (xd_card->delay_write.delay_write_flag) {
2094         dev_dbg(rtsx_dev(chip), "xD: delay write\n");
2095         xd_delay_write(chip);
2096         xd_card->cleanup_counter = 0;
2097     }
2098 #endif
2099 }
2100 
2101 int xd_power_off_card3v3(struct rtsx_chip *chip)
2102 {
2103     int retval;
2104 
2105     retval = disable_card_clock(chip, XD_CARD);
2106     if (retval != STATUS_SUCCESS)
2107         return STATUS_FAIL;
2108 
2109     retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
2110     if (retval)
2111         return retval;
2112 
2113     if (!chip->ft2_fast_mode) {
2114         retval = card_power_off(chip, XD_CARD);
2115         if (retval != STATUS_SUCCESS)
2116             return STATUS_FAIL;
2117 
2118         wait_timeout(50);
2119     }
2120 
2121     if (chip->asic_code) {
2122         retval = xd_pull_ctl_disable(chip);
2123         if (retval != STATUS_SUCCESS)
2124             return STATUS_FAIL;
2125     } else {
2126         retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2127         if (retval)
2128             return retval;
2129     }
2130 
2131     return STATUS_SUCCESS;
2132 }
2133 
2134 int release_xd_card(struct rtsx_chip *chip)
2135 {
2136     struct xd_info *xd_card = &chip->xd_card;
2137     int retval;
2138 
2139     chip->card_ready &= ~XD_CARD;
2140     chip->card_fail &= ~XD_CARD;
2141     chip->card_wp &= ~XD_CARD;
2142 
2143     xd_card->delay_write.delay_write_flag = 0;
2144 
2145     xd_free_l2p_tbl(chip);
2146 
2147     retval = xd_power_off_card3v3(chip);
2148     if (retval != STATUS_SUCCESS)
2149         return STATUS_FAIL;
2150 
2151     return STATUS_SUCCESS;
2152 }
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