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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for Realtek PCI-Express card reader
0004  *
0005  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0006  *
0007  * Author:
0008  *   Wei WANG (wei_wang@realsil.com.cn)
0009  *   Micky Ching (micky_ching@realsil.com.cn)
0010  */
0011 
0012 #include <linux/blkdev.h>
0013 #include <linux/kthread.h>
0014 #include <linux/sched.h>
0015 
0016 #include "rtsx.h"
0017 #include "spi.h"
0018 
0019 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
0020 {
0021     struct spi_info *spi = &chip->spi;
0022 
0023     spi->err_code = err_code;
0024 }
0025 
0026 static int spi_init(struct rtsx_chip *chip)
0027 {
0028     int retval;
0029 
0030     retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
0031                      CS_POLARITY_LOW | DTO_MSB_FIRST
0032                      | SPI_MASTER | SPI_MODE0 | SPI_AUTO);
0033     if (retval)
0034         return retval;
0035     retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
0036                      SAMPLE_DELAY_HALF);
0037     if (retval)
0038         return retval;
0039 
0040     return STATUS_SUCCESS;
0041 }
0042 
0043 static int spi_set_init_para(struct rtsx_chip *chip)
0044 {
0045     struct spi_info *spi = &chip->spi;
0046     int retval;
0047 
0048     retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF,
0049                      (u8)(spi->clk_div >> 8));
0050     if (retval)
0051         return retval;
0052     retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF,
0053                      (u8)(spi->clk_div));
0054     if (retval)
0055         return retval;
0056 
0057     retval = switch_clock(chip, spi->spi_clock);
0058     if (retval != STATUS_SUCCESS)
0059         return STATUS_FAIL;
0060 
0061     retval = select_card(chip, SPI_CARD);
0062     if (retval != STATUS_SUCCESS)
0063         return STATUS_FAIL;
0064 
0065     retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
0066                      SPI_CLK_EN);
0067     if (retval)
0068         return retval;
0069     retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
0070                      SPI_OUTPUT_EN);
0071     if (retval)
0072         return retval;
0073 
0074     wait_timeout(10);
0075 
0076     retval = spi_init(chip);
0077     if (retval != STATUS_SUCCESS)
0078         return STATUS_FAIL;
0079 
0080     return STATUS_SUCCESS;
0081 }
0082 
0083 static int sf_polling_status(struct rtsx_chip *chip, int msec)
0084 {
0085     int retval;
0086 
0087     rtsx_init_cmd(chip);
0088 
0089     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
0090     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0091              SPI_TRANSFER0_START | SPI_POLLING_MODE0);
0092     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0093              SPI_TRANSFER0_END);
0094 
0095     retval = rtsx_send_cmd(chip, 0, msec);
0096     if (retval < 0) {
0097         rtsx_clear_spi_error(chip);
0098         spi_set_err_code(chip, SPI_BUSY_ERR);
0099         return STATUS_FAIL;
0100     }
0101 
0102     return STATUS_SUCCESS;
0103 }
0104 
0105 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
0106 {
0107     struct spi_info *spi = &chip->spi;
0108     int retval;
0109 
0110     if (!spi->write_en)
0111         return STATUS_SUCCESS;
0112 
0113     rtsx_init_cmd(chip);
0114 
0115     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
0116     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0117              SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0118     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0119              SPI_TRANSFER0_START | SPI_C_MODE0);
0120     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0121              SPI_TRANSFER0_END);
0122 
0123     retval = rtsx_send_cmd(chip, 0, 100);
0124     if (retval < 0) {
0125         rtsx_clear_spi_error(chip);
0126         spi_set_err_code(chip, SPI_HW_ERR);
0127         return STATUS_FAIL;
0128     }
0129 
0130     return STATUS_SUCCESS;
0131 }
0132 
0133 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
0134 {
0135     struct spi_info *spi = &chip->spi;
0136     int retval;
0137 
0138     if (!spi->write_en)
0139         return STATUS_SUCCESS;
0140 
0141     rtsx_init_cmd(chip);
0142 
0143     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
0144     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0145              SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0146     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0147              SPI_TRANSFER0_START | SPI_C_MODE0);
0148     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0149              SPI_TRANSFER0_END);
0150 
0151     retval = rtsx_send_cmd(chip, 0, 100);
0152     if (retval < 0) {
0153         rtsx_clear_spi_error(chip);
0154         spi_set_err_code(chip, SPI_HW_ERR);
0155         return STATUS_FAIL;
0156     }
0157 
0158     return STATUS_SUCCESS;
0159 }
0160 
0161 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
0162                u16 len)
0163 {
0164     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
0165     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0166              SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0167     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
0168     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
0169     if (addr_mode) {
0170         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
0171         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
0172                  (u8)(addr >> 8));
0173         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
0174                  (u8)(addr >> 16));
0175         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0176                  SPI_TRANSFER0_START | SPI_CADO_MODE0);
0177     } else {
0178         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0179                  SPI_TRANSFER0_START | SPI_CDO_MODE0);
0180     }
0181     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0182              SPI_TRANSFER0_END);
0183 }
0184 
0185 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
0186 {
0187     int retval;
0188 
0189     rtsx_init_cmd(chip);
0190 
0191     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
0192     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0193              SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0194     if (addr_mode) {
0195         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
0196         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
0197                  (u8)(addr >> 8));
0198         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
0199                  (u8)(addr >> 16));
0200         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0201                  SPI_TRANSFER0_START | SPI_CA_MODE0);
0202     } else {
0203         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0204                  SPI_TRANSFER0_START | SPI_C_MODE0);
0205     }
0206     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0207              SPI_TRANSFER0_END);
0208 
0209     retval = rtsx_send_cmd(chip, 0, 100);
0210     if (retval < 0) {
0211         rtsx_clear_spi_error(chip);
0212         spi_set_err_code(chip, SPI_HW_ERR);
0213         return STATUS_FAIL;
0214     }
0215 
0216     return STATUS_SUCCESS;
0217 }
0218 
0219 static int spi_init_eeprom(struct rtsx_chip *chip)
0220 {
0221     int retval;
0222     int clk;
0223 
0224     if (chip->asic_code)
0225         clk = 30;
0226     else
0227         clk = CLK_30;
0228 
0229     retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
0230     if (retval)
0231         return retval;
0232     retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
0233     if (retval)
0234         return retval;
0235 
0236     retval = switch_clock(chip, clk);
0237     if (retval != STATUS_SUCCESS)
0238         return STATUS_FAIL;
0239 
0240     retval = select_card(chip, SPI_CARD);
0241     if (retval != STATUS_SUCCESS)
0242         return STATUS_FAIL;
0243 
0244     retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
0245                      SPI_CLK_EN);
0246     if (retval)
0247         return retval;
0248     retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
0249                      SPI_OUTPUT_EN);
0250     if (retval)
0251         return retval;
0252 
0253     wait_timeout(10);
0254 
0255     retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
0256                      CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
0257     if (retval)
0258         return retval;
0259     retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
0260                      SAMPLE_DELAY_HALF);
0261     if (retval)
0262         return retval;
0263 
0264     return STATUS_SUCCESS;
0265 }
0266 
0267 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
0268 {
0269     int retval;
0270 
0271     rtsx_init_cmd(chip);
0272 
0273     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
0274     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
0275     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0276              SPI_TRANSFER0_START | SPI_CA_MODE0);
0277     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0278              SPI_TRANSFER0_END);
0279 
0280     retval = rtsx_send_cmd(chip, 0, 100);
0281     if (retval < 0)
0282         return STATUS_FAIL;
0283 
0284     return STATUS_SUCCESS;
0285 }
0286 
0287 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
0288 {
0289     int retval;
0290 
0291     retval = spi_init_eeprom(chip);
0292     if (retval != STATUS_SUCCESS)
0293         return STATUS_FAIL;
0294 
0295     retval = spi_eeprom_program_enable(chip);
0296     if (retval != STATUS_SUCCESS)
0297         return STATUS_FAIL;
0298 
0299     rtsx_init_cmd(chip);
0300 
0301     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
0302     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
0303     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
0304     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
0305     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0306              SPI_TRANSFER0_START | SPI_CA_MODE0);
0307     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0308              SPI_TRANSFER0_END);
0309 
0310     retval = rtsx_send_cmd(chip, 0, 100);
0311     if (retval < 0)
0312         return STATUS_FAIL;
0313 
0314     retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
0315     if (retval)
0316         return retval;
0317 
0318     return STATUS_SUCCESS;
0319 }
0320 
0321 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
0322 {
0323     int retval;
0324 
0325     retval = spi_init_eeprom(chip);
0326     if (retval != STATUS_SUCCESS)
0327         return STATUS_FAIL;
0328 
0329     retval = spi_eeprom_program_enable(chip);
0330     if (retval != STATUS_SUCCESS)
0331         return STATUS_FAIL;
0332 
0333     rtsx_init_cmd(chip);
0334 
0335     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
0336     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
0337     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
0338     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
0339     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
0340     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
0341     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0342              SPI_TRANSFER0_START | SPI_CA_MODE0);
0343     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0344              SPI_TRANSFER0_END);
0345 
0346     retval = rtsx_send_cmd(chip, 0, 100);
0347     if (retval < 0)
0348         return STATUS_FAIL;
0349 
0350     retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
0351     if (retval)
0352         return retval;
0353 
0354     return STATUS_SUCCESS;
0355 }
0356 
0357 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
0358 {
0359     int retval;
0360     u8 data;
0361 
0362     retval = spi_init_eeprom(chip);
0363     if (retval != STATUS_SUCCESS)
0364         return STATUS_FAIL;
0365 
0366     rtsx_init_cmd(chip);
0367 
0368     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
0369     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
0370     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
0371     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
0372     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
0373     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
0374     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
0375     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0376              SPI_TRANSFER0_START | SPI_CADI_MODE0);
0377     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0378              SPI_TRANSFER0_END);
0379 
0380     retval = rtsx_send_cmd(chip, 0, 100);
0381     if (retval < 0)
0382         return STATUS_FAIL;
0383 
0384     wait_timeout(5);
0385     retval = rtsx_read_register(chip, SPI_DATA, &data);
0386     if (retval)
0387         return retval;
0388 
0389     if (val)
0390         *val = data;
0391 
0392     retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
0393     if (retval)
0394         return retval;
0395 
0396     return STATUS_SUCCESS;
0397 }
0398 
0399 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
0400 {
0401     int retval;
0402 
0403     retval = spi_init_eeprom(chip);
0404     if (retval != STATUS_SUCCESS)
0405         return STATUS_FAIL;
0406 
0407     retval = spi_eeprom_program_enable(chip);
0408     if (retval != STATUS_SUCCESS)
0409         return STATUS_FAIL;
0410 
0411     rtsx_init_cmd(chip);
0412 
0413     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
0414     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
0415     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
0416     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
0417     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
0418     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
0419     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
0420     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0421              SPI_TRANSFER0_START | SPI_CA_MODE0);
0422     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0423              SPI_TRANSFER0_END);
0424 
0425     retval = rtsx_send_cmd(chip, 0, 100);
0426     if (retval < 0)
0427         return STATUS_FAIL;
0428 
0429     retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
0430     if (retval)
0431         return retval;
0432 
0433     return STATUS_SUCCESS;
0434 }
0435 
0436 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0437 {
0438     struct spi_info *spi = &chip->spi;
0439 
0440     dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__,
0441         spi->err_code);
0442     rtsx_stor_set_xfer_buf(&spi->err_code,
0443                    min_t(int, scsi_bufflen(srb), 1), srb);
0444     scsi_set_resid(srb, scsi_bufflen(srb) - 1);
0445 
0446     return STATUS_SUCCESS;
0447 }
0448 
0449 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0450 {
0451     struct spi_info *spi = &chip->spi;
0452 
0453     spi_set_err_code(chip, SPI_NO_ERR);
0454 
0455     if (chip->asic_code)
0456         spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
0457     else
0458         spi->spi_clock = srb->cmnd[3];
0459 
0460     spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
0461     spi->write_en = srb->cmnd[6];
0462 
0463     dev_dbg(rtsx_dev(chip), "spi_clock = %d, clk_div = %d, write_en = %d\n",
0464         spi->spi_clock, spi->clk_div, spi->write_en);
0465 
0466     return STATUS_SUCCESS;
0467 }
0468 
0469 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0470 {
0471     int retval;
0472     u16 len;
0473     u8 *buf;
0474 
0475     spi_set_err_code(chip, SPI_NO_ERR);
0476 
0477     len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
0478     if (len > 512) {
0479         spi_set_err_code(chip, SPI_INVALID_COMMAND);
0480         return STATUS_FAIL;
0481     }
0482 
0483     retval = spi_set_init_para(chip);
0484     if (retval != STATUS_SUCCESS) {
0485         spi_set_err_code(chip, SPI_HW_ERR);
0486         return STATUS_FAIL;
0487     }
0488 
0489     rtsx_init_cmd(chip);
0490 
0491     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
0492              PINGPONG_BUFFER);
0493 
0494     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
0495     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
0496     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
0497     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
0498     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0499              SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0500     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
0501     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
0502 
0503     if (len == 0) {
0504         if (srb->cmnd[9]) {
0505             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
0506                      0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
0507         } else {
0508             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
0509                      0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
0510         }
0511     } else {
0512         if (srb->cmnd[9]) {
0513             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0514                      SPI_TRANSFER0_START | SPI_CADI_MODE0);
0515         } else {
0516             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0517                      SPI_TRANSFER0_START | SPI_CDI_MODE0);
0518         }
0519     }
0520 
0521     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0522              SPI_TRANSFER0_END);
0523 
0524     retval = rtsx_send_cmd(chip, 0, 100);
0525     if (retval < 0) {
0526         rtsx_clear_spi_error(chip);
0527         spi_set_err_code(chip, SPI_HW_ERR);
0528         return STATUS_FAIL;
0529     }
0530 
0531     if (len) {
0532         buf = kmalloc(len, GFP_KERNEL);
0533         if (!buf)
0534             return STATUS_ERROR;
0535 
0536         retval = rtsx_read_ppbuf(chip, buf, len);
0537         if (retval != STATUS_SUCCESS) {
0538             spi_set_err_code(chip, SPI_READ_ERR);
0539             kfree(buf);
0540             return STATUS_FAIL;
0541         }
0542 
0543         rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
0544         scsi_set_resid(srb, 0);
0545 
0546         kfree(buf);
0547     }
0548 
0549     return STATUS_SUCCESS;
0550 }
0551 
0552 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0553 {
0554     int retval;
0555     unsigned int index = 0, offset = 0;
0556     u8 ins, slow_read;
0557     u32 addr;
0558     u16 len;
0559     u8 *buf;
0560 
0561     spi_set_err_code(chip, SPI_NO_ERR);
0562 
0563     ins = srb->cmnd[3];
0564     addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
0565                     << 8) | srb->cmnd[6];
0566     len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
0567     slow_read = srb->cmnd[9];
0568 
0569     retval = spi_set_init_para(chip);
0570     if (retval != STATUS_SUCCESS) {
0571         spi_set_err_code(chip, SPI_HW_ERR);
0572         return STATUS_FAIL;
0573     }
0574 
0575     buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
0576     if (!buf)
0577         return STATUS_ERROR;
0578 
0579     while (len) {
0580         u16 pagelen = SF_PAGE_LEN - (u8)addr;
0581 
0582         if (pagelen > len)
0583             pagelen = len;
0584 
0585         rtsx_init_cmd(chip);
0586 
0587         trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
0588 
0589         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
0590 
0591         if (slow_read) {
0592             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
0593                      (u8)addr);
0594             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
0595                      (u8)(addr >> 8));
0596             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
0597                      (u8)(addr >> 16));
0598             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0599                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0600         } else {
0601             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
0602                      (u8)addr);
0603             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
0604                      (u8)(addr >> 8));
0605             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
0606                      (u8)(addr >> 16));
0607             rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0608                      SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
0609         }
0610 
0611         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
0612                  (u8)(pagelen >> 8));
0613         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
0614                  (u8)pagelen);
0615 
0616         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0617                  SPI_TRANSFER0_START | SPI_CADI_MODE0);
0618         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
0619                  SPI_TRANSFER0_END, SPI_TRANSFER0_END);
0620 
0621         rtsx_send_cmd_no_wait(chip);
0622 
0623         retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
0624                         DMA_FROM_DEVICE, 10000);
0625         if (retval < 0) {
0626             kfree(buf);
0627             rtsx_clear_spi_error(chip);
0628             spi_set_err_code(chip, SPI_HW_ERR);
0629             return STATUS_FAIL;
0630         }
0631 
0632         rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
0633                       TO_XFER_BUF);
0634 
0635         addr += pagelen;
0636         len -= pagelen;
0637     }
0638 
0639     scsi_set_resid(srb, 0);
0640     kfree(buf);
0641 
0642     return STATUS_SUCCESS;
0643 }
0644 
0645 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0646 {
0647     int retval;
0648     u8 ins, program_mode;
0649     u32 addr;
0650     u16 len;
0651     u8 *buf;
0652     unsigned int index = 0, offset = 0;
0653 
0654     spi_set_err_code(chip, SPI_NO_ERR);
0655 
0656     ins = srb->cmnd[3];
0657     addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
0658                     << 8) | srb->cmnd[6];
0659     len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
0660     program_mode = srb->cmnd[9];
0661 
0662     retval = spi_set_init_para(chip);
0663     if (retval != STATUS_SUCCESS) {
0664         spi_set_err_code(chip, SPI_HW_ERR);
0665         return STATUS_FAIL;
0666     }
0667 
0668     if (program_mode == BYTE_PROGRAM) {
0669         buf = kmalloc(4, GFP_KERNEL);
0670         if (!buf)
0671             return STATUS_ERROR;
0672 
0673         while (len) {
0674             retval = sf_enable_write(chip, SPI_WREN);
0675             if (retval != STATUS_SUCCESS) {
0676                 kfree(buf);
0677                 return STATUS_FAIL;
0678             }
0679 
0680             rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
0681                           FROM_XFER_BUF);
0682 
0683             rtsx_init_cmd(chip);
0684 
0685             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
0686                      0x01, PINGPONG_BUFFER);
0687             rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
0688                      buf[0]);
0689             sf_program(chip, ins, 1, addr, 1);
0690 
0691             retval = rtsx_send_cmd(chip, 0, 100);
0692             if (retval < 0) {
0693                 kfree(buf);
0694                 rtsx_clear_spi_error(chip);
0695                 spi_set_err_code(chip, SPI_HW_ERR);
0696                 return STATUS_FAIL;
0697             }
0698 
0699             retval = sf_polling_status(chip, 100);
0700             if (retval != STATUS_SUCCESS) {
0701                 kfree(buf);
0702                 return STATUS_FAIL;
0703             }
0704 
0705             addr++;
0706             len--;
0707         }
0708 
0709         kfree(buf);
0710 
0711     } else if (program_mode == AAI_PROGRAM) {
0712         int first_byte = 1;
0713 
0714         retval = sf_enable_write(chip, SPI_WREN);
0715         if (retval != STATUS_SUCCESS)
0716             return STATUS_FAIL;
0717 
0718         buf = kmalloc(4, GFP_KERNEL);
0719         if (!buf)
0720             return STATUS_ERROR;
0721 
0722         while (len) {
0723             rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
0724                           FROM_XFER_BUF);
0725 
0726             rtsx_init_cmd(chip);
0727 
0728             rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
0729                      0x01, PINGPONG_BUFFER);
0730             rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
0731                      buf[0]);
0732             if (first_byte) {
0733                 sf_program(chip, ins, 1, addr, 1);
0734                 first_byte = 0;
0735             } else {
0736                 sf_program(chip, ins, 0, 0, 1);
0737             }
0738 
0739             retval = rtsx_send_cmd(chip, 0, 100);
0740             if (retval < 0) {
0741                 kfree(buf);
0742                 rtsx_clear_spi_error(chip);
0743                 spi_set_err_code(chip, SPI_HW_ERR);
0744                 return STATUS_FAIL;
0745             }
0746 
0747             retval = sf_polling_status(chip, 100);
0748             if (retval != STATUS_SUCCESS) {
0749                 kfree(buf);
0750                 return STATUS_FAIL;
0751             }
0752 
0753             len--;
0754         }
0755 
0756         kfree(buf);
0757 
0758         retval = sf_disable_write(chip, SPI_WRDI);
0759         if (retval != STATUS_SUCCESS)
0760             return STATUS_FAIL;
0761 
0762         retval = sf_polling_status(chip, 100);
0763         if (retval != STATUS_SUCCESS)
0764             return STATUS_FAIL;
0765     } else if (program_mode == PAGE_PROGRAM) {
0766         buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
0767         if (!buf)
0768             return STATUS_NOMEM;
0769 
0770         while (len) {
0771             u16 pagelen = SF_PAGE_LEN - (u8)addr;
0772 
0773             if (pagelen > len)
0774                 pagelen = len;
0775 
0776             retval = sf_enable_write(chip, SPI_WREN);
0777             if (retval != STATUS_SUCCESS) {
0778                 kfree(buf);
0779                 return STATUS_FAIL;
0780             }
0781 
0782             rtsx_init_cmd(chip);
0783 
0784             trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
0785             sf_program(chip, ins, 1, addr, pagelen);
0786 
0787             rtsx_send_cmd_no_wait(chip);
0788 
0789             rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
0790                           &offset, FROM_XFER_BUF);
0791 
0792             retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
0793                             DMA_TO_DEVICE, 100);
0794             if (retval < 0) {
0795                 kfree(buf);
0796                 rtsx_clear_spi_error(chip);
0797                 spi_set_err_code(chip, SPI_HW_ERR);
0798                 return STATUS_FAIL;
0799             }
0800 
0801             retval = sf_polling_status(chip, 100);
0802             if (retval != STATUS_SUCCESS) {
0803                 kfree(buf);
0804                 return STATUS_FAIL;
0805             }
0806 
0807             addr += pagelen;
0808             len -= pagelen;
0809         }
0810 
0811         kfree(buf);
0812     } else {
0813         spi_set_err_code(chip, SPI_INVALID_COMMAND);
0814         return STATUS_FAIL;
0815     }
0816 
0817     return STATUS_SUCCESS;
0818 }
0819 
0820 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0821 {
0822     int retval;
0823     u8 ins, erase_mode;
0824     u32 addr;
0825 
0826     spi_set_err_code(chip, SPI_NO_ERR);
0827 
0828     ins = srb->cmnd[3];
0829     addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
0830                     << 8) | srb->cmnd[6];
0831     erase_mode = srb->cmnd[9];
0832 
0833     retval = spi_set_init_para(chip);
0834     if (retval != STATUS_SUCCESS) {
0835         spi_set_err_code(chip, SPI_HW_ERR);
0836         return STATUS_FAIL;
0837     }
0838 
0839     if (erase_mode == PAGE_ERASE) {
0840         retval = sf_enable_write(chip, SPI_WREN);
0841         if (retval != STATUS_SUCCESS)
0842             return STATUS_FAIL;
0843 
0844         retval = sf_erase(chip, ins, 1, addr);
0845         if (retval != STATUS_SUCCESS)
0846             return STATUS_FAIL;
0847     } else if (erase_mode == CHIP_ERASE) {
0848         retval = sf_enable_write(chip, SPI_WREN);
0849         if (retval != STATUS_SUCCESS)
0850             return STATUS_FAIL;
0851 
0852         retval = sf_erase(chip, ins, 0, 0);
0853         if (retval != STATUS_SUCCESS)
0854             return STATUS_FAIL;
0855     } else {
0856         spi_set_err_code(chip, SPI_INVALID_COMMAND);
0857         return STATUS_FAIL;
0858     }
0859 
0860     return STATUS_SUCCESS;
0861 }
0862 
0863 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
0864 {
0865     int retval;
0866     u8 ins, status, ewsr;
0867 
0868     ins = srb->cmnd[3];
0869     status = srb->cmnd[4];
0870     ewsr = srb->cmnd[5];
0871 
0872     retval = spi_set_init_para(chip);
0873     if (retval != STATUS_SUCCESS) {
0874         spi_set_err_code(chip, SPI_HW_ERR);
0875         return STATUS_FAIL;
0876     }
0877 
0878     retval = sf_enable_write(chip, ewsr);
0879     if (retval != STATUS_SUCCESS)
0880         return STATUS_FAIL;
0881 
0882     rtsx_init_cmd(chip);
0883 
0884     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
0885              PINGPONG_BUFFER);
0886 
0887     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
0888     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
0889              SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
0890     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
0891     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
0892     rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
0893     rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
0894              SPI_TRANSFER0_START | SPI_CDO_MODE0);
0895     rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
0896              SPI_TRANSFER0_END);
0897 
0898     retval = rtsx_send_cmd(chip, 0, 100);
0899     if (retval != STATUS_SUCCESS) {
0900         rtsx_clear_spi_error(chip);
0901         spi_set_err_code(chip, SPI_HW_ERR);
0902         return STATUS_FAIL;
0903     }
0904 
0905     return STATUS_SUCCESS;
0906 }
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