staging/rts5208/sd.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Driver for Realtek PCI-Express card reader
0004  *
0005  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0006  *
0007  * Author:
0008  *   Wei WANG (wei_wang@realsil.com.cn)
0009  *   Micky Ching (micky_ching@realsil.com.cn)
0010  */
0011
0012 #ifndef __REALTEK_RTSX_SD_H
0013 #define __REALTEK_RTSX_SD_H
0014
0015 #include "rtsx_chip.h"
0016
0017 #define SUPPORT_VOLTAGE 0x003C0000
0018
0019 /* Error Code */
0020 #define SD_NO_ERROR     0x0
0021 #define SD_CRC_ERR      0x80
0022 #define SD_TO_ERR       0x40
0023 #define SD_NO_CARD      0x20
0024 #define SD_BUSY         0x10
0025 #define SD_STS_ERR      0x08
0026 #define SD_RSP_TIMEOUT      0x04
0027 #define SD_IO_ERR       0x02
0028
0029 /* Return code for MMC switch bus */
0030 #define SWITCH_SUCCESS      0
0031 #define SWITCH_ERR      1
0032 #define SWITCH_FAIL     2
0033
0034 /* MMC/SD Command Index */
0035 /* Basic command (class 0) */
0036 #define GO_IDLE_STATE       0
0037 #define SEND_OP_COND        1
0038 #define ALL_SEND_CID        2
0039 #define SET_RELATIVE_ADDR   3
0040 #define SEND_RELATIVE_ADDR  3
0041 #define SET_DSR         4
0042 #define IO_SEND_OP_COND     5
0043 #define SWITCH          6
0044 #define SELECT_CARD     7
0045 #define DESELECT_CARD       7
0046 /* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec
0047  * while is "SEND_IF_COND" for SD 2.0
0048  */
0049 #define SEND_EXT_CSD        8
0050 #define SEND_IF_COND        8
0051
0052 #define SEND_CSD        9
0053 #define SEND_CID        10
0054 #define VOLTAGE_SWITCH      11
0055 #define READ_DAT_UTIL_STOP  11
0056 #define STOP_TRANSMISSION   12
0057 #define SEND_STATUS     13
0058 #define GO_INACTIVE_STATE   15
0059
0060 #define SET_BLOCKLEN        16
0061 #define READ_SINGLE_BLOCK   17
0062 #define READ_MULTIPLE_BLOCK 18
0063 #define SEND_TUNING_PATTERN 19
0064
0065 #define BUSTEST_R       14
0066 #define BUSTEST_W       19
0067
0068 #define WRITE_BLOCK     24
0069 #define WRITE_MULTIPLE_BLOCK    25
0070 #define PROGRAM_CSD     27
0071
0072 #define ERASE_WR_BLK_START  32
0073 #define ERASE_WR_BLK_END    33
0074 #define ERASE_CMD       38
0075
0076 #define LOCK_UNLOCK     42
0077 #define IO_RW_DIRECT        52
0078
0079 #define APP_CMD         55
0080 #define GEN_CMD         56
0081
0082 #define SET_BUS_WIDTH       6
0083 #define SD_STATUS       13
0084 #define SEND_NUM_WR_BLOCKS  22
0085 #define SET_WR_BLK_ERASE_COUNT  23
0086 #define SD_APP_OP_COND      41
0087 #define SET_CLR_CARD_DETECT 42
0088 #define SEND_SCR        51
0089
0090 #define SD_READ_COMPLETE    0x00
0091 #define SD_READ_TO      0x01
0092 #define SD_READ_ADVENCE     0x02
0093
0094 #define SD_CHECK_MODE       0x00
0095 #define SD_SWITCH_MODE      0x80
0096 #define SD_FUNC_GROUP_1     0x01
0097 #define SD_FUNC_GROUP_2     0x02
0098 #define SD_FUNC_GROUP_3     0x03
0099 #define SD_FUNC_GROUP_4     0x04
0100 #define SD_CHECK_SPEC_V1_1  0xFF
0101
0102 #define NO_ARGUMENT             0x00
0103 #define CHECK_PATTERN               0x000000AA
0104 #define VOLTAGE_SUPPLY_RANGE            0x00000100
0105 #define SUPPORT_HIGH_AND_EXTENDED_CAPACITY  0x40000000
0106 #define SUPPORT_MAX_POWER_PERMANCE      0x10000000
0107 #define SUPPORT_1V8             0x01000000
0108
0109 #define SWITCH_NO_ERR       0x00
0110 #define CARD_NOT_EXIST      0x01
0111 #define SPEC_NOT_SUPPORT    0x02
0112 #define CHECK_MODE_ERR      0x03
0113 #define CHECK_NOT_READY     0x04
0114 #define SWITCH_CRC_ERR      0x05
0115 #define SWITCH_MODE_ERR     0x06
0116 #define SWITCH_PASS     0x07
0117
0118 #ifdef SUPPORT_SD_LOCK
0119 #define SD_ERASE        0x08
0120 #define SD_LOCK         0x04
0121 #define SD_UNLOCK       0x00
0122 #define SD_CLR_PWD      0x02
0123 #define SD_SET_PWD      0x01
0124
0125 #define SD_PWD_LEN      0x10
0126
0127 #define SD_LOCKED       0x80
0128 #define SD_LOCK_1BIT_MODE   0x40
0129 #define SD_PWD_EXIST        0x20
0130 #define SD_UNLOCK_POW_ON    0x01
0131 #define SD_SDR_RST      0x02
0132
0133 #define SD_NOT_ERASE        0x00
0134 #define SD_UNDER_ERASING    0x01
0135 #define SD_COMPLETE_ERASE   0x02
0136
0137 #define SD_RW_FORBIDDEN     0x0F
0138
0139 #endif
0140
0141 #define HS_SUPPORT          0x01
0142 #define SDR50_SUPPORT           0x02
0143 #define SDR104_SUPPORT          0x03
0144 #define DDR50_SUPPORT           0x04
0145
0146 #define HS_SUPPORT_MASK         0x02
0147 #define SDR50_SUPPORT_MASK      0x04
0148 #define SDR104_SUPPORT_MASK     0x08
0149 #define DDR50_SUPPORT_MASK      0x10
0150
0151 #define HS_QUERY_SWITCH_OK      0x01
0152 #define SDR50_QUERY_SWITCH_OK       0x02
0153 #define SDR104_QUERY_SWITCH_OK      0x03
0154 #define DDR50_QUERY_SWITCH_OK       0x04
0155
0156 #define HS_SWITCH_BUSY          0x02
0157 #define SDR50_SWITCH_BUSY       0x04
0158 #define SDR104_SWITCH_BUSY      0x08
0159 #define DDR50_SWITCH_BUSY       0x10
0160
0161 #define FUNCTION_GROUP1_SUPPORT_OFFSET       0x0D
0162 #define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET  0x10
0163 #define FUNCTION_GROUP1_CHECK_BUSY_OFFSET    0x1D
0164
0165 #define DRIVING_TYPE_A      0x01
0166 #define DRIVING_TYPE_B          0x00
0167 #define DRIVING_TYPE_C          0x02
0168 #define DRIVING_TYPE_D      0x03
0169
0170 #define DRIVING_TYPE_A_MASK     0x02
0171 #define DRIVING_TYPE_B_MASK     0x01
0172 #define DRIVING_TYPE_C_MASK     0x04
0173 #define DRIVING_TYPE_D_MASK     0x08
0174
0175 #define TYPE_A_QUERY_SWITCH_OK  0x01
0176 #define TYPE_B_QUERY_SWITCH_OK  0x00
0177 #define TYPE_C_QUERY_SWITCH_OK  0x02
0178 #define TYPE_D_QUERY_SWITCH_OK  0x03
0179
0180 #define TYPE_A_SWITCH_BUSY      0x02
0181 #define TYPE_B_SWITCH_BUSY      0x01
0182 #define TYPE_C_SWITCH_BUSY      0x04
0183 #define TYPE_D_SWITCH_BUSY      0x08
0184
0185 #define FUNCTION_GROUP3_SUPPORT_OFFSET       0x09
0186 #define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET  0x0F
0187 #define FUNCTION_GROUP3_CHECK_BUSY_OFFSET    0x19
0188
0189 #define CURRENT_LIMIT_200       0x00
0190 #define CURRENT_LIMIT_400       0x01
0191 #define CURRENT_LIMIT_600       0x02
0192 #define CURRENT_LIMIT_800       0x03
0193
0194 #define CURRENT_LIMIT_200_MASK  0x01
0195 #define CURRENT_LIMIT_400_MASK  0x02
0196 #define CURRENT_LIMIT_600_MASK  0x04
0197 #define CURRENT_LIMIT_800_MASK  0x08
0198
0199 #define CURRENT_LIMIT_200_QUERY_SWITCH_OK    0x00
0200 #define CURRENT_LIMIT_400_QUERY_SWITCH_OK    0x01
0201 #define CURRENT_LIMIT_600_QUERY_SWITCH_OK    0x02
0202 #define CURRENT_LIMIT_800_QUERY_SWITCH_OK    0x03
0203
0204 #define CURRENT_LIMIT_200_SWITCH_BUSY        0x01
0205 #define CURRENT_LIMIT_400_SWITCH_BUSY        0x02
0206 #define CURRENT_LIMIT_600_SWITCH_BUSY        0x04
0207 #define CURRENT_LIMIT_800_SWITCH_BUSY        0x08
0208
0209 #define FUNCTION_GROUP4_SUPPORT_OFFSET       0x07
0210 #define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET  0x0F
0211 #define FUNCTION_GROUP4_CHECK_BUSY_OFFSET    0x17
0212
0213 #define DATA_STRUCTURE_VER_OFFSET   0x11
0214
0215 #define MAX_PHASE           31
0216
0217 #define MMC_8BIT_BUS            0x0010
0218 #define MMC_4BIT_BUS            0x0020
0219
0220 #define MMC_SWITCH_ERR          0x80
0221
0222 #define SD_IO_3V3       0
0223 #define SD_IO_1V8       1
0224
0225 #define TUNE_TX    0x00
0226 #define TUNE_RX    0x01
0227
0228 #define CHANGE_TX  0x00
0229 #define CHANGE_RX  0x01
0230
0231 #define DCM_HIGH_FREQUENCY_MODE  0x00
0232 #define DCM_LOW_FREQUENCY_MODE   0x01
0233
0234 #define DCM_HIGH_FREQUENCY_MODE_SET  0x0C
0235 #define DCM_LOW_FREQUENCY_MODE_SET   0x00
0236
0237 #define MULTIPLY_BY_1    0x00
0238 #define MULTIPLY_BY_2    0x01
0239 #define MULTIPLY_BY_3    0x02
0240 #define MULTIPLY_BY_4    0x03
0241 #define MULTIPLY_BY_5    0x04
0242 #define MULTIPLY_BY_6    0x05
0243 #define MULTIPLY_BY_7    0x06
0244 #define MULTIPLY_BY_8    0x07
0245 #define MULTIPLY_BY_9    0x08
0246 #define MULTIPLY_BY_10   0x09
0247
0248 #define DIVIDE_BY_2      0x01
0249 #define DIVIDE_BY_3      0x02
0250 #define DIVIDE_BY_4      0x03
0251 #define DIVIDE_BY_5      0x04
0252 #define DIVIDE_BY_6      0x05
0253 #define DIVIDE_BY_7      0x06
0254 #define DIVIDE_BY_8      0x07
0255 #define DIVIDE_BY_9      0x08
0256 #define DIVIDE_BY_10     0x09
0257
0258 struct timing_phase_path {
0259     int start;
0260     int end;
0261     int mid;
0262     int len;
0263 };
0264
0265 int sd_select_card(struct rtsx_chip *chip, int select);
0266 int sd_pull_ctl_enable(struct rtsx_chip *chip);
0267 int reset_sd_card(struct rtsx_chip *chip);
0268 int sd_switch_clock(struct rtsx_chip *chip);
0269 void sd_stop_seq_mode(struct rtsx_chip *chip);
0270 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
0271       u32 start_sector, u16 sector_cnt);
0272 void sd_cleanup_work(struct rtsx_chip *chip);
0273 int sd_power_off_card3v3(struct rtsx_chip *chip);
0274 int release_sd_card(struct rtsx_chip *chip);
0275 #ifdef SUPPORT_CPRM
0276 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
0277                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len,
0278                 bool special_check);
0279 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type);
0280
0281 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip);
0282 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip);
0283 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip);
0284 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip);
0285 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip);
0286 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip);
0287 #endif
0288
0289 #endif  /* __REALTEK_RTSX_SD_H */