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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Driver for Realtek PCI-Express card reader
0004  *
0005  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0006  *
0007  * Author:
0008  *   Wei WANG (wei_wang@realsil.com.cn)
0009  *   Micky Ching (micky_ching@realsil.com.cn)
0010  */
0011 
0012 #ifndef __REALTEK_RTSX_CHIP_H
0013 #define __REALTEK_RTSX_CHIP_H
0014 
0015 #include "rtsx.h"
0016 
0017 #define SUPPORT_CPRM
0018 #define SUPPORT_OCP
0019 #define SUPPORT_SDIO_ASPM
0020 #define SUPPORT_MAGIC_GATE
0021 #define SUPPORT_MSXC
0022 #define SUPPORT_SD_LOCK
0023 /* Hardware switch bus_ctl and cd_ctl automatically */
0024 #define HW_AUTO_SWITCH_SD_BUS
0025 /* Enable hardware interrupt write clear */
0026 #define HW_INT_WRITE_CLR
0027 /* #define LED_AUTO_BLINK */
0028 /* #define DISABLE_CARD_INT */
0029 
0030 #ifdef SUPPORT_MAGIC_GATE
0031     /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */
0032     #define MG_SET_ICV_SLOW
0033     /* HW may miss ERR/CMDNK signal when sampling INT status. */
0034     #define MS_SAMPLE_INT_ERR
0035     /*
0036      * HW DO NOT support Wait_INT function
0037      * during READ_BYTES transfer mode
0038      */
0039     #define READ_BYTES_WAIT_INT
0040 #endif
0041 
0042 #ifdef SUPPORT_MSXC
0043 #define XC_POWERCLASS
0044 #define SUPPORT_PCGL_1P18
0045 #endif
0046 
0047 #ifndef LED_AUTO_BLINK
0048 #define REGULAR_BLINK
0049 #endif
0050 
0051 #define LED_BLINK_SPEED     5
0052 #define LED_TOGGLE_INTERVAL 6
0053 #define GPIO_TOGGLE_THRESHOLD   1024
0054 #define LED_GPIO        0
0055 
0056 #define POLLING_INTERVAL    30
0057 
0058 #define TRACE_ITEM_CNT      64
0059 
0060 #ifndef STATUS_SUCCESS
0061 #define STATUS_SUCCESS      0
0062 #endif
0063 #ifndef STATUS_FAIL
0064 #define STATUS_FAIL     1
0065 #endif
0066 #ifndef STATUS_TIMEDOUT
0067 #define STATUS_TIMEDOUT     2
0068 #endif
0069 #ifndef STATUS_NOMEM
0070 #define STATUS_NOMEM        3
0071 #endif
0072 #ifndef STATUS_READ_FAIL
0073 #define STATUS_READ_FAIL    4
0074 #endif
0075 #ifndef STATUS_WRITE_FAIL
0076 #define STATUS_WRITE_FAIL   5
0077 #endif
0078 #ifndef STATUS_ERROR
0079 #define STATUS_ERROR        10
0080 #endif
0081 
0082 #define PM_S1           1
0083 #define PM_S3           3
0084 
0085 /*
0086  * Transport return codes
0087  */
0088 
0089 #define TRANSPORT_GOOD      0   /* Transport good, command good    */
0090 #define TRANSPORT_FAILED    1   /* Transport good, command failed   */
0091 #define TRANSPORT_NO_SENSE  2  /* Command failed, no auto-sense    */
0092 #define TRANSPORT_ERROR     3   /* Transport bad (i.e. device dead) */
0093 
0094 /*
0095  * Start-Stop-Unit
0096  */
0097 #define STOP_MEDIUM         0x00    /* access disable         */
0098 #define MAKE_MEDIUM_READY       0x01    /* access enable          */
0099 #define UNLOAD_MEDIUM           0x02    /* unload                 */
0100 #define LOAD_MEDIUM         0x03    /* load                   */
0101 
0102 /*
0103  * STANDARD_INQUIRY
0104  */
0105 #define QULIFIRE                0x00
0106 #define AENC_FNC                0x00
0107 #define TRML_IOP                0x00
0108 #define REL_ADR                 0x00
0109 #define WBUS_32                 0x00
0110 #define WBUS_16                 0x00
0111 #define SYNC                    0x00
0112 #define LINKED                  0x00
0113 #define CMD_QUE                 0x00
0114 #define SFT_RE                  0x00
0115 
0116 #define VEN_ID_LEN              8               /* Vendor ID Length         */
0117 #define PRDCT_ID_LEN            16              /* Product ID Length        */
0118 #define PRDCT_REV_LEN           4               /* Product LOT Length       */
0119 
0120 /* Dynamic flag definitions: used in set_bit() etc. */
0121 /* 0x00040000 transfer is active */
0122 #define RTSX_FLIDX_TRANS_ACTIVE     18
0123 /* 0x00100000 abort is in progress */
0124 #define RTSX_FLIDX_ABORTING     20
0125 /* 0x00200000 disconnect in progress */
0126 #define RTSX_FLIDX_DISCONNECTING    21
0127 
0128 #define ABORTING_OR_DISCONNECTING   ((1UL << US_FLIDX_ABORTING) | \
0129                      (1UL << US_FLIDX_DISCONNECTING))
0130 
0131 /* 0x00400000 device reset in progress */
0132 #define RTSX_FLIDX_RESETTING        22
0133 /* 0x00800000 SCSI midlayer timed out  */
0134 #define RTSX_FLIDX_TIMED_OUT        23
0135 #define DRCT_ACCESS_DEV         0x00    /* Direct Access Device      */
0136 #define RMB_DISC                0x80    /* The Device is Removable   */
0137 #define ANSI_SCSI2              0x02    /* Based on ANSI-SCSI2       */
0138 
0139 #define SCSI                    0x00    /* Interface ID              */
0140 
0141 #define WRITE_PROTECTED_MEDIA 0x07
0142 
0143 /*---- sense key ----*/
0144 #define ILI                     0x20    /* ILI bit is on                    */
0145 
0146 #define NO_SENSE                0x00    /* not exist sense key              */
0147 #define RECOVER_ERR             0x01    /* Target/Logical unit is recoverd  */
0148 #define NOT_READY               0x02    /* Logical unit is not ready        */
0149 #define MEDIA_ERR               0x03    /* medium/data error                */
0150 #define HARDWARE_ERR            0x04    /* hardware error                   */
0151 #define ILGAL_REQ               0x05    /* CDB/parameter/identify msg error */
0152 #define UNIT_ATTENTION          0x06    /* unit attention condition occur   */
0153 #define DAT_PRTCT               0x07    /* read/write is desable            */
0154 #define BLNC_CHK                0x08    /* find blank/DOF in read           */
0155                     /* write to unblank area            */
0156 #define CPY_ABRT                0x0a    /* Copy/Compare/Copy&Verify illegal */
0157 #define ABRT_CMD                0x0b    /* Target make the command in error */
0158 #define EQUAL                   0x0c    /* Search Data end with Equal       */
0159 #define VLM_OVRFLW              0x0d    /* Some data are left in buffer     */
0160 #define MISCMP                  0x0e    /* find inequality                  */
0161 
0162 #define READ_ERR                -1
0163 #define WRITE_ERR               -2
0164 
0165 #define FIRST_RESET     0x01
0166 #define USED_EXIST      0x02
0167 
0168 /*
0169  * SENSE_DATA
0170  */
0171 /*---- valid ----*/
0172 #define SENSE_VALID             0x80    /* Sense data is valid as SCSI2     */
0173 #define SENSE_INVALID           0x00    /* Sense data is invalid as SCSI2   */
0174 
0175 /*---- error code ----*/
0176 #define CUR_ERR                 0x70    /* current error                    */
0177 #define DEF_ERR                 0x71    /* specific command error           */
0178 
0179 /*---- sense key Information ----*/
0180 #define SNSKEYINFO_LEN          3       /* length of sense key information   */
0181 
0182 #define SKSV                    0x80
0183 #define CDB_ILLEGAL             0x40
0184 #define DAT_ILLEGAL             0x00
0185 #define BPV                     0x08
0186 #define BIT_ILLEGAL0            0       /* bit0 is illegal                  */
0187 #define BIT_ILLEGAL1            1       /* bit1 is illegal                  */
0188 #define BIT_ILLEGAL2            2       /* bit2 is illegal                  */
0189 #define BIT_ILLEGAL3            3       /* bit3 is illegal                  */
0190 #define BIT_ILLEGAL4            4       /* bit4 is illegal                  */
0191 #define BIT_ILLEGAL5            5       /* bit5 is illegal                  */
0192 #define BIT_ILLEGAL6            6       /* bit6 is illegal                  */
0193 #define BIT_ILLEGAL7            7       /* bit7 is illegal                  */
0194 
0195 /*---- ASC ----*/
0196 #define ASC_NO_INFO             0x00
0197 #define ASC_MISCMP              0x1d
0198 #define ASC_INVLD_CDB           0x24
0199 #define ASC_INVLD_PARA          0x26
0200 #define ASC_LU_NOT_READY    0x04
0201 #define ASC_WRITE_ERR           0x0c
0202 #define ASC_READ_ERR            0x11
0203 #define ASC_LOAD_EJCT_ERR       0x53
0204 #define ASC_MEDIA_NOT_PRESENT   0x3A
0205 #define ASC_MEDIA_CHANGED   0x28
0206 #define ASC_MEDIA_IN_PROCESS    0x04
0207 #define ASC_WRITE_PROTECT   0x27
0208 #define ASC_LUN_NOT_SUPPORTED   0x25
0209 
0210 /*---- ASQC ----*/
0211 #define ASCQ_NO_INFO            0x00
0212 #define ASCQ_MEDIA_IN_PROCESS   0x01
0213 #define ASCQ_MISCMP             0x00
0214 #define ASCQ_INVLD_CDB          0x00
0215 #define ASCQ_INVLD_PARA         0x02
0216 #define ASCQ_LU_NOT_READY   0x02
0217 #define ASCQ_WRITE_ERR          0x02
0218 #define ASCQ_READ_ERR           0x00
0219 #define ASCQ_LOAD_EJCT_ERR      0x00
0220 #define ASCQ_WRITE_PROTECT  0x00
0221 
0222 struct sense_data_t {
0223     unsigned char   err_code;   /* error code */
0224     /* bit7 : valid */
0225     /*   (1 : SCSI2) */
0226     /*   (0 : Vendor * specific) */
0227     /* bit6-0 : error * code */
0228     /*  (0x70 : current * error) */
0229     /*  (0x71 : specific command error) */
0230     unsigned char   seg_no;     /* segment No.                      */
0231     unsigned char   sense_key;  /* byte5 : ILI                      */
0232     /* bit3-0 : sense key              */
0233     unsigned char   info[4];    /* information                       */
0234     unsigned char   ad_sense_len;   /* additional sense data length     */
0235     unsigned char   cmd_info[4];    /* command specific information      */
0236     unsigned char   asc;        /* ASC                              */
0237     unsigned char   ascq;       /* ASCQ                             */
0238     unsigned char   rfu;        /* FRU                              */
0239     unsigned char   sns_key_info[3];/* sense key specific information    */
0240 };
0241 
0242 /* PCI Operation Register Address */
0243 #define RTSX_HCBAR      0x00
0244 #define RTSX_HCBCTLR        0x04
0245 #define RTSX_HDBAR      0x08
0246 #define RTSX_HDBCTLR        0x0C
0247 #define RTSX_HAIMR      0x10
0248 #define RTSX_BIPR       0x14
0249 #define RTSX_BIER       0x18
0250 
0251 /* Host command buffer control register */
0252 #define STOP_CMD        (0x01 << 28)
0253 
0254 /* Host data buffer control register */
0255 #define SDMA_MODE       0x00
0256 #define ADMA_MODE       (0x02 << 26)
0257 #define STOP_DMA        (0x01 << 28)
0258 #define TRIG_DMA        (0x01 << 31)
0259 
0260 /* Bus interrupt pending register */
0261 #define CMD_DONE_INT        BIT(31)
0262 #define DATA_DONE_INT       BIT(30)
0263 #define TRANS_OK_INT        BIT(29)
0264 #define TRANS_FAIL_INT      BIT(28)
0265 #define XD_INT          BIT(27)
0266 #define MS_INT          BIT(26)
0267 #define SD_INT          BIT(25)
0268 #define GPIO0_INT       BIT(24)
0269 #define OC_INT          BIT(23)
0270 #define SD_WRITE_PROTECT    BIT(19)
0271 #define XD_EXIST        BIT(18)
0272 #define MS_EXIST        BIT(17)
0273 #define SD_EXIST        BIT(16)
0274 #define DELINK_INT      GPIO0_INT
0275 #define MS_OC_INT       BIT(23)
0276 #define SD_OC_INT       BIT(22)
0277 
0278 #define CARD_INT        (XD_INT | MS_INT | SD_INT)
0279 #define NEED_COMPLETE_INT   (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
0280 #define RTSX_INT        (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | \
0281                  GPIO0_INT | OC_INT)
0282 
0283 #define CARD_EXIST      (XD_EXIST | MS_EXIST | SD_EXIST)
0284 
0285 /* Bus interrupt enable register */
0286 #define CMD_DONE_INT_EN     BIT(31)
0287 #define DATA_DONE_INT_EN    BIT(30)
0288 #define TRANS_OK_INT_EN     BIT(29)
0289 #define TRANS_FAIL_INT_EN   BIT(28)
0290 #define XD_INT_EN       BIT(27)
0291 #define MS_INT_EN       BIT(26)
0292 #define SD_INT_EN       BIT(25)
0293 #define GPIO0_INT_EN        BIT(24)
0294 #define OC_INT_EN       BIT(23)
0295 #define DELINK_INT_EN       GPIO0_INT_EN
0296 #define MS_OC_INT_EN        BIT(23)
0297 #define SD_OC_INT_EN        BIT(22)
0298 
0299 #define READ_REG_CMD        0
0300 #define WRITE_REG_CMD       1
0301 #define CHECK_REG_CMD       2
0302 
0303 #define HOST_TO_DEVICE      0
0304 #define DEVICE_TO_HOST      1
0305 
0306 #define RTSX_RESV_BUF_LEN   4096
0307 #define HOST_CMDS_BUF_LEN   1024
0308 #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
0309 
0310 #define SD_NR       2
0311 #define MS_NR       3
0312 #define XD_NR       4
0313 #define SPI_NR      7
0314 #define SD_CARD     BIT(SD_NR)
0315 #define MS_CARD     BIT(MS_NR)
0316 #define XD_CARD     BIT(XD_NR)
0317 #define SPI_CARD    BIT(SPI_NR)
0318 
0319 #define MAX_ALLOWED_LUN_CNT 8
0320 
0321 #define XD_FREE_TABLE_CNT   1200
0322 #define MS_FREE_TABLE_CNT   512
0323 
0324 /* Bit Operation */
0325 #define SET_BIT(data, idx)  ((data) |= 1 << (idx))
0326 #define CLR_BIT(data, idx)  ((data) &= ~(1 << (idx)))
0327 #define CHK_BIT(data, idx)  ((data) & (1 << (idx)))
0328 
0329 /* SG descriptor */
0330 #define RTSX_SG_INT     0x04
0331 #define RTSX_SG_END     0x02
0332 #define RTSX_SG_VALID       0x01
0333 
0334 #define RTSX_SG_NO_OP       0x00
0335 #define RTSX_SG_TRANS_DATA  (0x02 << 4)
0336 #define RTSX_SG_LINK_DESC   (0x03 << 4)
0337 
0338 struct rtsx_chip;
0339 
0340 typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip,
0341             u32 sec_addr, u16 sec_cnt);
0342 
0343 /* Supported Clock */
0344 enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60,
0345          CLK_80, CLK_100, CLK_120, CLK_150, CLK_200};
0346 
0347 enum RTSX_STAT  {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS,
0348          RTSX_STAT_DELINK, RTSX_STAT_SUSPEND,
0349          RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT};
0350 enum IC_VER {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3};
0351 
0352 #define MAX_RESET_CNT       3
0353 
0354 /* For MS Card */
0355 #define MAX_DEFECTIVE_BLOCK     10
0356 
0357 struct zone_entry {
0358     u16 *l2p_table;
0359     u16 *free_table;
0360     u16 defect_list[MAX_DEFECTIVE_BLOCK];  /* For MS card only */
0361     int set_index;
0362     int get_index;
0363     int unused_blk_cnt;
0364     int disable_count;
0365     /* To indicate whether the L2P table of this zone has been built. */
0366     int build_flag;
0367 };
0368 
0369 #define TYPE_SD         0x0000
0370 #define TYPE_MMC        0x0001
0371 
0372 /* TYPE_SD */
0373 #define SD_HS           0x0100
0374 #define SD_SDR50        0x0200
0375 #define SD_DDR50        0x0400
0376 #define SD_SDR104       0x0800
0377 #define SD_HCXC         0x1000
0378 
0379 /* TYPE_MMC */
0380 #define MMC_26M         0x0100
0381 #define MMC_52M         0x0200
0382 #define MMC_4BIT        0x0400
0383 #define MMC_8BIT        0x0800
0384 #define MMC_SECTOR_MODE     0x1000
0385 #define MMC_DDR52       0x2000
0386 
0387 /* SD card */
0388 #define CHK_SD(sd_card)         (((sd_card)->sd_type & 0xFF) == TYPE_SD)
0389 #define CHK_SD_HS(sd_card)      (CHK_SD(sd_card) && \
0390                      ((sd_card)->sd_type & SD_HS))
0391 #define CHK_SD_SDR50(sd_card)       (CHK_SD(sd_card) && \
0392                      ((sd_card)->sd_type & SD_SDR50))
0393 #define CHK_SD_DDR50(sd_card)       (CHK_SD(sd_card) && \
0394                      ((sd_card)->sd_type & SD_DDR50))
0395 #define CHK_SD_SDR104(sd_card)      (CHK_SD(sd_card) && \
0396                      ((sd_card)->sd_type & SD_SDR104))
0397 #define CHK_SD_HCXC(sd_card)        (CHK_SD(sd_card) && \
0398                      ((sd_card)->sd_type & SD_HCXC))
0399 #define CHK_SD_HC(sd_card)      (CHK_SD_HCXC(sd_card) && \
0400                      ((sd_card)->capacity <= 0x4000000))
0401 #define CHK_SD_XC(sd_card)      (CHK_SD_HCXC(sd_card) && \
0402                      ((sd_card)->capacity > 0x4000000))
0403 #define CHK_SD30_SPEED(sd_card)     (CHK_SD_SDR50(sd_card) || \
0404                      CHK_SD_DDR50(sd_card) || \
0405                      CHK_SD_SDR104(sd_card))
0406 
0407 #define SET_SD(sd_card)         ((sd_card)->sd_type = TYPE_SD)
0408 #define SET_SD_HS(sd_card)      ((sd_card)->sd_type |= SD_HS)
0409 #define SET_SD_SDR50(sd_card)       ((sd_card)->sd_type |= SD_SDR50)
0410 #define SET_SD_DDR50(sd_card)       ((sd_card)->sd_type |= SD_DDR50)
0411 #define SET_SD_SDR104(sd_card)      ((sd_card)->sd_type |= SD_SDR104)
0412 #define SET_SD_HCXC(sd_card)        ((sd_card)->sd_type |= SD_HCXC)
0413 
0414 #define CLR_SD_HS(sd_card)      ((sd_card)->sd_type &= ~SD_HS)
0415 #define CLR_SD_SDR50(sd_card)       ((sd_card)->sd_type &= ~SD_SDR50)
0416 #define CLR_SD_DDR50(sd_card)       ((sd_card)->sd_type &= ~SD_DDR50)
0417 #define CLR_SD_SDR104(sd_card)      ((sd_card)->sd_type &= ~SD_SDR104)
0418 #define CLR_SD_HCXC(sd_card)        ((sd_card)->sd_type &= ~SD_HCXC)
0419 
0420 /* MMC card */
0421 #define CHK_MMC(sd_card)        (((sd_card)->sd_type & 0xFF) == \
0422                      TYPE_MMC)
0423 #define CHK_MMC_26M(sd_card)        (CHK_MMC(sd_card) && \
0424                      ((sd_card)->sd_type & MMC_26M))
0425 #define CHK_MMC_52M(sd_card)        (CHK_MMC(sd_card) && \
0426                      ((sd_card)->sd_type & MMC_52M))
0427 #define CHK_MMC_4BIT(sd_card)       (CHK_MMC(sd_card) && \
0428                      ((sd_card)->sd_type & MMC_4BIT))
0429 #define CHK_MMC_8BIT(sd_card)       (CHK_MMC(sd_card) && \
0430                      ((sd_card)->sd_type & MMC_8BIT))
0431 #define CHK_MMC_SECTOR_MODE(sd_card)    (CHK_MMC(sd_card) && \
0432                      ((sd_card)->sd_type & MMC_SECTOR_MODE))
0433 #define CHK_MMC_DDR52(sd_card)      (CHK_MMC(sd_card) && \
0434                      ((sd_card)->sd_type & MMC_DDR52))
0435 
0436 #define SET_MMC(sd_card)        ((sd_card)->sd_type = TYPE_MMC)
0437 #define SET_MMC_26M(sd_card)        ((sd_card)->sd_type |= MMC_26M)
0438 #define SET_MMC_52M(sd_card)        ((sd_card)->sd_type |= MMC_52M)
0439 #define SET_MMC_4BIT(sd_card)       ((sd_card)->sd_type |= MMC_4BIT)
0440 #define SET_MMC_8BIT(sd_card)       ((sd_card)->sd_type |= MMC_8BIT)
0441 #define SET_MMC_SECTOR_MODE(sd_card)    ((sd_card)->sd_type |= MMC_SECTOR_MODE)
0442 #define SET_MMC_DDR52(sd_card)      ((sd_card)->sd_type |= MMC_DDR52)
0443 
0444 #define CLR_MMC_26M(sd_card)        ((sd_card)->sd_type &= ~MMC_26M)
0445 #define CLR_MMC_52M(sd_card)        ((sd_card)->sd_type &= ~MMC_52M)
0446 #define CLR_MMC_4BIT(sd_card)       ((sd_card)->sd_type &= ~MMC_4BIT)
0447 #define CLR_MMC_8BIT(sd_card)       ((sd_card)->sd_type &= ~MMC_8BIT)
0448 #define CLR_MMC_SECTOR_MODE(sd_card)    ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
0449 #define CLR_MMC_DDR52(sd_card)      ((sd_card)->sd_type &= ~MMC_DDR52)
0450 
0451 #define CHK_MMC_HS(sd_card)     (CHK_MMC_52M(sd_card) && \
0452                      CHK_MMC_26M(sd_card))
0453 #define CLR_MMC_HS(sd_card)         \
0454 do {                        \
0455     CLR_MMC_DDR52(sd_card);         \
0456     CLR_MMC_52M(sd_card);           \
0457     CLR_MMC_26M(sd_card);           \
0458 } while (0)
0459 
0460 #define SD_SUPPORT_CLASS_TEN        0x01
0461 #define SD_SUPPORT_1V8          0x02
0462 
0463 #define SD_SET_CLASS_TEN(sd_card)   ((sd_card)->sd_setting |= \
0464                      SD_SUPPORT_CLASS_TEN)
0465 #define SD_CHK_CLASS_TEN(sd_card)   ((sd_card)->sd_setting & \
0466                      SD_SUPPORT_CLASS_TEN)
0467 #define SD_CLR_CLASS_TEN(sd_card)   ((sd_card)->sd_setting &= \
0468                      ~SD_SUPPORT_CLASS_TEN)
0469 #define SD_SET_1V8(sd_card)     ((sd_card)->sd_setting |= \
0470                      SD_SUPPORT_1V8)
0471 #define SD_CHK_1V8(sd_card)     ((sd_card)->sd_setting & \
0472                      SD_SUPPORT_1V8)
0473 #define SD_CLR_1V8(sd_card)     ((sd_card)->sd_setting &= \
0474                      ~SD_SUPPORT_1V8)
0475 
0476 struct sd_info {
0477     u16 sd_type;
0478     u8 err_code;
0479     u8 sd_data_buf_ready;
0480     u32 sd_addr;
0481     u32 capacity;
0482 
0483     u8 raw_csd[16];
0484     u8 raw_scr[8];
0485 
0486     /* Sequential RW */
0487     int seq_mode;
0488     enum dma_data_direction pre_dir;
0489     u32 pre_sec_addr;
0490     u16 pre_sec_cnt;
0491 
0492     int cleanup_counter;
0493 
0494     int sd_clock;
0495 
0496     int mmc_dont_switch_bus;
0497 
0498 #ifdef SUPPORT_CPRM
0499     int sd_pass_thru_en;
0500     int pre_cmd_err;
0501     u8 last_rsp_type;
0502     u8 rsp[17];
0503 #endif
0504 
0505     u8 func_group1_mask;
0506     u8 func_group2_mask;
0507     u8 func_group3_mask;
0508     u8 func_group4_mask;
0509 
0510     u8 sd_switch_fail;
0511     u8 sd_read_phase;
0512 
0513 #ifdef SUPPORT_SD_LOCK
0514     u8 sd_lock_status;
0515     u8 sd_erase_status;
0516     u8 sd_lock_notify;
0517 #endif
0518     int need_retune;
0519 };
0520 
0521 struct xd_delay_write_tag {
0522     u32 old_phyblock;
0523     u32 new_phyblock;
0524     u32 logblock;
0525     u8 pageoff;
0526     u8 delay_write_flag;
0527 };
0528 
0529 struct xd_info {
0530     u8 maker_code;
0531     u8 device_code;
0532     u8 block_shift;
0533     u8 page_off;
0534     u8 addr_cycle;
0535     u16 cis_block;
0536     u8 multi_flag;
0537     u8 err_code;
0538     u32 capacity;
0539 
0540     struct zone_entry *zone;
0541     int zone_cnt;
0542 
0543     struct xd_delay_write_tag delay_write;
0544     int cleanup_counter;
0545 
0546     int xd_clock;
0547 };
0548 
0549 #define MODE_512_SEQ        0x01
0550 #define MODE_2K_SEQ     0x02
0551 
0552 #define TYPE_MS         0x0000
0553 #define TYPE_MSPRO      0x0001
0554 
0555 #define MS_4BIT         0x0100
0556 #define MS_8BIT         0x0200
0557 #define MS_HG           0x0400
0558 #define MS_XC           0x0800
0559 
0560 #define HG8BIT          (MS_HG | MS_8BIT)
0561 
0562 #define CHK_MSPRO(ms_card)  (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
0563 #define CHK_HG8BIT(ms_card) (CHK_MSPRO(ms_card) && \
0564                  (((ms_card)->ms_type & HG8BIT) == HG8BIT))
0565 #define CHK_MSXC(ms_card)   (CHK_MSPRO(ms_card) && \
0566                  ((ms_card)->ms_type & MS_XC))
0567 #define CHK_MSHG(ms_card)   (CHK_MSPRO(ms_card) && \
0568                  ((ms_card)->ms_type & MS_HG))
0569 
0570 #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT))
0571 #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT))
0572 
0573 struct ms_delay_write_tag {
0574     u16 old_phyblock;
0575     u16 new_phyblock;
0576     u16 logblock;
0577     u8 pageoff;
0578     u8 delay_write_flag;
0579 };
0580 
0581 struct ms_info {
0582     u16 ms_type;
0583     u8 block_shift;
0584     u8 page_off;
0585     u16 total_block;
0586     u16 boot_block;
0587     u32 capacity;
0588 
0589     u8 check_ms_flow;
0590     u8 switch_8bit_fail;
0591     u8 err_code;
0592 
0593     struct zone_entry *segment;
0594     int segment_cnt;
0595 
0596     int pro_under_formatting;
0597     int format_status;
0598     u16 progress;
0599     u8 raw_sys_info[96];
0600 #ifdef SUPPORT_PCGL_1P18
0601     u8 raw_model_name[48];
0602 #endif
0603 
0604     u8 multi_flag;
0605 
0606     /* Sequential RW */
0607     u8 seq_mode;
0608     enum dma_data_direction pre_dir;
0609     u32 pre_sec_addr;
0610     u16 pre_sec_cnt;
0611     u32 total_sec_cnt;
0612 
0613     struct ms_delay_write_tag delay_write;
0614 
0615     int cleanup_counter;
0616 
0617     int ms_clock;
0618 
0619 #ifdef SUPPORT_MAGIC_GATE
0620     u8 magic_gate_id[16];
0621     u8 mg_entry_num;
0622     int mg_auth;    /* flag to indicate authentication process */
0623 #endif
0624 };
0625 
0626 struct spi_info {
0627     u8 use_clk;
0628     u8 write_en;
0629     u16 clk_div;
0630     u8 err_code;
0631 
0632     int spi_clock;
0633 };
0634 
0635 /************/
0636 /* LUN mode */
0637 /************/
0638 /* Single LUN, support xD/SD/MS */
0639 #define DEFAULT_SINGLE      0
0640 /* 2 LUN mode, support SD/MS */
0641 #define SD_MS_2LUN      1
0642 /* Single LUN, but only support SD/MS, for Barossa LQFP */
0643 #define SD_MS_1LUN      2
0644 
0645 #define LAST_LUN_MODE       2
0646 
0647 /* Barossa package */
0648 #define QFN     0
0649 #define LQFP        1
0650 
0651 /******************/
0652 /* sd_ctl bit map */
0653 /******************/
0654 /* SD push point control, bit 0, 1 */
0655 #define SD_PUSH_POINT_CTL_MASK      0x03
0656 #define SD_PUSH_POINT_DELAY     0x01
0657 #define SD_PUSH_POINT_AUTO      0x02
0658 /* SD sample point control, bit 2, 3 */
0659 #define SD_SAMPLE_POINT_CTL_MASK    0x0C
0660 #define SD_SAMPLE_POINT_DELAY       0x04
0661 #define SD_SAMPLE_POINT_AUTO        0x08
0662 /* SD DDR Tx phase set by user, bit 4 */
0663 #define SD_DDR_TX_PHASE_SET_BY_USER 0x10
0664 /* MMC DDR Tx phase set by user, bit 5 */
0665 #define MMC_DDR_TX_PHASE_SET_BY_USER    0x20
0666 /* Support MMC DDR mode, bit 6 */
0667 #define SUPPORT_MMC_DDR_MODE        0x40
0668 /* Reset MMC at first */
0669 #define RESET_MMC_FIRST         0x80
0670 
0671 #define SEQ_START_CRITERIA      0x20
0672 
0673 /* MS Power Class En */
0674 #define POWER_CLASS_2_EN        0x02
0675 #define POWER_CLASS_1_EN        0x01
0676 
0677 #define MAX_SHOW_CNT            10
0678 #define MAX_RESET_CNT           3
0679 
0680 #define SDIO_EXIST          0x01
0681 #define SDIO_IGNORED            0x02
0682 
0683 #define CHK_SDIO_EXIST(chip)        ((chip)->sdio_func_exist & SDIO_EXIST)
0684 #define SET_SDIO_EXIST(chip)        ((chip)->sdio_func_exist |= SDIO_EXIST)
0685 #define CLR_SDIO_EXIST(chip)        ((chip)->sdio_func_exist &= ~SDIO_EXIST)
0686 
0687 #define CHK_SDIO_IGNORED(chip)      ((chip)->sdio_func_exist & SDIO_IGNORED)
0688 #define SET_SDIO_IGNORED(chip)      ((chip)->sdio_func_exist |= \
0689                      SDIO_IGNORED)
0690 #define CLR_SDIO_IGNORED(chip)      ((chip)->sdio_func_exist &= \
0691                      ~SDIO_IGNORED)
0692 
0693 struct rtsx_chip {
0694     struct rtsx_dev *rtsx;
0695 
0696     u32     int_reg; /* Bus interrupt pending register */
0697     char        max_lun;
0698     void        *context;
0699 
0700     void        *host_cmds_ptr; /* host commands buffer pointer */
0701     dma_addr_t  host_cmds_addr;
0702     int     ci;         /* Command Index */
0703 
0704     void        *host_sg_tbl_ptr;   /* SG descriptor table */
0705     dma_addr_t  host_sg_tbl_addr;
0706     int     sgi;            /* SG entry index */
0707 
0708     struct scsi_cmnd    *srb;           /* current srb */
0709     struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT];
0710 
0711     int         cur_clk;        /* current card clock */
0712 
0713     /* Current accessed card */
0714     int         cur_card;
0715 
0716     unsigned long   need_release;       /* need release bit map */
0717     unsigned long   need_reset;     /* need reset bit map */
0718     /*
0719      * Flag to indicate that this card is just resumed from SS state,
0720      * and need released before being resetted
0721      */
0722     unsigned long       need_reinit;
0723 
0724     int         rw_need_retry;
0725 
0726 #ifdef SUPPORT_OCP
0727     u32         ocp_int;
0728     u8          ocp_stat;
0729 #endif
0730 
0731     u8  card_exist; /* card exist bit map (physical exist) */
0732     u8  card_ready; /* card ready bit map (reset successfully) */
0733     u8  card_fail;  /* card reset fail bit map */
0734     u8  card_ejected;   /* card ejected bit map */
0735     u8  card_wp;    /* card write protected bit map */
0736 
0737     u8  lun_mc;     /*
0738                  * flag to indicate whether to answer
0739                  * MediaChange
0740                  */
0741 
0742 #ifndef LED_AUTO_BLINK
0743     int         led_toggle_counter;
0744 #endif
0745 
0746     int         sd_reset_counter;
0747     int         xd_reset_counter;
0748     int         ms_reset_counter;
0749 
0750     /* card bus width */
0751     u8          card_bus_width[MAX_ALLOWED_LUN_CNT];
0752     /* card capacity */
0753     u32         capacity[MAX_ALLOWED_LUN_CNT];
0754     /* read/write card function pointer */
0755     card_rw_func        rw_card[MAX_ALLOWED_LUN_CNT];
0756     /* read/write capacity, used for GPIO Toggle */
0757     u32         rw_cap[MAX_ALLOWED_LUN_CNT];
0758     /* card to lun mapping table */
0759     u8          card2lun[32];
0760     /* lun to card mapping table */
0761     u8          lun2card[MAX_ALLOWED_LUN_CNT];
0762 
0763     int         rw_fail_cnt[MAX_ALLOWED_LUN_CNT];
0764 
0765     int         sd_show_cnt;
0766     int         xd_show_cnt;
0767     int         ms_show_cnt;
0768 
0769     /* card information */
0770     struct sd_info      sd_card;
0771     struct xd_info      xd_card;
0772     struct ms_info      ms_card;
0773 
0774     struct spi_info     spi;
0775 
0776     int         auto_delink_cnt;
0777     int         auto_delink_allowed;
0778 
0779     int         aspm_enabled;
0780 
0781     int         sdio_aspm;
0782     int         sdio_idle;
0783     int         sdio_counter;
0784     u8          sdio_raw_data[12];
0785 
0786     u8          sd_io;
0787     u8          sd_int;
0788 
0789     u8          rtsx_flag;
0790 
0791     int         ss_counter;
0792     int         idle_counter;
0793     enum RTSX_STAT      rtsx_stat;
0794 
0795     u16         vendor_id;
0796     u16         product_id;
0797     u8          ic_version;
0798 
0799     int         driver_first_load;
0800 
0801 #ifdef HW_AUTO_SWITCH_SD_BUS
0802     int         sdio_in_charge;
0803 #endif
0804 
0805     u8          aspm_level[2];
0806 
0807     int         chip_insert_with_sdio;
0808 
0809     /* Options */
0810 
0811     int adma_mode;
0812 
0813     int auto_delink_en;
0814     int ss_en;
0815     u8 lun_mode;
0816     u8 aspm_l0s_l1_en;
0817 
0818     int power_down_in_ss;
0819 
0820     int sdr104_en;
0821     int ddr50_en;
0822     int sdr50_en;
0823 
0824     int baro_pkg;
0825 
0826     int asic_code;
0827     int phy_debug_mode;
0828     int hw_bypass_sd;
0829     int sdio_func_exist;
0830     int aux_pwr_exist;
0831     u8 ms_power_class_en;
0832 
0833     int mspro_formatter_enable;
0834 
0835     int remote_wakeup_en;
0836 
0837     int ignore_sd;
0838     int use_hw_setting;
0839 
0840     int ss_idle_period;
0841 
0842     int dynamic_aspm;
0843 
0844     int fpga_sd_sdr104_clk;
0845     int fpga_sd_ddr50_clk;
0846     int fpga_sd_sdr50_clk;
0847     int fpga_sd_hs_clk;
0848     int fpga_mmc_52m_clk;
0849     int fpga_ms_hg_clk;
0850     int fpga_ms_4bit_clk;
0851     int fpga_ms_1bit_clk;
0852 
0853     int asic_sd_sdr104_clk;
0854     int asic_sd_ddr50_clk;
0855     int asic_sd_sdr50_clk;
0856     int asic_sd_hs_clk;
0857     int asic_mmc_52m_clk;
0858     int asic_ms_hg_clk;
0859     int asic_ms_4bit_clk;
0860     int asic_ms_1bit_clk;
0861 
0862     u8 ssc_depth_sd_sdr104;
0863     u8 ssc_depth_sd_ddr50;
0864     u8 ssc_depth_sd_sdr50;
0865     u8 ssc_depth_sd_hs;
0866     u8 ssc_depth_mmc_52m;
0867     u8 ssc_depth_ms_hg;
0868     u8 ssc_depth_ms_4bit;
0869     u8 ssc_depth_low_speed;
0870 
0871     u8 card_drive_sel;
0872     u8 sd30_drive_sel_1v8;
0873     u8 sd30_drive_sel_3v3;
0874 
0875     u8 sd_400mA_ocp_thd;
0876     u8 sd_800mA_ocp_thd;
0877     u8 ms_ocp_thd;
0878 
0879     int ssc_en;
0880     int msi_en;
0881 
0882     int xd_timeout;
0883     int sd_timeout;
0884     int ms_timeout;
0885     int mspro_timeout;
0886 
0887     int auto_power_down;
0888 
0889     int sd_ddr_tx_phase;
0890     int mmc_ddr_tx_phase;
0891     int sd_default_tx_phase;
0892     int sd_default_rx_phase;
0893 
0894     int pmos_pwr_on_interval;
0895     int sd_voltage_switch_delay;
0896     int s3_pwr_off_delay;
0897 
0898     int force_clkreq_0;
0899     int ft2_fast_mode;
0900 
0901     int do_delink_before_power_down;
0902     int polling_config;
0903     int sdio_retry_cnt;
0904 
0905     int delink_stage1_step;
0906     int delink_stage2_step;
0907     int delink_stage3_step;
0908 
0909     int auto_delink_in_L1;
0910     int hp_watch_bios_hotplug;
0911     int support_ms_8bit;
0912 
0913     u8 blink_led;
0914     u8 phy_voltage;
0915     u8 max_payload;
0916 
0917     u32 sd_speed_prior;
0918     u32 sd_current_prior;
0919     u32 sd_ctl;
0920 };
0921 
0922 static inline struct device *rtsx_dev(const struct rtsx_chip *chip)
0923 {
0924     return &chip->rtsx->pci->dev;
0925 }
0926 
0927 #define rtsx_set_stat(chip, stat)               \
0928 do {                                \
0929     if ((stat) != RTSX_STAT_IDLE) {             \
0930         (chip)->idle_counter = 0;           \
0931     }                           \
0932     (chip)->rtsx_stat = (enum RTSX_STAT)(stat);     \
0933 } while (0)
0934 #define rtsx_get_stat(chip)     ((chip)->rtsx_stat)
0935 #define rtsx_chk_stat(chip, stat)   ((chip)->rtsx_stat == (stat))
0936 
0937 #define RTSX_SET_DELINK(chip)   ((chip)->rtsx_flag |= 0x01)
0938 #define RTSX_CLR_DELINK(chip)   ((chip)->rtsx_flag &= 0xFE)
0939 #define RTSX_TST_DELINK(chip)   ((chip)->rtsx_flag & 0x01)
0940 
0941 #define CHECK_PID(chip, pid)        ((chip)->product_id == (pid))
0942 #define CHECK_BARO_PKG(chip, pkg)   ((chip)->baro_pkg == (pkg))
0943 #define CHECK_LUN_MODE(chip, mode)  ((chip)->lun_mode == (mode))
0944 
0945 /* Power down control */
0946 #define SSC_PDCTL       0x01
0947 #define OC_PDCTL        0x02
0948 
0949 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl);
0950 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl);
0951 
0952 void rtsx_enable_card_int(struct rtsx_chip *chip);
0953 void rtsx_enable_bus_int(struct rtsx_chip *chip);
0954 void rtsx_disable_bus_int(struct rtsx_chip *chip);
0955 int rtsx_reset_chip(struct rtsx_chip *chip);
0956 int rtsx_init_chip(struct rtsx_chip *chip);
0957 void rtsx_release_chip(struct rtsx_chip *chip);
0958 void rtsx_polling_func(struct rtsx_chip *chip);
0959 void rtsx_stop_cmd(struct rtsx_chip *chip, int card);
0960 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data);
0961 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data);
0962 int rtsx_write_cfg_dw(struct rtsx_chip *chip,
0963               u8 func_no, u16 addr, u32 mask, u32 val);
0964 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val);
0965 int rtsx_write_cfg_seq(struct rtsx_chip *chip,
0966                u8 func, u16 addr, u8 *buf, int len);
0967 int rtsx_read_cfg_seq(struct rtsx_chip *chip,
0968               u8 func, u16 addr, u8 *buf, int len);
0969 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val);
0970 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val);
0971 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val);
0972 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val);
0973 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
0974 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
0975 void rtsx_enter_ss(struct rtsx_chip *chip);
0976 void rtsx_exit_ss(struct rtsx_chip *chip);
0977 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip);
0978 void rtsx_enter_L1(struct rtsx_chip *chip);
0979 void rtsx_exit_L1(struct rtsx_chip *chip);
0980 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat);
0981 void rtsx_enable_aspm(struct rtsx_chip *chip);
0982 void rtsx_disable_aspm(struct rtsx_chip *chip);
0983 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
0984 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
0985 int rtsx_check_chip_exist(struct rtsx_chip *chip);
0986 
0987 #endif  /* __REALTEK_RTSX_CHIP_H */
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