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0012 #ifndef __REALTEK_RTSX_CARD_H
0013 #define __REALTEK_RTSX_CARD_H
0014
0015 #include "rtsx.h"
0016 #include "rtsx_chip.h"
0017 #include "rtsx_transport.h"
0018 #include "sd.h"
0019
0020 #define SSC_POWER_DOWN 0x01
0021 #define SD_OC_POWER_DOWN 0x02
0022 #define MS_OC_POWER_DOWN 0x04
0023 #define ALL_POWER_DOWN 0x07
0024 #define OC_POWER_DOWN 0x06
0025
0026 #define PMOS_STRG_MASK 0x10
0027 #define PMOS_STRG_800mA 0x10
0028 #define PMOS_STRG_400mA 0x00
0029
0030 #define POWER_OFF 0x03
0031 #define PARTIAL_POWER_ON 0x01
0032 #define POWER_ON 0x00
0033
0034 #define MS_POWER_OFF 0x0C
0035 #define MS_PARTIAL_POWER_ON 0x04
0036 #define MS_POWER_ON 0x00
0037 #define MS_POWER_MASK 0x0C
0038
0039 #define SD_POWER_OFF 0x03
0040 #define SD_PARTIAL_POWER_ON 0x01
0041 #define SD_POWER_ON 0x00
0042 #define SD_POWER_MASK 0x03
0043
0044 #define XD_OUTPUT_EN 0x02
0045 #define SD_OUTPUT_EN 0x04
0046 #define MS_OUTPUT_EN 0x08
0047 #define SPI_OUTPUT_EN 0x10
0048
0049 #define CLK_LOW_FREQ 0x01
0050
0051 #define CLK_DIV_1 0x01
0052 #define CLK_DIV_2 0x02
0053 #define CLK_DIV_4 0x03
0054 #define CLK_DIV_8 0x04
0055
0056 #define SSC_80 0
0057 #define SSC_100 1
0058 #define SSC_120 2
0059 #define SSC_150 3
0060 #define SSC_200 4
0061
0062 #define XD_CLK_EN 0x02
0063 #define SD_CLK_EN 0x04
0064 #define MS_CLK_EN 0x08
0065 #define SPI_CLK_EN 0x10
0066
0067 #define XD_MOD_SEL 1
0068 #define SD_MOD_SEL 2
0069 #define MS_MOD_SEL 3
0070 #define SPI_MOD_SEL 4
0071
0072 #define CHANGE_CLK 0x01
0073
0074 #define SD_CRC7_ERR 0x80
0075 #define SD_CRC16_ERR 0x40
0076 #define SD_CRC_WRITE_ERR 0x20
0077 #define SD_CRC_WRITE_ERR_MASK 0x1C
0078 #define GET_CRC_TIME_OUT 0x02
0079 #define SD_TUNING_COMPARE_ERR 0x01
0080
0081 #define SD_RSP_80CLK_TIMEOUT 0x01
0082
0083 #define SD_CLK_TOGGLE_EN 0x80
0084 #define SD_CLK_FORCE_STOP 0x40
0085 #define SD_DAT3_STATUS 0x10
0086 #define SD_DAT2_STATUS 0x08
0087 #define SD_DAT1_STATUS 0x04
0088 #define SD_DAT0_STATUS 0x02
0089 #define SD_CMD_STATUS 0x01
0090
0091 #define SD_IO_USING_1V8 0x80
0092 #define SD_IO_USING_3V3 0x7F
0093 #define TYPE_A_DRIVING 0x00
0094 #define TYPE_B_DRIVING 0x01
0095 #define TYPE_C_DRIVING 0x02
0096 #define TYPE_D_DRIVING 0x03
0097
0098 #define DDR_FIX_RX_DAT 0x00
0099 #define DDR_VAR_RX_DAT 0x80
0100 #define DDR_FIX_RX_DAT_EDGE 0x00
0101 #define DDR_FIX_RX_DAT_14_DELAY 0x40
0102 #define DDR_FIX_RX_CMD 0x00
0103 #define DDR_VAR_RX_CMD 0x20
0104 #define DDR_FIX_RX_CMD_POS_EDGE 0x00
0105 #define DDR_FIX_RX_CMD_14_DELAY 0x10
0106 #define SD20_RX_POS_EDGE 0x00
0107 #define SD20_RX_14_DELAY 0x08
0108 #define SD20_RX_SEL_MASK 0x08
0109
0110 #define DDR_FIX_TX_CMD_DAT 0x00
0111 #define DDR_VAR_TX_CMD_DAT 0x80
0112 #define DDR_FIX_TX_DAT_14_TSU 0x00
0113 #define DDR_FIX_TX_DAT_12_TSU 0x40
0114 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
0115 #define DDR_FIX_TX_CMD_14_AHEAD 0x20
0116 #define SD20_TX_NEG_EDGE 0x00
0117 #define SD20_TX_14_AHEAD 0x10
0118 #define SD20_TX_SEL_MASK 0x10
0119 #define DDR_VAR_SDCLK_POL_SWAP 0x01
0120
0121 #define SD_TRANSFER_START 0x80
0122 #define SD_TRANSFER_END 0x40
0123 #define SD_STAT_IDLE 0x20
0124 #define SD_TRANSFER_ERR 0x10
0125 #define SD_TM_NORMAL_WRITE 0x00
0126 #define SD_TM_AUTO_WRITE_3 0x01
0127 #define SD_TM_AUTO_WRITE_4 0x02
0128 #define SD_TM_AUTO_READ_3 0x05
0129 #define SD_TM_AUTO_READ_4 0x06
0130 #define SD_TM_CMD_RSP 0x08
0131 #define SD_TM_AUTO_WRITE_1 0x09
0132 #define SD_TM_AUTO_WRITE_2 0x0A
0133 #define SD_TM_NORMAL_READ 0x0C
0134 #define SD_TM_AUTO_READ_1 0x0D
0135 #define SD_TM_AUTO_READ_2 0x0E
0136 #define SD_TM_AUTO_TUNING 0x0F
0137
0138 #define PHASE_CHANGE 0x80
0139 #define PHASE_NOT_RESET 0x40
0140
0141 #define DCMPS_CHANGE 0x80
0142 #define DCMPS_CHANGE_DONE 0x40
0143 #define DCMPS_ERROR 0x20
0144 #define DCMPS_CURRENT_PHASE 0x1F
0145
0146 #define SD_CLK_DIVIDE_0 0x00
0147 #define SD_CLK_DIVIDE_256 0xC0
0148 #define SD_CLK_DIVIDE_128 0x80
0149 #define SD_BUS_WIDTH_1 0x00
0150 #define SD_BUS_WIDTH_4 0x01
0151 #define SD_BUS_WIDTH_8 0x02
0152 #define SD_ASYNC_FIFO_NOT_RST 0x10
0153 #define SD_20_MODE 0x00
0154 #define SD_DDR_MODE 0x04
0155 #define SD_30_MODE 0x08
0156
0157 #define SD_CLK_DIVIDE_MASK 0xC0
0158
0159 #define SD_CMD_IDLE 0x80
0160
0161 #define SD_DATA_IDLE 0x80
0162
0163 #define DCM_RESET 0x08
0164 #define DCM_LOCKED 0x04
0165 #define DCM_208M 0x00
0166 #define DCM_TX 0x01
0167 #define DCM_RX 0x02
0168
0169 #define DRP_START 0x80
0170 #define DRP_DONE 0x40
0171
0172 #define DRP_WRITE 0x80
0173 #define DRP_READ 0x00
0174 #define DCM_WRITE_ADDRESS_50 0x50
0175 #define DCM_WRITE_ADDRESS_51 0x51
0176 #define DCM_READ_ADDRESS_00 0x00
0177 #define DCM_READ_ADDRESS_51 0x51
0178
0179 #define SD_CALCULATE_CRC7 0x00
0180 #define SD_NO_CALCULATE_CRC7 0x80
0181 #define SD_CHECK_CRC16 0x00
0182 #define SD_NO_CHECK_CRC16 0x40
0183 #define SD_NO_CHECK_WAIT_CRC_TO 0x20
0184 #define SD_WAIT_BUSY_END 0x08
0185 #define SD_NO_WAIT_BUSY_END 0x00
0186 #define SD_CHECK_CRC7 0x00
0187 #define SD_NO_CHECK_CRC7 0x04
0188 #define SD_RSP_LEN_0 0x00
0189 #define SD_RSP_LEN_6 0x01
0190 #define SD_RSP_LEN_17 0x02
0191 #define SD_RSP_TYPE_R0 0x04
0192 #define SD_RSP_TYPE_R1 0x01
0193 #define SD_RSP_TYPE_R1b 0x09
0194 #define SD_RSP_TYPE_R2 0x02
0195 #define SD_RSP_TYPE_R3 0x05
0196 #define SD_RSP_TYPE_R4 0x05
0197 #define SD_RSP_TYPE_R5 0x01
0198 #define SD_RSP_TYPE_R6 0x01
0199 #define SD_RSP_TYPE_R7 0x01
0200
0201 #define SD_RSP_80CLK_TIMEOUT_EN 0x01
0202
0203 #define SAMPLE_TIME_RISING 0x00
0204 #define SAMPLE_TIME_FALLING 0x80
0205 #define PUSH_TIME_DEFAULT 0x00
0206 #define PUSH_TIME_ODD 0x40
0207 #define NO_EXTEND_TOGGLE 0x00
0208 #define EXTEND_TOGGLE_CHK 0x20
0209 #define MS_BUS_WIDTH_1 0x00
0210 #define MS_BUS_WIDTH_4 0x10
0211 #define MS_BUS_WIDTH_8 0x18
0212 #define MS_2K_SECTOR_MODE 0x04
0213 #define MS_512_SECTOR_MODE 0x00
0214 #define MS_TOGGLE_TIMEOUT_EN 0x00
0215 #define MS_TOGGLE_TIMEOUT_DISEN 0x01
0216 #define MS_NO_CHECK_INT 0x02
0217
0218 #define WAIT_INT 0x80
0219 #define NO_WAIT_INT 0x00
0220 #define NO_AUTO_READ_INT_REG 0x00
0221 #define AUTO_READ_INT_REG 0x40
0222 #define MS_CRC16_ERR 0x20
0223 #define MS_RDY_TIMEOUT 0x10
0224 #define MS_INT_CMDNK 0x08
0225 #define MS_INT_BREQ 0x04
0226 #define MS_INT_ERR 0x02
0227 #define MS_INT_CED 0x01
0228
0229 #define MS_TRANSFER_START 0x80
0230 #define MS_TRANSFER_END 0x40
0231 #define MS_TRANSFER_ERR 0x20
0232 #define MS_BS_STATE 0x10
0233 #define MS_TM_READ_BYTES 0x00
0234 #define MS_TM_NORMAL_READ 0x01
0235 #define MS_TM_WRITE_BYTES 0x04
0236 #define MS_TM_NORMAL_WRITE 0x05
0237 #define MS_TM_AUTO_READ 0x08
0238 #define MS_TM_AUTO_WRITE 0x0C
0239
0240 #define CARD_SHARE_MASK 0x0F
0241 #define CARD_SHARE_MULTI_LUN 0x00
0242 #define CARD_SHARE_NORMAL 0x00
0243 #define CARD_SHARE_48_XD 0x02
0244 #define CARD_SHARE_48_SD 0x04
0245 #define CARD_SHARE_48_MS 0x08
0246 #define CARD_SHARE_BAROSSA_XD 0x00
0247 #define CARD_SHARE_BAROSSA_SD 0x01
0248 #define CARD_SHARE_BAROSSA_MS 0x02
0249
0250 #define MS_DRIVE_8 0x00
0251 #define MS_DRIVE_4 0x40
0252 #define MS_DRIVE_12 0x80
0253 #define SD_DRIVE_8 0x00
0254 #define SD_DRIVE_4 0x10
0255 #define SD_DRIVE_12 0x20
0256 #define XD_DRIVE_8 0x00
0257 #define XD_DRIVE_4 0x04
0258 #define XD_DRIVE_12 0x08
0259
0260 #define SPI_STOP 0x01
0261 #define XD_STOP 0x02
0262 #define SD_STOP 0x04
0263 #define MS_STOP 0x08
0264 #define SPI_CLR_ERR 0x10
0265 #define XD_CLR_ERR 0x20
0266 #define SD_CLR_ERR 0x40
0267 #define MS_CLR_ERR 0x80
0268
0269 #define CRC_FIX_CLK (0x00 << 0)
0270 #define CRC_VAR_CLK0 (0x01 << 0)
0271 #define CRC_VAR_CLK1 (0x02 << 0)
0272 #define SD30_FIX_CLK (0x00 << 2)
0273 #define SD30_VAR_CLK0 (0x01 << 2)
0274 #define SD30_VAR_CLK1 (0x02 << 2)
0275 #define SAMPLE_FIX_CLK (0x00 << 4)
0276 #define SAMPLE_VAR_CLK0 (0x01 << 4)
0277 #define SAMPLE_VAR_CLK1 (0x02 << 4)
0278
0279 #define SDIO_VER_20 0x80
0280 #define SDIO_VER_10 0x00
0281 #define SDIO_VER_CHG 0x40
0282 #define SDIO_BUS_AUTO_SWITCH 0x10
0283
0284 #define PINGPONG_BUFFER 0x01
0285 #define RING_BUFFER 0x00
0286
0287 #define RB_FLUSH 0x80
0288
0289 #define DMA_DONE_INT_EN 0x80
0290 #define SUSPEND_INT_EN 0x40
0291 #define LINK_RDY_INT_EN 0x20
0292 #define LINK_DOWN_INT_EN 0x10
0293
0294 #define DMA_DONE_INT 0x80
0295 #define SUSPEND_INT 0x40
0296 #define LINK_RDY_INT 0x20
0297 #define LINK_DOWN_INT 0x10
0298
0299 #define MRD_ERR_INT_EN 0x40
0300 #define MWR_ERR_INT_EN 0x20
0301 #define SCSI_CMD_INT_EN 0x10
0302 #define TLP_RCV_INT_EN 0x08
0303 #define TLP_TRSMT_INT_EN 0x04
0304 #define MRD_COMPLETE_INT_EN 0x02
0305 #define MWR_COMPLETE_INT_EN 0x01
0306
0307 #define MRD_ERR_INT 0x40
0308 #define MWR_ERR_INT 0x20
0309 #define SCSI_CMD_INT 0x10
0310 #define TLP_RX_INT 0x08
0311 #define TLP_TX_INT 0x04
0312 #define MRD_COMPLETE_INT 0x02
0313 #define MWR_COMPLETE_INT 0x01
0314
0315 #define MSG_RX_INT_EN 0x08
0316 #define MRD_RX_INT_EN 0x04
0317 #define MWR_RX_INT_EN 0x02
0318 #define CPLD_RX_INT_EN 0x01
0319
0320 #define MSG_RX_INT 0x08
0321 #define MRD_RX_INT 0x04
0322 #define MWR_RX_INT 0x02
0323 #define CPLD_RX_INT 0x01
0324
0325 #define MSG_TX_INT_EN 0x08
0326 #define MRD_TX_INT_EN 0x04
0327 #define MWR_TX_INT_EN 0x02
0328 #define CPLD_TX_INT_EN 0x01
0329
0330 #define MSG_TX_INT 0x08
0331 #define MRD_TX_INT 0x04
0332 #define MWR_TX_INT 0x02
0333 #define CPLD_TX_INT 0x01
0334
0335 #define DMA_RST 0x80
0336 #define DMA_BUSY 0x04
0337 #define DMA_DIR_TO_CARD 0x00
0338 #define DMA_DIR_FROM_CARD 0x02
0339 #define DMA_EN 0x01
0340 #define DMA_128 (0 << 4)
0341 #define DMA_256 (1 << 4)
0342 #define DMA_512 (2 << 4)
0343 #define DMA_1024 (3 << 4)
0344 #define DMA_PACK_SIZE_MASK 0x30
0345
0346 #define XD_PWR_OFF_DELAY0 0x00
0347 #define XD_PWR_OFF_DELAY1 0x02
0348 #define XD_PWR_OFF_DELAY2 0x04
0349 #define XD_PWR_OFF_DELAY3 0x06
0350 #define XD_AUTO_PWR_OFF_EN 0xF7
0351 #define XD_NO_AUTO_PWR_OFF 0x08
0352
0353 #define XD_TIME_RWN_1 0x00
0354 #define XD_TIME_RWN_STEP 0x20
0355 #define XD_TIME_RW_1 0x00
0356 #define XD_TIME_RW_STEP 0x04
0357 #define XD_TIME_SETUP_1 0x00
0358 #define XD_TIME_SETUP_STEP 0x01
0359
0360 #define XD_ECC2_UNCORRECTABLE 0x80
0361 #define XD_ECC2_ERROR 0x40
0362 #define XD_ECC1_UNCORRECTABLE 0x20
0363 #define XD_ECC1_ERROR 0x10
0364 #define XD_RDY 0x04
0365 #define XD_CE_EN 0xFD
0366 #define XD_CE_DISEN 0x02
0367 #define XD_WP_EN 0xFE
0368 #define XD_WP_DISEN 0x01
0369
0370 #define XD_TRANSFER_START 0x80
0371 #define XD_TRANSFER_END 0x40
0372 #define XD_PPB_EMPTY 0x20
0373 #define XD_RESET 0x00
0374 #define XD_ERASE 0x01
0375 #define XD_READ_STATUS 0x02
0376 #define XD_READ_ID 0x03
0377 #define XD_READ_REDUNDANT 0x04
0378 #define XD_READ_PAGES 0x05
0379 #define XD_SET_CMD 0x06
0380 #define XD_NORMAL_READ 0x07
0381 #define XD_WRITE_PAGES 0x08
0382 #define XD_NORMAL_WRITE 0x09
0383 #define XD_WRITE_REDUNDANT 0x0A
0384 #define XD_SET_ADDR 0x0B
0385
0386 #define XD_PPB_TO_SIE 0x80
0387 #define XD_TO_PPB_ONLY 0x00
0388 #define XD_BA_TRANSFORM 0x40
0389 #define XD_BA_NO_TRANSFORM 0x00
0390 #define XD_NO_CALC_ECC 0x20
0391 #define XD_CALC_ECC 0x00
0392 #define XD_IGNORE_ECC 0x10
0393 #define XD_CHECK_ECC 0x00
0394 #define XD_DIRECT_TO_RB 0x08
0395 #define XD_ADDR_LENGTH_0 0x00
0396 #define XD_ADDR_LENGTH_1 0x01
0397 #define XD_ADDR_LENGTH_2 0x02
0398 #define XD_ADDR_LENGTH_3 0x03
0399 #define XD_ADDR_LENGTH_4 0x04
0400
0401 #define XD_GPG 0xFF
0402 #define XD_BPG 0x00
0403
0404 #define XD_GBLK 0xFF
0405 #define XD_LATER_BBLK 0xF0
0406
0407 #define XD_ECC2_ALL1 0x80
0408 #define XD_ECC1_ALL1 0x40
0409 #define XD_BA2_ALL0 0x20
0410 #define XD_BA1_ALL0 0x10
0411 #define XD_BA1_BA2_EQL 0x04
0412 #define XD_BA2_VALID 0x02
0413 #define XD_BA1_VALID 0x01
0414
0415 #define XD_PGSTS_ZEROBIT_OVER4 0x00
0416 #define XD_PGSTS_NOT_FF 0x02
0417 #define XD_AUTO_CHK_DATA_STATUS 0x01
0418
0419 #define RSTB_MODE_DETECT 0x80
0420 #define MODE_OUT_VLD 0x40
0421 #define MODE_OUT_0_NONE 0x00
0422 #define MODE_OUT_10_NONE 0x04
0423 #define MODE_OUT_10_47 0x05
0424 #define MODE_OUT_10_180 0x06
0425 #define MODE_OUT_10_680 0x07
0426 #define MODE_OUT_16_NONE 0x08
0427 #define MODE_OUT_16_47 0x09
0428 #define MODE_OUT_16_180 0x0A
0429 #define MODE_OUT_16_680 0x0B
0430 #define MODE_OUT_NONE_NONE 0x0C
0431 #define MODE_OUT_NONE_47 0x0D
0432 #define MODE_OUT_NONE_180 0x0E
0433 #define MODE_OUT_NONE_680 0x0F
0434
0435 #define CARD_OC_INT_EN 0x20
0436 #define CARD_DETECT_EN 0x08
0437
0438 #define MS_DETECT_EN 0x80
0439 #define MS_OCP_INT_EN 0x40
0440 #define MS_OCP_INT_CLR 0x20
0441 #define MS_OC_CLR 0x10
0442 #define SD_DETECT_EN 0x08
0443 #define SD_OCP_INT_EN 0x04
0444 #define SD_OCP_INT_CLR 0x02
0445 #define SD_OC_CLR 0x01
0446
0447 #define CARD_OCP_DETECT 0x80
0448 #define CARD_OC_NOW 0x08
0449 #define CARD_OC_EVER 0x04
0450
0451 #define MS_OCP_DETECT 0x80
0452 #define MS_OC_NOW 0x40
0453 #define MS_OC_EVER 0x20
0454 #define SD_OCP_DETECT 0x08
0455 #define SD_OC_NOW 0x04
0456 #define SD_OC_EVER 0x02
0457
0458 #define CARD_OC_INT_CLR 0x08
0459 #define CARD_OC_CLR 0x02
0460
0461 #define SD_OCP_GLITCH_MASK 0x07
0462 #define SD_OCP_GLITCH_6_4 0x00
0463 #define SD_OCP_GLITCH_64 0x01
0464 #define SD_OCP_GLITCH_640 0x02
0465 #define SD_OCP_GLITCH_1000 0x03
0466 #define SD_OCP_GLITCH_2000 0x04
0467 #define SD_OCP_GLITCH_4000 0x05
0468 #define SD_OCP_GLITCH_8000 0x06
0469 #define SD_OCP_GLITCH_10000 0x07
0470
0471 #define MS_OCP_GLITCH_MASK 0x70
0472 #define MS_OCP_GLITCH_6_4 (0x00 << 4)
0473 #define MS_OCP_GLITCH_64 (0x01 << 4)
0474 #define MS_OCP_GLITCH_640 (0x02 << 4)
0475 #define MS_OCP_GLITCH_1000 (0x03 << 4)
0476 #define MS_OCP_GLITCH_2000 (0x04 << 4)
0477 #define MS_OCP_GLITCH_4000 (0x05 << 4)
0478 #define MS_OCP_GLITCH_8000 (0x06 << 4)
0479 #define MS_OCP_GLITCH_10000 (0x07 << 4)
0480
0481 #define OCP_TIME_60 0x00
0482 #define OCP_TIME_100 (0x01 << 3)
0483 #define OCP_TIME_200 (0x02 << 3)
0484 #define OCP_TIME_400 (0x03 << 3)
0485 #define OCP_TIME_600 (0x04 << 3)
0486 #define OCP_TIME_800 (0x05 << 3)
0487 #define OCP_TIME_1100 (0x06 << 3)
0488 #define OCP_TIME_MASK 0x38
0489
0490 #define MS_OCP_TIME_60 0x00
0491 #define MS_OCP_TIME_100 (0x01 << 4)
0492 #define MS_OCP_TIME_200 (0x02 << 4)
0493 #define MS_OCP_TIME_400 (0x03 << 4)
0494 #define MS_OCP_TIME_600 (0x04 << 4)
0495 #define MS_OCP_TIME_800 (0x05 << 4)
0496 #define MS_OCP_TIME_1100 (0x06 << 4)
0497 #define MS_OCP_TIME_MASK 0x70
0498
0499 #define SD_OCP_TIME_60 0x00
0500 #define SD_OCP_TIME_100 0x01
0501 #define SD_OCP_TIME_200 0x02
0502 #define SD_OCP_TIME_400 0x03
0503 #define SD_OCP_TIME_600 0x04
0504 #define SD_OCP_TIME_800 0x05
0505 #define SD_OCP_TIME_1100 0x06
0506 #define SD_OCP_TIME_MASK 0x07
0507
0508 #define OCP_THD_315_417 0x00
0509 #define OCP_THD_283_783 (0x01 << 6)
0510 #define OCP_THD_244_946 (0x02 << 6)
0511 #define OCP_THD_191_1080 (0x03 << 6)
0512 #define OCP_THD_MASK 0xC0
0513
0514 #define MS_OCP_THD_450 0x00
0515 #define MS_OCP_THD_550 (0x01 << 4)
0516 #define MS_OCP_THD_650 (0x02 << 4)
0517 #define MS_OCP_THD_750 (0x03 << 4)
0518 #define MS_OCP_THD_850 (0x04 << 4)
0519 #define MS_OCP_THD_950 (0x05 << 4)
0520 #define MS_OCP_THD_1050 (0x06 << 4)
0521 #define MS_OCP_THD_1150 (0x07 << 4)
0522 #define MS_OCP_THD_MASK 0x70
0523
0524 #define SD_OCP_THD_450 0x00
0525 #define SD_OCP_THD_550 0x01
0526 #define SD_OCP_THD_650 0x02
0527 #define SD_OCP_THD_750 0x03
0528 #define SD_OCP_THD_850 0x04
0529 #define SD_OCP_THD_950 0x05
0530 #define SD_OCP_THD_1050 0x06
0531 #define SD_OCP_THD_1150 0x07
0532 #define SD_OCP_THD_MASK 0x07
0533
0534 #define FPGA_MS_PULL_CTL_EN 0xEF
0535 #define FPGA_SD_PULL_CTL_EN 0xF7
0536 #define FPGA_XD_PULL_CTL_EN1 0xFE
0537 #define FPGA_XD_PULL_CTL_EN2 0xFD
0538 #define FPGA_XD_PULL_CTL_EN3 0xFB
0539
0540 #define FPGA_MS_PULL_CTL_BIT 0x10
0541 #define FPGA_SD_PULL_CTL_BIT 0x08
0542
0543 #define BLINK_EN 0x08
0544 #define LED_GPIO0 (0 << 4)
0545 #define LED_GPIO1 (1 << 4)
0546 #define LED_GPIO2 (2 << 4)
0547
0548 #define SDIO_BUS_CTRL 0x01
0549 #define SDIO_CD_CTRL 0x02
0550
0551 #define SSC_RSTB 0x80
0552 #define SSC_8X_EN 0x40
0553 #define SSC_FIX_FRAC 0x20
0554 #define SSC_SEL_1M 0x00
0555 #define SSC_SEL_2M 0x08
0556 #define SSC_SEL_4M 0x10
0557 #define SSC_SEL_8M 0x18
0558
0559 #define SSC_DEPTH_MASK 0x07
0560 #define SSC_DEPTH_DISALBE 0x00
0561 #define SSC_DEPTH_4M 0x01
0562 #define SSC_DEPTH_2M 0x02
0563 #define SSC_DEPTH_1M 0x03
0564 #define SSC_DEPTH_512K 0x04
0565 #define SSC_DEPTH_256K 0x05
0566 #define SSC_DEPTH_128K 0x06
0567 #define SSC_DEPTH_64K 0x07
0568
0569 #define XD_D3_NP 0x00
0570 #define XD_D3_PD (0x01 << 6)
0571 #define XD_D3_PU (0x02 << 6)
0572 #define XD_D2_NP 0x00
0573 #define XD_D2_PD (0x01 << 4)
0574 #define XD_D2_PU (0x02 << 4)
0575 #define XD_D1_NP 0x00
0576 #define XD_D1_PD (0x01 << 2)
0577 #define XD_D1_PU (0x02 << 2)
0578 #define XD_D0_NP 0x00
0579 #define XD_D0_PD 0x01
0580 #define XD_D0_PU 0x02
0581
0582 #define SD_D7_NP 0x00
0583 #define SD_D7_PD (0x01 << 4)
0584 #define SD_DAT7_PU (0x02 << 4)
0585 #define SD_CLK_NP 0x00
0586 #define SD_CLK_PD (0x01 << 2)
0587 #define SD_CLK_PU (0x02 << 2)
0588 #define SD_D5_NP 0x00
0589 #define SD_D5_PD 0x01
0590 #define SD_D5_PU 0x02
0591
0592 #define MS_D1_NP 0x00
0593 #define MS_D1_PD (0x01 << 6)
0594 #define MS_D1_PU (0x02 << 6)
0595 #define MS_D2_NP 0x00
0596 #define MS_D2_PD (0x01 << 4)
0597 #define MS_D2_PU (0x02 << 4)
0598 #define MS_CLK_NP 0x00
0599 #define MS_CLK_PD (0x01 << 2)
0600 #define MS_CLK_PU (0x02 << 2)
0601 #define MS_D6_NP 0x00
0602 #define MS_D6_PD 0x01
0603 #define MS_D6_PU 0x02
0604
0605 #define XD_D7_NP 0x00
0606 #define XD_D7_PD (0x01 << 6)
0607 #define XD_D7_PU (0x02 << 6)
0608 #define XD_D6_NP 0x00
0609 #define XD_D6_PD (0x01 << 4)
0610 #define XD_D6_PU (0x02 << 4)
0611 #define XD_D5_NP 0x00
0612 #define XD_D5_PD (0x01 << 2)
0613 #define XD_D5_PU (0x02 << 2)
0614 #define XD_D4_NP 0x00
0615 #define XD_D4_PD 0x01
0616 #define XD_D4_PU 0x02
0617
0618 #define SD_D6_NP 0x00
0619 #define SD_D6_PD (0x01 << 6)
0620 #define SD_D6_PU (0x02 << 6)
0621 #define SD_D0_NP 0x00
0622 #define SD_D0_PD (0x01 << 4)
0623 #define SD_D0_PU (0x02 << 4)
0624 #define SD_D1_NP 0x00
0625 #define SD_D1_PD 0x01
0626 #define SD_D1_PU 0x02
0627
0628 #define MS_D3_NP 0x00
0629 #define MS_D3_PD (0x01 << 6)
0630 #define MS_D3_PU (0x02 << 6)
0631 #define MS_D0_NP 0x00
0632 #define MS_D0_PD (0x01 << 4)
0633 #define MS_D0_PU (0x02 << 4)
0634 #define MS_BS_NP 0x00
0635 #define MS_BS_PD (0x01 << 2)
0636 #define MS_BS_PU (0x02 << 2)
0637
0638 #define XD_WP_NP 0x00
0639 #define XD_WP_PD (0x01 << 6)
0640 #define XD_WP_PU (0x02 << 6)
0641 #define XD_CE_NP 0x00
0642 #define XD_CE_PD (0x01 << 3)
0643 #define XD_CE_PU (0x02 << 3)
0644 #define XD_CLE_NP 0x00
0645 #define XD_CLE_PD (0x01 << 1)
0646 #define XD_CLE_PU (0x02 << 1)
0647 #define XD_CD_PD 0x00
0648 #define XD_CD_PU 0x01
0649
0650 #define SD_D4_NP 0x00
0651 #define SD_D4_PD (0x01 << 6)
0652 #define SD_D4_PU (0x02 << 6)
0653
0654 #define MS_D7_NP 0x00
0655 #define MS_D7_PD (0x01 << 6)
0656 #define MS_D7_PU (0x02 << 6)
0657
0658 #define XD_RDY_NP 0x00
0659 #define XD_RDY_PD (0x01 << 6)
0660 #define XD_RDY_PU (0x02 << 6)
0661 #define XD_WE_NP 0x00
0662 #define XD_WE_PD (0x01 << 4)
0663 #define XD_WE_PU (0x02 << 4)
0664 #define XD_RE_NP 0x00
0665 #define XD_RE_PD (0x01 << 2)
0666 #define XD_RE_PU (0x02 << 2)
0667 #define XD_ALE_NP 0x00
0668 #define XD_ALE_PD 0x01
0669 #define XD_ALE_PU 0x02
0670
0671 #define SD_D3_NP 0x00
0672 #define SD_D3_PD (0x01 << 4)
0673 #define SD_D3_PU (0x02 << 4)
0674 #define SD_D2_NP 0x00
0675 #define SD_D2_PD (0x01 << 2)
0676 #define SD_D2_PU (0x02 << 2)
0677
0678 #define MS_INS_PD 0x00
0679 #define MS_INS_PU (0x01 << 7)
0680 #define SD_WP_NP 0x00
0681 #define SD_WP_PD (0x01 << 5)
0682 #define SD_WP_PU (0x02 << 5)
0683 #define SD_CD_PD 0x00
0684 #define SD_CD_PU (0x01 << 4)
0685 #define SD_CMD_NP 0x00
0686 #define SD_CMD_PD (0x01 << 2)
0687 #define SD_CMD_PU (0x02 << 2)
0688
0689 #define MS_D5_NP 0x00
0690 #define MS_D5_PD (0x01 << 2)
0691 #define MS_D5_PU (0x02 << 2)
0692 #define MS_D4_NP 0x00
0693 #define MS_D4_PD 0x01
0694 #define MS_D4_PU 0x02
0695
0696 #define FORCE_PM_CLOCK 0x10
0697 #define EN_CLOCK_PM 0x01
0698
0699 #define HOST_ENTER_S3 0x02
0700 #define HOST_ENTER_S1 0x01
0701
0702 #define AUX_PWR_DETECTED 0x01
0703
0704 #define PHY_DEBUG_MODE 0x01
0705
0706 #define SPI_COMMAND_BIT_8 0xE0
0707 #define SPI_ADDRESS_BIT_24 0x17
0708 #define SPI_ADDRESS_BIT_32 0x1F
0709
0710 #define SPI_TRANSFER0_START 0x80
0711 #define SPI_TRANSFER0_END 0x40
0712 #define SPI_C_MODE0 0x00
0713 #define SPI_CA_MODE0 0x01
0714 #define SPI_CDO_MODE0 0x02
0715 #define SPI_CDI_MODE0 0x03
0716 #define SPI_CADO_MODE0 0x04
0717 #define SPI_CADI_MODE0 0x05
0718 #define SPI_POLLING_MODE0 0x06
0719
0720 #define SPI_TRANSFER1_START 0x80
0721 #define SPI_TRANSFER1_END 0x40
0722 #define SPI_DO_MODE1 0x00
0723 #define SPI_DI_MODE1 0x01
0724
0725 #define CS_POLARITY_HIGH 0x40
0726 #define CS_POLARITY_LOW 0x00
0727 #define DTO_MSB_FIRST 0x00
0728 #define DTO_LSB_FIRST 0x20
0729 #define SPI_MASTER 0x00
0730 #define SPI_SLAVE 0x10
0731 #define SPI_MODE0 0x00
0732 #define SPI_MODE1 0x04
0733 #define SPI_MODE2 0x08
0734 #define SPI_MODE3 0x0C
0735 #define SPI_MANUAL 0x00
0736 #define SPI_HALF_AUTO 0x01
0737 #define SPI_AUTO 0x02
0738 #define SPI_EEPROM_AUTO 0x03
0739
0740 #define EDO_TIMING_MASK 0x03
0741 #define SAMPLE_RISING 0x00
0742 #define SAMPLE_DELAY_HALF 0x01
0743 #define SAMPLE_DELAY_ONE 0x02
0744 #define SAPMLE_DELAY_ONE_HALF 0x03
0745 #define TCS_MASK 0x0C
0746
0747 #define NOT_BYPASS_SD 0x02
0748 #define DISABLE_SDIO_FUNC 0x04
0749 #define SELECT_1LUN 0x08
0750
0751 #define PWR_GATE_EN 0x01
0752 #define LDO3318_PWR_MASK 0x06
0753 #define LDO_ON 0x00
0754 #define LDO_SUSPEND 0x04
0755 #define LDO_OFF 0x06
0756
0757 #define SD_CFG1 0xFDA0
0758 #define SD_CFG2 0xFDA1
0759 #define SD_CFG3 0xFDA2
0760 #define SD_STAT1 0xFDA3
0761 #define SD_STAT2 0xFDA4
0762 #define SD_BUS_STAT 0xFDA5
0763 #define SD_PAD_CTL 0xFDA6
0764 #define SD_SAMPLE_POINT_CTL 0xFDA7
0765 #define SD_PUSH_POINT_CTL 0xFDA8
0766 #define SD_CMD0 0xFDA9
0767 #define SD_CMD1 0xFDAA
0768 #define SD_CMD2 0xFDAB
0769 #define SD_CMD3 0xFDAC
0770 #define SD_CMD4 0xFDAD
0771 #define SD_CMD5 0xFDAE
0772 #define SD_BYTE_CNT_L 0xFDAF
0773 #define SD_BYTE_CNT_H 0xFDB0
0774 #define SD_BLOCK_CNT_L 0xFDB1
0775 #define SD_BLOCK_CNT_H 0xFDB2
0776 #define SD_TRANSFER 0xFDB3
0777 #define SD_CMD_STATE 0xFDB5
0778 #define SD_DATA_STATE 0xFDB6
0779
0780 #define DCM_DRP_CTL 0xFC23
0781 #define DCM_DRP_TRIG 0xFC24
0782 #define DCM_DRP_CFG 0xFC25
0783 #define DCM_DRP_WR_DATA_L 0xFC26
0784 #define DCM_DRP_WR_DATA_H 0xFC27
0785 #define DCM_DRP_RD_DATA_L 0xFC28
0786 #define DCM_DRP_RD_DATA_H 0xFC29
0787 #define SD_VPCLK0_CTL 0xFC2A
0788 #define SD_VPCLK1_CTL 0xFC2B
0789 #define SD_DCMPS0_CTL 0xFC2C
0790 #define SD_DCMPS1_CTL 0xFC2D
0791 #define SD_VPTX_CTL SD_VPCLK0_CTL
0792 #define SD_VPRX_CTL SD_VPCLK1_CTL
0793 #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
0794 #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
0795
0796 #define CARD_CLK_SOURCE 0xFC2E
0797
0798 #define CARD_PWR_CTL 0xFD50
0799 #define CARD_CLK_SWITCH 0xFD51
0800 #define CARD_SHARE_MODE 0xFD52
0801 #define CARD_DRIVE_SEL 0xFD53
0802 #define CARD_STOP 0xFD54
0803 #define CARD_OE 0xFD55
0804 #define CARD_AUTO_BLINK 0xFD56
0805 #define CARD_GPIO_DIR 0xFD57
0806 #define CARD_GPIO 0xFD58
0807
0808 #define CARD_DATA_SOURCE 0xFD5B
0809 #define CARD_SELECT 0xFD5C
0810 #define SD30_DRIVE_SEL 0xFD5E
0811
0812 #define CARD_CLK_EN 0xFD69
0813
0814 #define SDIO_CTRL 0xFD6B
0815
0816 #define FPDCTL 0xFC00
0817 #define PDINFO 0xFC01
0818
0819 #define CLK_CTL 0xFC02
0820 #define CLK_DIV 0xFC03
0821 #define CLK_SEL 0xFC04
0822
0823 #define SSC_DIV_N_0 0xFC0F
0824 #define SSC_DIV_N_1 0xFC10
0825
0826 #define RCCTL 0xFC14
0827
0828 #define FPGA_PULL_CTL 0xFC1D
0829
0830 #define CARD_PULL_CTL1 0xFD60
0831 #define CARD_PULL_CTL2 0xFD61
0832 #define CARD_PULL_CTL3 0xFD62
0833 #define CARD_PULL_CTL4 0xFD63
0834 #define CARD_PULL_CTL5 0xFD64
0835 #define CARD_PULL_CTL6 0xFD65
0836
0837 #define IRQEN0 0xFE20
0838 #define IRQSTAT0 0xFE21
0839 #define IRQEN1 0xFE22
0840 #define IRQSTAT1 0xFE23
0841 #define TLPRIEN 0xFE24
0842 #define TLPRISTAT 0xFE25
0843 #define TLPTIEN 0xFE26
0844 #define TLPTISTAT 0xFE27
0845 #define DMATC0 0xFE28
0846 #define DMATC1 0xFE29
0847 #define DMATC2 0xFE2A
0848 #define DMATC3 0xFE2B
0849 #define DMACTL 0xFE2C
0850 #define BCTL 0xFE2D
0851 #define RBBC0 0xFE2E
0852 #define RBBC1 0xFE2F
0853 #define RBDAT 0xFE30
0854 #define RBCTL 0xFE34
0855 #define CFGADDR0 0xFE35
0856 #define CFGADDR1 0xFE36
0857 #define CFGDATA0 0xFE37
0858 #define CFGDATA1 0xFE38
0859 #define CFGDATA2 0xFE39
0860 #define CFGDATA3 0xFE3A
0861 #define CFGRWCTL 0xFE3B
0862 #define PHYRWCTL 0xFE3C
0863 #define PHYDATA0 0xFE3D
0864 #define PHYDATA1 0xFE3E
0865 #define PHYADDR 0xFE3F
0866 #define MSGRXDATA0 0xFE40
0867 #define MSGRXDATA1 0xFE41
0868 #define MSGRXDATA2 0xFE42
0869 #define MSGRXDATA3 0xFE43
0870 #define MSGTXDATA0 0xFE44
0871 #define MSGTXDATA1 0xFE45
0872 #define MSGTXDATA2 0xFE46
0873 #define MSGTXDATA3 0xFE47
0874 #define MSGTXCTL 0xFE48
0875 #define PETXCFG 0xFE49
0876
0877 #define CDRESUMECTL 0xFE52
0878 #define WAKE_SEL_CTL 0xFE54
0879 #define PME_FORCE_CTL 0xFE56
0880 #define ASPM_FORCE_CTL 0xFE57
0881 #define PM_CLK_FORCE_CTL 0xFE58
0882 #define PERST_GLITCH_WIDTH 0xFE5C
0883 #define CHANGE_LINK_STATE 0xFE5B
0884 #define RESET_LOAD_REG 0xFE5E
0885 #define HOST_SLEEP_STATE 0xFE60
0886 #define MAIN_PWR_OFF_CTL 0xFE70
0887
0888 #define NFTS_TX_CTRL 0xFE72
0889
0890 #define PWR_GATE_CTRL 0xFE75
0891 #define PWD_SUSPEND_EN 0xFE76
0892
0893 #define EFUSE_CONTENT 0xFE5F
0894
0895 #define XD_INIT 0xFD10
0896 #define XD_DTCTL 0xFD11
0897 #define XD_CTL 0xFD12
0898 #define XD_TRANSFER 0xFD13
0899 #define XD_CFG 0xFD14
0900 #define XD_ADDRESS0 0xFD15
0901 #define XD_ADDRESS1 0xFD16
0902 #define XD_ADDRESS2 0xFD17
0903 #define XD_ADDRESS3 0xFD18
0904 #define XD_ADDRESS4 0xFD19
0905 #define XD_DAT 0xFD1A
0906 #define XD_PAGE_CNT 0xFD1B
0907 #define XD_PAGE_STATUS 0xFD1C
0908 #define XD_BLOCK_STATUS 0xFD1D
0909 #define XD_BLOCK_ADDR1_L 0xFD1E
0910 #define XD_BLOCK_ADDR1_H 0xFD1F
0911 #define XD_BLOCK_ADDR2_L 0xFD20
0912 #define XD_BLOCK_ADDR2_H 0xFD21
0913 #define XD_BYTE_CNT_L 0xFD22
0914 #define XD_BYTE_CNT_H 0xFD23
0915 #define XD_PARITY 0xFD24
0916 #define XD_ECC_BIT1 0xFD25
0917 #define XD_ECC_BYTE1 0xFD26
0918 #define XD_ECC_BIT2 0xFD27
0919 #define XD_ECC_BYTE2 0xFD28
0920 #define XD_RESERVED0 0xFD29
0921 #define XD_RESERVED1 0xFD2A
0922 #define XD_RESERVED2 0xFD2B
0923 #define XD_RESERVED3 0xFD2C
0924 #define XD_CHK_DATA_STATUS 0xFD2D
0925 #define XD_CATCTL 0xFD2E
0926
0927 #define MS_CFG 0xFD40
0928 #define MS_TPC 0xFD41
0929 #define MS_TRANS_CFG 0xFD42
0930 #define MS_TRANSFER 0xFD43
0931 #define MS_INT_REG 0xFD44
0932 #define MS_BYTE_CNT 0xFD45
0933 #define MS_SECTOR_CNT_L 0xFD46
0934 #define MS_SECTOR_CNT_H 0xFD47
0935 #define MS_DBUS_H 0xFD48
0936
0937 #define SSC_CTL1 0xFC11
0938 #define SSC_CTL2 0xFC12
0939
0940 #define OCPCTL 0xFC15
0941 #define OCPSTAT 0xFC16
0942 #define OCPCLR 0xFC17
0943 #define OCPPARA1 0xFC18
0944 #define OCPPARA2 0xFC19
0945
0946 #define EFUSE_OP 0xFC20
0947 #define EFUSE_CTRL 0xFC21
0948 #define EFUSE_DATA 0xFC22
0949
0950 #define SPI_COMMAND 0xFD80
0951 #define SPI_ADDR0 0xFD81
0952 #define SPI_ADDR1 0xFD82
0953 #define SPI_ADDR2 0xFD83
0954 #define SPI_ADDR3 0xFD84
0955 #define SPI_CA_NUMBER 0xFD85
0956 #define SPI_LENGTH0 0xFD86
0957 #define SPI_LENGTH1 0xFD87
0958 #define SPI_DATA 0xFD88
0959 #define SPI_DATA_NUMBER 0xFD89
0960 #define SPI_TRANSFER0 0xFD90
0961 #define SPI_TRANSFER1 0xFD91
0962 #define SPI_CONTROL 0xFD92
0963 #define SPI_SIG 0xFD93
0964 #define SPI_TCTL 0xFD94
0965 #define SPI_SLAVE_NUM 0xFD95
0966 #define SPI_CLK_DIVIDER0 0xFD96
0967 #define SPI_CLK_DIVIDER1 0xFD97
0968
0969 #define SRAM_BASE 0xE600
0970 #define RBUF_BASE 0xF400
0971 #define PPBUF_BASE1 0xF800
0972 #define PPBUF_BASE2 0xFA00
0973 #define IMAGE_FLAG_ADDR0 0xCE80
0974 #define IMAGE_FLAG_ADDR1 0xCE81
0975
0976 #define READ_OP 1
0977 #define WRITE_OP 2
0978
0979 #define LCTLR 0x80
0980
0981 #define POLLING_WAIT_CNT 1
0982 #define IDLE_MAX_COUNT 10
0983 #define SDIO_IDLE_COUNT 10
0984
0985 #define DEBOUNCE_CNT 5
0986
0987 void do_remaining_work(struct rtsx_chip *chip);
0988 void try_to_switch_sdio_ctrl(struct rtsx_chip *chip);
0989 void do_reset_sd_card(struct rtsx_chip *chip);
0990 void do_reset_xd_card(struct rtsx_chip *chip);
0991 void do_reset_ms_card(struct rtsx_chip *chip);
0992 void rtsx_power_off_card(struct rtsx_chip *chip);
0993 void rtsx_release_cards(struct rtsx_chip *chip);
0994 void rtsx_reset_cards(struct rtsx_chip *chip);
0995 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip);
0996 void rtsx_init_cards(struct rtsx_chip *chip);
0997 int switch_ssc_clock(struct rtsx_chip *chip, int clk);
0998 int switch_normal_clock(struct rtsx_chip *chip, int clk);
0999 int enable_card_clock(struct rtsx_chip *chip, u8 card);
1000 int disable_card_clock(struct rtsx_chip *chip, u8 card);
1001 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
1002 u32 sec_addr, u16 sec_cnt);
1003 void trans_dma_enable(enum dma_data_direction dir,
1004 struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size);
1005 void toggle_gpio(struct rtsx_chip *chip, u8 gpio);
1006 void turn_on_led(struct rtsx_chip *chip, u8 gpio);
1007 void turn_off_led(struct rtsx_chip *chip, u8 gpio);
1008
1009 int card_share_mode(struct rtsx_chip *chip, int card);
1010 int select_card(struct rtsx_chip *chip, int card);
1011 int detect_card_cd(struct rtsx_chip *chip, int card);
1012 int check_card_exist(struct rtsx_chip *chip, unsigned int lun);
1013 int check_card_ready(struct rtsx_chip *chip, unsigned int lun);
1014 int check_card_wp(struct rtsx_chip *chip, unsigned int lun);
1015 void eject_card(struct rtsx_chip *chip, unsigned int lun);
1016 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun);
1017
1018 static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun)
1019 {
1020 #ifdef SUPPORT_SD_LOCK
1021 struct sd_info *sd_card = &chip->sd_card;
1022
1023 if ((get_lun_card(chip, lun) == SD_CARD) &&
1024 (sd_card->sd_lock_status & SD_LOCKED))
1025 return 0;
1026
1027 return chip->capacity[lun];
1028 #else
1029 return chip->capacity[lun];
1030 #endif
1031 }
1032
1033 static inline int switch_clock(struct rtsx_chip *chip, int clk)
1034 {
1035 int retval = 0;
1036
1037 if (chip->asic_code)
1038 retval = switch_ssc_clock(chip, clk);
1039 else
1040 retval = switch_normal_clock(chip, clk);
1041
1042 return retval;
1043 }
1044
1045 int card_power_on(struct rtsx_chip *chip, u8 card);
1046 int card_power_off(struct rtsx_chip *chip, u8 card);
1047
1048 static inline int card_power_off_all(struct rtsx_chip *chip)
1049 {
1050 int retval;
1051
1052 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F);
1053 if (retval)
1054 return retval;
1055
1056 return STATUS_SUCCESS;
1057 }
1058
1059 static inline void rtsx_clear_xd_error(struct rtsx_chip *chip)
1060 {
1061 rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
1062 XD_STOP | XD_CLR_ERR);
1063 }
1064
1065 static inline void rtsx_clear_sd_error(struct rtsx_chip *chip)
1066 {
1067 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
1068 SD_STOP | SD_CLR_ERR);
1069 }
1070
1071 static inline void rtsx_clear_ms_error(struct rtsx_chip *chip)
1072 {
1073 rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR,
1074 MS_STOP | MS_CLR_ERR);
1075 }
1076
1077 static inline void rtsx_clear_spi_error(struct rtsx_chip *chip)
1078 {
1079 rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR,
1080 SPI_STOP | SPI_CLR_ERR);
1081 }
1082
1083 #ifdef SUPPORT_SDIO_ASPM
1084 void dynamic_configure_sdio_aspm(struct rtsx_chip *chip);
1085 #endif
1086
1087 #endif
