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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for Realtek PCI-Express card reader
0004  *
0005  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0006  *
0007  * Author:
0008  *   Wei WANG (wei_wang@realsil.com.cn)
0009  *   Micky Ching (micky_ching@realsil.com.cn)
0010  */
0011 
0012 #include <linux/blkdev.h>
0013 #include <linux/kthread.h>
0014 #include <linux/sched.h>
0015 #include <linux/workqueue.h>
0016 #include <linux/kernel.h>
0017 
0018 #include "rtsx.h"
0019 #include "sd.h"
0020 #include "xd.h"
0021 #include "ms.h"
0022 
0023 void do_remaining_work(struct rtsx_chip *chip)
0024 {
0025     struct sd_info *sd_card = &chip->sd_card;
0026 #ifdef XD_DELAY_WRITE
0027     struct xd_info *xd_card = &chip->xd_card;
0028 #endif
0029     struct ms_info *ms_card = &chip->ms_card;
0030 
0031     if (chip->card_ready & SD_CARD) {
0032         if (sd_card->seq_mode) {
0033             rtsx_set_stat(chip, RTSX_STAT_RUN);
0034             sd_card->cleanup_counter++;
0035         } else {
0036             sd_card->cleanup_counter = 0;
0037         }
0038     }
0039 
0040 #ifdef XD_DELAY_WRITE
0041     if (chip->card_ready & XD_CARD) {
0042         if (xd_card->delay_write.delay_write_flag) {
0043             rtsx_set_stat(chip, RTSX_STAT_RUN);
0044             xd_card->cleanup_counter++;
0045         } else {
0046             xd_card->cleanup_counter = 0;
0047         }
0048     }
0049 #endif
0050 
0051     if (chip->card_ready & MS_CARD) {
0052         if (CHK_MSPRO(ms_card)) {
0053             if (ms_card->seq_mode) {
0054                 rtsx_set_stat(chip, RTSX_STAT_RUN);
0055                 ms_card->cleanup_counter++;
0056             } else {
0057                 ms_card->cleanup_counter = 0;
0058             }
0059         } else {
0060 #ifdef MS_DELAY_WRITE
0061             if (ms_card->delay_write.delay_write_flag) {
0062                 rtsx_set_stat(chip, RTSX_STAT_RUN);
0063                 ms_card->cleanup_counter++;
0064             } else {
0065                 ms_card->cleanup_counter = 0;
0066             }
0067 #endif
0068         }
0069     }
0070 
0071     if (sd_card->cleanup_counter > POLLING_WAIT_CNT)
0072         sd_cleanup_work(chip);
0073 
0074     if (xd_card->cleanup_counter > POLLING_WAIT_CNT)
0075         xd_cleanup_work(chip);
0076 
0077     if (ms_card->cleanup_counter > POLLING_WAIT_CNT)
0078         ms_cleanup_work(chip);
0079 }
0080 
0081 void try_to_switch_sdio_ctrl(struct rtsx_chip *chip)
0082 {
0083     u8 reg1 = 0, reg2 = 0;
0084 
0085     rtsx_read_register(chip, 0xFF34, &reg1);
0086     rtsx_read_register(chip, 0xFF38, &reg2);
0087     dev_dbg(rtsx_dev(chip), "reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n",
0088         reg1, reg2);
0089     if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
0090         chip->sd_int = 1;
0091         rtsx_write_register(chip, SDIO_CTRL, 0xFF,
0092                     SDIO_BUS_CTRL | SDIO_CD_CTRL);
0093         rtsx_write_register(chip, PWR_GATE_CTRL,
0094                     LDO3318_PWR_MASK, LDO_ON);
0095     }
0096 }
0097 
0098 #ifdef SUPPORT_SDIO_ASPM
0099 void dynamic_configure_sdio_aspm(struct rtsx_chip *chip)
0100 {
0101     u8 buf[12], reg;
0102     int i;
0103 
0104     for (i = 0; i < 12; i++)
0105         rtsx_read_register(chip, 0xFF08 + i, &buf[i]);
0106     rtsx_read_register(chip, 0xFF25, &reg);
0107     if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) {
0108         chip->sdio_counter = 0;
0109         chip->sdio_idle = 0;
0110     } else {
0111         if (!chip->sdio_idle) {
0112             chip->sdio_counter++;
0113             if (chip->sdio_counter >= SDIO_IDLE_COUNT) {
0114                 chip->sdio_counter = 0;
0115                 chip->sdio_idle = 1;
0116             }
0117         }
0118     }
0119     memcpy(chip->sdio_raw_data, buf, 12);
0120 
0121     if (chip->sdio_idle) {
0122         if (!chip->sdio_aspm) {
0123             dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
0124             rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC,
0125                         0x30 | (chip->aspm_level[1] << 2));
0126             chip->sdio_aspm = 1;
0127         }
0128     } else {
0129         if (chip->sdio_aspm) {
0130             dev_dbg(rtsx_dev(chip), "SDIO exit ASPM!\n");
0131             rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30);
0132             chip->sdio_aspm = 0;
0133         }
0134     }
0135 }
0136 #endif
0137 
0138 void do_reset_sd_card(struct rtsx_chip *chip)
0139 {
0140     int retval;
0141 
0142     dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
0143         chip->sd_reset_counter, chip->card2lun[SD_CARD]);
0144 
0145     if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) {
0146         clear_bit(SD_NR, &chip->need_reset);
0147         chip->sd_reset_counter = 0;
0148         chip->sd_show_cnt = 0;
0149         return;
0150     }
0151 
0152     chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
0153 
0154     rtsx_set_stat(chip, RTSX_STAT_RUN);
0155     rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
0156 
0157     retval = reset_sd_card(chip);
0158     if (chip->need_release & SD_CARD)
0159         return;
0160     if (retval == STATUS_SUCCESS) {
0161         clear_bit(SD_NR, &chip->need_reset);
0162         chip->sd_reset_counter = 0;
0163         chip->sd_show_cnt = 0;
0164         chip->card_ready |= SD_CARD;
0165         chip->card_fail &= ~SD_CARD;
0166         chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
0167     } else {
0168         if (chip->sd_io || chip->sd_reset_counter >= MAX_RESET_CNT) {
0169             clear_bit(SD_NR, &chip->need_reset);
0170             chip->sd_reset_counter = 0;
0171             chip->sd_show_cnt = 0;
0172         } else {
0173             chip->sd_reset_counter++;
0174         }
0175         chip->card_ready &= ~SD_CARD;
0176         chip->card_fail |= SD_CARD;
0177         chip->capacity[chip->card2lun[SD_CARD]] = 0;
0178         chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
0179 
0180         rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
0181         if (!chip->ft2_fast_mode)
0182             card_power_off(chip, SD_CARD);
0183         if (chip->sd_io) {
0184             chip->sd_int = 0;
0185             try_to_switch_sdio_ctrl(chip);
0186         } else {
0187             disable_card_clock(chip, SD_CARD);
0188         }
0189     }
0190 }
0191 
0192 void do_reset_xd_card(struct rtsx_chip *chip)
0193 {
0194     int retval;
0195 
0196     dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
0197         chip->xd_reset_counter, chip->card2lun[XD_CARD]);
0198 
0199     if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) {
0200         clear_bit(XD_NR, &chip->need_reset);
0201         chip->xd_reset_counter = 0;
0202         chip->xd_show_cnt = 0;
0203         return;
0204     }
0205 
0206     chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
0207 
0208     rtsx_set_stat(chip, RTSX_STAT_RUN);
0209     rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
0210 
0211     retval = reset_xd_card(chip);
0212     if (chip->need_release & XD_CARD)
0213         return;
0214     if (retval == STATUS_SUCCESS) {
0215         clear_bit(XD_NR, &chip->need_reset);
0216         chip->xd_reset_counter = 0;
0217         chip->card_ready |= XD_CARD;
0218         chip->card_fail &= ~XD_CARD;
0219         chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
0220     } else {
0221         if (chip->xd_reset_counter >= MAX_RESET_CNT) {
0222             clear_bit(XD_NR, &chip->need_reset);
0223             chip->xd_reset_counter = 0;
0224             chip->xd_show_cnt = 0;
0225         } else {
0226             chip->xd_reset_counter++;
0227         }
0228         chip->card_ready &= ~XD_CARD;
0229         chip->card_fail |= XD_CARD;
0230         chip->capacity[chip->card2lun[XD_CARD]] = 0;
0231         chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
0232 
0233         rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
0234         if (!chip->ft2_fast_mode)
0235             card_power_off(chip, XD_CARD);
0236         disable_card_clock(chip, XD_CARD);
0237     }
0238 }
0239 
0240 void do_reset_ms_card(struct rtsx_chip *chip)
0241 {
0242     int retval;
0243 
0244     dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
0245         chip->ms_reset_counter, chip->card2lun[MS_CARD]);
0246 
0247     if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) {
0248         clear_bit(MS_NR, &chip->need_reset);
0249         chip->ms_reset_counter = 0;
0250         chip->ms_show_cnt = 0;
0251         return;
0252     }
0253 
0254     chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
0255 
0256     rtsx_set_stat(chip, RTSX_STAT_RUN);
0257     rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
0258 
0259     retval = reset_ms_card(chip);
0260     if (chip->need_release & MS_CARD)
0261         return;
0262     if (retval == STATUS_SUCCESS) {
0263         clear_bit(MS_NR, &chip->need_reset);
0264         chip->ms_reset_counter = 0;
0265         chip->card_ready |= MS_CARD;
0266         chip->card_fail &= ~MS_CARD;
0267         chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
0268     } else {
0269         if (chip->ms_reset_counter >= MAX_RESET_CNT) {
0270             clear_bit(MS_NR, &chip->need_reset);
0271             chip->ms_reset_counter = 0;
0272             chip->ms_show_cnt = 0;
0273         } else {
0274             chip->ms_reset_counter++;
0275         }
0276         chip->card_ready &= ~MS_CARD;
0277         chip->card_fail |= MS_CARD;
0278         chip->capacity[chip->card2lun[MS_CARD]] = 0;
0279         chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
0280 
0281         rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
0282         if (!chip->ft2_fast_mode)
0283             card_power_off(chip, MS_CARD);
0284         disable_card_clock(chip, MS_CARD);
0285     }
0286 }
0287 
0288 static void release_sdio(struct rtsx_chip *chip)
0289 {
0290     if (chip->sd_io) {
0291         rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
0292                     SD_STOP | SD_CLR_ERR);
0293 
0294         if (chip->chip_insert_with_sdio) {
0295             chip->chip_insert_with_sdio = 0;
0296 
0297             if (CHECK_PID(chip, 0x5288))
0298                 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00);
0299             else
0300                 rtsx_write_register(chip, 0xFE70, 0x80, 0x00);
0301         }
0302 
0303         rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0);
0304         chip->sd_io = 0;
0305     }
0306 }
0307 
0308 void rtsx_power_off_card(struct rtsx_chip *chip)
0309 {
0310     if ((chip->card_ready & SD_CARD) || chip->sd_io) {
0311         sd_cleanup_work(chip);
0312         sd_power_off_card3v3(chip);
0313     }
0314 
0315     if (chip->card_ready & XD_CARD) {
0316         xd_cleanup_work(chip);
0317         xd_power_off_card3v3(chip);
0318     }
0319 
0320     if (chip->card_ready & MS_CARD) {
0321         ms_cleanup_work(chip);
0322         ms_power_off_card3v3(chip);
0323     }
0324 }
0325 
0326 void rtsx_release_cards(struct rtsx_chip *chip)
0327 {
0328     chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
0329 
0330     if ((chip->card_ready & SD_CARD) || chip->sd_io) {
0331         if (chip->int_reg & SD_EXIST)
0332             sd_cleanup_work(chip);
0333         release_sd_card(chip);
0334     }
0335 
0336     if (chip->card_ready & XD_CARD) {
0337         if (chip->int_reg & XD_EXIST)
0338             xd_cleanup_work(chip);
0339         release_xd_card(chip);
0340     }
0341 
0342     if (chip->card_ready & MS_CARD) {
0343         if (chip->int_reg & MS_EXIST)
0344             ms_cleanup_work(chip);
0345         release_ms_card(chip);
0346     }
0347 }
0348 
0349 void rtsx_reset_cards(struct rtsx_chip *chip)
0350 {
0351     if (!chip->need_reset)
0352         return;
0353 
0354     rtsx_set_stat(chip, RTSX_STAT_RUN);
0355 
0356     rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
0357 
0358     rtsx_disable_aspm(chip);
0359 
0360     if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio)
0361         clear_bit(SD_NR, &chip->need_reset);
0362 
0363     if (chip->need_reset & XD_CARD) {
0364         chip->card_exist |= XD_CARD;
0365 
0366         if (chip->xd_show_cnt >= MAX_SHOW_CNT)
0367             do_reset_xd_card(chip);
0368         else
0369             chip->xd_show_cnt++;
0370     }
0371     if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
0372         if (chip->card_exist & XD_CARD) {
0373             clear_bit(SD_NR, &chip->need_reset);
0374             clear_bit(MS_NR, &chip->need_reset);
0375         }
0376     }
0377     if (chip->need_reset & SD_CARD) {
0378         chip->card_exist |= SD_CARD;
0379 
0380         if (chip->sd_show_cnt >= MAX_SHOW_CNT) {
0381             rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
0382             do_reset_sd_card(chip);
0383         } else {
0384             chip->sd_show_cnt++;
0385         }
0386     }
0387     if (chip->need_reset & MS_CARD) {
0388         chip->card_exist |= MS_CARD;
0389 
0390         if (chip->ms_show_cnt >= MAX_SHOW_CNT)
0391             do_reset_ms_card(chip);
0392         else
0393             chip->ms_show_cnt++;
0394     }
0395 }
0396 
0397 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip)
0398 {
0399     rtsx_set_stat(chip, RTSX_STAT_RUN);
0400 
0401     rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
0402 
0403     if (reset_chip)
0404         rtsx_reset_chip(chip);
0405 
0406     chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
0407 
0408     if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) {
0409         release_sdio(chip);
0410         release_sd_card(chip);
0411 
0412         wait_timeout(100);
0413 
0414         chip->card_exist |= SD_CARD;
0415         do_reset_sd_card(chip);
0416     }
0417 
0418     if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) {
0419         release_xd_card(chip);
0420 
0421         wait_timeout(100);
0422 
0423         chip->card_exist |= XD_CARD;
0424         do_reset_xd_card(chip);
0425     }
0426 
0427     if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) {
0428         release_ms_card(chip);
0429 
0430         wait_timeout(100);
0431 
0432         chip->card_exist |= MS_CARD;
0433         do_reset_ms_card(chip);
0434     }
0435 
0436     chip->need_reinit = 0;
0437 }
0438 
0439 #ifdef DISABLE_CARD_INT
0440 void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset,
0441               unsigned long *need_release)
0442 {
0443     u8 release_map = 0, reset_map = 0;
0444 
0445     chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
0446 
0447     if (chip->card_exist) {
0448         if (chip->card_exist & XD_CARD) {
0449             if (!(chip->int_reg & XD_EXIST))
0450                 release_map |= XD_CARD;
0451         } else if (chip->card_exist & SD_CARD) {
0452             if (!(chip->int_reg & SD_EXIST))
0453                 release_map |= SD_CARD;
0454         } else if (chip->card_exist & MS_CARD) {
0455             if (!(chip->int_reg & MS_EXIST))
0456                 release_map |= MS_CARD;
0457         }
0458     } else {
0459         if (chip->int_reg & XD_EXIST)
0460             reset_map |= XD_CARD;
0461         else if (chip->int_reg & SD_EXIST)
0462             reset_map |= SD_CARD;
0463         else if (chip->int_reg & MS_EXIST)
0464             reset_map |= MS_CARD;
0465     }
0466 
0467     if (reset_map) {
0468         int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
0469         int i;
0470 
0471         for (i = 0; i < (DEBOUNCE_CNT); i++) {
0472             chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
0473 
0474             if (chip->int_reg & XD_EXIST)
0475                 xd_cnt++;
0476             else
0477                 xd_cnt = 0;
0478 
0479             if (chip->int_reg & SD_EXIST)
0480                 sd_cnt++;
0481             else
0482                 sd_cnt = 0;
0483 
0484             if (chip->int_reg & MS_EXIST)
0485                 ms_cnt++;
0486             else
0487                 ms_cnt = 0;
0488 
0489             wait_timeout(30);
0490         }
0491 
0492         reset_map = 0;
0493         if (!(chip->card_exist & XD_CARD) &&
0494             (xd_cnt > (DEBOUNCE_CNT - 1)))
0495             reset_map |= XD_CARD;
0496         if (!(chip->card_exist & SD_CARD) &&
0497             (sd_cnt > (DEBOUNCE_CNT - 1)))
0498             reset_map |= SD_CARD;
0499         if (!(chip->card_exist & MS_CARD) &&
0500             (ms_cnt > (DEBOUNCE_CNT - 1)))
0501             reset_map |= MS_CARD;
0502     }
0503 
0504     if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
0505         rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00);
0506 
0507     if (need_reset)
0508         *need_reset = reset_map;
0509     if (need_release)
0510         *need_release = release_map;
0511 }
0512 #endif
0513 
0514 void rtsx_init_cards(struct rtsx_chip *chip)
0515 {
0516     if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
0517         dev_dbg(rtsx_dev(chip), "Reset chip in polling thread!\n");
0518         rtsx_reset_chip(chip);
0519         RTSX_CLR_DELINK(chip);
0520     }
0521 
0522 #ifdef DISABLE_CARD_INT
0523     card_cd_debounce(chip, &chip->need_reset, &chip->need_release);
0524 #endif
0525 
0526     if (chip->need_release) {
0527         if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
0528             if (chip->int_reg & XD_EXIST) {
0529                 clear_bit(SD_NR, &chip->need_release);
0530                 clear_bit(MS_NR, &chip->need_release);
0531             }
0532         }
0533 
0534         if (!(chip->card_exist & SD_CARD) && !chip->sd_io)
0535             clear_bit(SD_NR, &chip->need_release);
0536         if (!(chip->card_exist & XD_CARD))
0537             clear_bit(XD_NR, &chip->need_release);
0538         if (!(chip->card_exist & MS_CARD))
0539             clear_bit(MS_NR, &chip->need_release);
0540 
0541         dev_dbg(rtsx_dev(chip), "chip->need_release = 0x%x\n",
0542             (unsigned int)(chip->need_release));
0543 
0544 #ifdef SUPPORT_OCP
0545         if (chip->need_release) {
0546             if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER))
0547                 rtsx_write_register(chip, OCPCLR,
0548                             CARD_OC_INT_CLR |
0549                             CARD_OC_CLR,
0550                             CARD_OC_INT_CLR |
0551                             CARD_OC_CLR);
0552             chip->ocp_stat = 0;
0553         }
0554 #endif
0555         if (chip->need_release) {
0556             rtsx_set_stat(chip, RTSX_STAT_RUN);
0557             rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
0558         }
0559 
0560         if (chip->need_release & SD_CARD) {
0561             clear_bit(SD_NR, &chip->need_release);
0562             chip->card_exist &= ~SD_CARD;
0563             chip->card_ejected &= ~SD_CARD;
0564             chip->card_fail &= ~SD_CARD;
0565             CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]);
0566             chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
0567             rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
0568 
0569             release_sdio(chip);
0570             release_sd_card(chip);
0571         }
0572 
0573         if (chip->need_release & XD_CARD) {
0574             clear_bit(XD_NR, &chip->need_release);
0575             chip->card_exist &= ~XD_CARD;
0576             chip->card_ejected &= ~XD_CARD;
0577             chip->card_fail &= ~XD_CARD;
0578             CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]);
0579             chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
0580 
0581             release_xd_card(chip);
0582 
0583             if (CHECK_PID(chip, 0x5288) &&
0584                 CHECK_BARO_PKG(chip, QFN))
0585                 rtsx_write_register(chip, HOST_SLEEP_STATE,
0586                             0xC0, 0xC0);
0587         }
0588 
0589         if (chip->need_release & MS_CARD) {
0590             clear_bit(MS_NR, &chip->need_release);
0591             chip->card_exist &= ~MS_CARD;
0592             chip->card_ejected &= ~MS_CARD;
0593             chip->card_fail &= ~MS_CARD;
0594             CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]);
0595             chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
0596 
0597             release_ms_card(chip);
0598         }
0599 
0600         dev_dbg(rtsx_dev(chip), "chip->card_exist = 0x%x\n",
0601             chip->card_exist);
0602 
0603         if (!chip->card_exist)
0604             turn_off_led(chip, LED_GPIO);
0605     }
0606 
0607     if (chip->need_reset) {
0608         dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x\n",
0609             (unsigned int)(chip->need_reset));
0610 
0611         rtsx_reset_cards(chip);
0612     }
0613 
0614     if (chip->need_reinit) {
0615         dev_dbg(rtsx_dev(chip), "chip->need_reinit = 0x%x\n",
0616             (unsigned int)(chip->need_reinit));
0617 
0618         rtsx_reinit_cards(chip, 0);
0619     }
0620 }
0621 
0622 int switch_ssc_clock(struct rtsx_chip *chip, int clk)
0623 {
0624     int retval;
0625     u8 n = (u8)(clk - 2), min_n, max_n;
0626     u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask;
0627     int sd_vpclk_phase_reset = 0;
0628 
0629     if (chip->cur_clk == clk)
0630         return STATUS_SUCCESS;
0631 
0632     min_n = 60;
0633     max_n = 120;
0634     max_div = CLK_DIV_4;
0635 
0636     dev_dbg(rtsx_dev(chip), "Switch SSC clock to %dMHz (cur_clk = %d)\n",
0637         clk, chip->cur_clk);
0638 
0639     if (clk <= 2 || n > max_n)
0640         return STATUS_FAIL;
0641 
0642     mcu_cnt = (u8)(125 / clk + 3);
0643     if (mcu_cnt > 7)
0644         mcu_cnt = 7;
0645 
0646     div = CLK_DIV_1;
0647     while ((n < min_n) && (div < max_div)) {
0648         n = (n + 2) * 2 - 2;
0649         div++;
0650     }
0651     dev_dbg(rtsx_dev(chip), "n = %d, div = %d\n", n, div);
0652 
0653     if (chip->ssc_en) {
0654         ssc_depth = 0x01;
0655         n -= 2;
0656     } else {
0657         ssc_depth = 0;
0658     }
0659 
0660     ssc_depth_mask = 0x03;
0661 
0662     dev_dbg(rtsx_dev(chip), "ssc_depth = %d\n", ssc_depth);
0663 
0664     rtsx_init_cmd(chip);
0665     rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
0666     rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
0667     rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
0668     rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth);
0669     rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
0670     rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
0671     if (sd_vpclk_phase_reset) {
0672         rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
0673                  PHASE_NOT_RESET, 0);
0674         rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
0675                  PHASE_NOT_RESET, PHASE_NOT_RESET);
0676     }
0677 
0678     retval = rtsx_send_cmd(chip, 0, WAIT_TIME);
0679     if (retval < 0)
0680         return STATUS_ERROR;
0681 
0682     udelay(10);
0683     retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0);
0684     if (retval)
0685         return retval;
0686 
0687     chip->cur_clk = clk;
0688 
0689     return STATUS_SUCCESS;
0690 }
0691 
0692 int switch_normal_clock(struct rtsx_chip *chip, int clk)
0693 {
0694     int retval;
0695     u8 sel, div, mcu_cnt;
0696     int sd_vpclk_phase_reset = 0;
0697 
0698     if (chip->cur_clk == clk)
0699         return STATUS_SUCCESS;
0700 
0701     switch (clk) {
0702     case CLK_20:
0703         dev_dbg(rtsx_dev(chip), "Switch clock to 20MHz\n");
0704         sel = SSC_80;
0705         div = CLK_DIV_4;
0706         mcu_cnt = 7;
0707         break;
0708 
0709     case CLK_30:
0710         dev_dbg(rtsx_dev(chip), "Switch clock to 30MHz\n");
0711         sel = SSC_120;
0712         div = CLK_DIV_4;
0713         mcu_cnt = 7;
0714         break;
0715 
0716     case CLK_40:
0717         dev_dbg(rtsx_dev(chip), "Switch clock to 40MHz\n");
0718         sel = SSC_80;
0719         div = CLK_DIV_2;
0720         mcu_cnt = 7;
0721         break;
0722 
0723     case CLK_50:
0724         dev_dbg(rtsx_dev(chip), "Switch clock to 50MHz\n");
0725         sel = SSC_100;
0726         div = CLK_DIV_2;
0727         mcu_cnt = 6;
0728         break;
0729 
0730     case CLK_60:
0731         dev_dbg(rtsx_dev(chip), "Switch clock to 60MHz\n");
0732         sel = SSC_120;
0733         div = CLK_DIV_2;
0734         mcu_cnt = 6;
0735         break;
0736 
0737     case CLK_80:
0738         dev_dbg(rtsx_dev(chip), "Switch clock to 80MHz\n");
0739         sel = SSC_80;
0740         div = CLK_DIV_1;
0741         mcu_cnt = 5;
0742         break;
0743 
0744     case CLK_100:
0745         dev_dbg(rtsx_dev(chip), "Switch clock to 100MHz\n");
0746         sel = SSC_100;
0747         div = CLK_DIV_1;
0748         mcu_cnt = 5;
0749         break;
0750 
0751     case CLK_120:
0752         dev_dbg(rtsx_dev(chip), "Switch clock to 120MHz\n");
0753         sel = SSC_120;
0754         div = CLK_DIV_1;
0755         mcu_cnt = 5;
0756         break;
0757 
0758     case CLK_150:
0759         dev_dbg(rtsx_dev(chip), "Switch clock to 150MHz\n");
0760         sel = SSC_150;
0761         div = CLK_DIV_1;
0762         mcu_cnt = 4;
0763         break;
0764 
0765     case CLK_200:
0766         dev_dbg(rtsx_dev(chip), "Switch clock to 200MHz\n");
0767         sel = SSC_200;
0768         div = CLK_DIV_1;
0769         mcu_cnt = 4;
0770         break;
0771 
0772     default:
0773         dev_dbg(rtsx_dev(chip), "Try to switch to an illegal clock (%d)\n",
0774             clk);
0775         return STATUS_FAIL;
0776     }
0777 
0778     retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);
0779     if (retval)
0780         return retval;
0781     if (sd_vpclk_phase_reset) {
0782         retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
0783                          PHASE_NOT_RESET, 0);
0784         if (retval)
0785             return retval;
0786         retval = rtsx_write_register(chip, SD_VPCLK1_CTL,
0787                          PHASE_NOT_RESET, 0);
0788         if (retval)
0789             return retval;
0790     }
0791     retval = rtsx_write_register(chip, CLK_DIV, 0xFF,
0792                      (div << 4) | mcu_cnt);
0793     if (retval)
0794         return retval;
0795     retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel);
0796     if (retval)
0797         return retval;
0798 
0799     if (sd_vpclk_phase_reset) {
0800         udelay(200);
0801         retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
0802                          PHASE_NOT_RESET, PHASE_NOT_RESET);
0803         if (retval)
0804             return retval;
0805         retval = rtsx_write_register(chip, SD_VPCLK1_CTL,
0806                          PHASE_NOT_RESET, PHASE_NOT_RESET);
0807         if (retval)
0808             return retval;
0809         udelay(200);
0810     }
0811     retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0);
0812     if (retval)
0813         return retval;
0814 
0815     chip->cur_clk = clk;
0816 
0817     return STATUS_SUCCESS;
0818 }
0819 
0820 void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip,
0821               u32 byte_cnt, u8 pack_size)
0822 {
0823     if (pack_size > DMA_1024)
0824         pack_size = DMA_512;
0825 
0826     rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT);
0827 
0828     rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24));
0829     rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16));
0830     rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8));
0831     rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt);
0832 
0833     if (dir == DMA_FROM_DEVICE) {
0834         rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL,
0835                  0x03 | DMA_PACK_SIZE_MASK,
0836                  DMA_DIR_FROM_CARD | DMA_EN | pack_size);
0837     } else {
0838         rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL,
0839                  0x03 | DMA_PACK_SIZE_MASK,
0840                  DMA_DIR_TO_CARD | DMA_EN | pack_size);
0841     }
0842 
0843     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
0844 }
0845 
0846 int enable_card_clock(struct rtsx_chip *chip, u8 card)
0847 {
0848     int retval;
0849     u8 clk_en = 0;
0850 
0851     if (card & XD_CARD)
0852         clk_en |= XD_CLK_EN;
0853     if (card & SD_CARD)
0854         clk_en |= SD_CLK_EN;
0855     if (card & MS_CARD)
0856         clk_en |= MS_CLK_EN;
0857 
0858     retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en);
0859     if (retval)
0860         return retval;
0861 
0862     return STATUS_SUCCESS;
0863 }
0864 
0865 int disable_card_clock(struct rtsx_chip *chip, u8 card)
0866 {
0867     int retval;
0868     u8 clk_en = 0;
0869 
0870     if (card & XD_CARD)
0871         clk_en |= XD_CLK_EN;
0872     if (card & SD_CARD)
0873         clk_en |= SD_CLK_EN;
0874     if (card & MS_CARD)
0875         clk_en |= MS_CLK_EN;
0876 
0877     retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0);
0878     if (retval)
0879         return retval;
0880 
0881     return STATUS_SUCCESS;
0882 }
0883 
0884 int card_power_on(struct rtsx_chip *chip, u8 card)
0885 {
0886     int retval;
0887     u8 mask, val1, val2;
0888 
0889     if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && card == MS_CARD) {
0890         mask = MS_POWER_MASK;
0891         val1 = MS_PARTIAL_POWER_ON;
0892         val2 = MS_POWER_ON;
0893     } else {
0894         mask = SD_POWER_MASK;
0895         val1 = SD_PARTIAL_POWER_ON;
0896         val2 = SD_POWER_ON;
0897     }
0898 
0899     rtsx_init_cmd(chip);
0900     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1);
0901 
0902     retval = rtsx_send_cmd(chip, 0, 100);
0903     if (retval != STATUS_SUCCESS)
0904         return STATUS_FAIL;
0905 
0906     udelay(chip->pmos_pwr_on_interval);
0907 
0908     rtsx_init_cmd(chip);
0909     rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2);
0910 
0911     retval = rtsx_send_cmd(chip, 0, 100);
0912     if (retval != STATUS_SUCCESS)
0913         return STATUS_FAIL;
0914 
0915     return STATUS_SUCCESS;
0916 }
0917 
0918 int card_power_off(struct rtsx_chip *chip, u8 card)
0919 {
0920     int retval;
0921     u8 mask, val;
0922 
0923     if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && card == MS_CARD) {
0924         mask = MS_POWER_MASK;
0925         val = MS_POWER_OFF;
0926     } else {
0927         mask = SD_POWER_MASK;
0928         val = SD_POWER_OFF;
0929     }
0930 
0931     retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val);
0932     if (retval)
0933         return retval;
0934 
0935     return STATUS_SUCCESS;
0936 }
0937 
0938 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
0939         u32 sec_addr, u16 sec_cnt)
0940 {
0941     int retval;
0942     unsigned int lun = SCSI_LUN(srb);
0943     int i;
0944 
0945     if (!chip->rw_card[lun])
0946         return STATUS_FAIL;
0947 
0948     for (i = 0; i < 3; i++) {
0949         chip->rw_need_retry = 0;
0950 
0951         retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt);
0952         if (retval != STATUS_SUCCESS) {
0953             if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) {
0954                 rtsx_release_chip(chip);
0955                 return STATUS_FAIL;
0956             }
0957             if (detect_card_cd(chip, chip->cur_card) !=
0958                             STATUS_SUCCESS) {
0959                 return STATUS_FAIL;
0960             }
0961 
0962             if (!chip->rw_need_retry) {
0963                 dev_dbg(rtsx_dev(chip), "RW fail, but no need to retry\n");
0964                 break;
0965             }
0966         } else {
0967             chip->rw_need_retry = 0;
0968             break;
0969         }
0970 
0971         dev_dbg(rtsx_dev(chip), "Retry RW, (i = %d)\n", i);
0972     }
0973 
0974     return retval;
0975 }
0976 
0977 int card_share_mode(struct rtsx_chip *chip, int card)
0978 {
0979     int retval;
0980     u8 mask, value;
0981 
0982     if (CHECK_PID(chip, 0x5208)) {
0983         mask = CARD_SHARE_MASK;
0984         if (card == SD_CARD)
0985             value = CARD_SHARE_48_SD;
0986         else if (card == MS_CARD)
0987             value = CARD_SHARE_48_MS;
0988         else if (card == XD_CARD)
0989             value = CARD_SHARE_48_XD;
0990         else
0991             return STATUS_FAIL;
0992 
0993     } else if (CHECK_PID(chip, 0x5288)) {
0994         mask = 0x03;
0995         if (card == SD_CARD)
0996             value = CARD_SHARE_BAROSSA_SD;
0997         else if (card == MS_CARD)
0998             value = CARD_SHARE_BAROSSA_MS;
0999         else if (card == XD_CARD)
1000             value = CARD_SHARE_BAROSSA_XD;
1001         else
1002             return STATUS_FAIL;
1003 
1004     } else {
1005         return STATUS_FAIL;
1006     }
1007 
1008     retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value);
1009     if (retval)
1010         return retval;
1011 
1012     return STATUS_SUCCESS;
1013 }
1014 
1015 int select_card(struct rtsx_chip *chip, int card)
1016 {
1017     int retval;
1018 
1019     if (chip->cur_card != card) {
1020         u8 mod;
1021 
1022         if (card == SD_CARD)
1023             mod = SD_MOD_SEL;
1024         else if (card == MS_CARD)
1025             mod = MS_MOD_SEL;
1026         else if (card == XD_CARD)
1027             mod = XD_MOD_SEL;
1028         else if (card == SPI_CARD)
1029             mod = SPI_MOD_SEL;
1030         else
1031             return STATUS_FAIL;
1032 
1033         retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod);
1034         if (retval)
1035             return retval;
1036         chip->cur_card = card;
1037 
1038         retval =  card_share_mode(chip, card);
1039         if (retval != STATUS_SUCCESS)
1040             return STATUS_FAIL;
1041     }
1042 
1043     return STATUS_SUCCESS;
1044 }
1045 
1046 void toggle_gpio(struct rtsx_chip *chip, u8 gpio)
1047 {
1048     u8 temp_reg;
1049 
1050     rtsx_read_register(chip, CARD_GPIO, &temp_reg);
1051     temp_reg ^= (0x01 << gpio);
1052     rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg);
1053 }
1054 
1055 void turn_on_led(struct rtsx_chip *chip, u8 gpio)
1056 {
1057     if (CHECK_PID(chip, 0x5288))
1058         rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio),
1059                     (u8)(1 << gpio));
1060     else
1061         rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1062 }
1063 
1064 void turn_off_led(struct rtsx_chip *chip, u8 gpio)
1065 {
1066     if (CHECK_PID(chip, 0x5288))
1067         rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1068     else
1069         rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio),
1070                     (u8)(1 << gpio));
1071 }
1072 
1073 int detect_card_cd(struct rtsx_chip *chip, int card)
1074 {
1075     u32 card_cd, status;
1076 
1077     if (card == SD_CARD) {
1078         card_cd = SD_EXIST;
1079     } else if (card == MS_CARD) {
1080         card_cd = MS_EXIST;
1081     } else if (card == XD_CARD) {
1082         card_cd = XD_EXIST;
1083     } else {
1084         dev_dbg(rtsx_dev(chip), "Wrong card type: 0x%x\n", card);
1085         return STATUS_FAIL;
1086     }
1087 
1088     status = rtsx_readl(chip, RTSX_BIPR);
1089     if (!(status & card_cd))
1090         return STATUS_FAIL;
1091 
1092     return STATUS_SUCCESS;
1093 }
1094 
1095 int check_card_exist(struct rtsx_chip *chip, unsigned int lun)
1096 {
1097     if (chip->card_exist & chip->lun2card[lun])
1098         return 1;
1099 
1100     return 0;
1101 }
1102 
1103 int check_card_ready(struct rtsx_chip *chip, unsigned int lun)
1104 {
1105     if (chip->card_ready & chip->lun2card[lun])
1106         return 1;
1107 
1108     return 0;
1109 }
1110 
1111 int check_card_wp(struct rtsx_chip *chip, unsigned int lun)
1112 {
1113     if (chip->card_wp & chip->lun2card[lun])
1114         return 1;
1115 
1116     return 0;
1117 }
1118 
1119 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun)
1120 {
1121     if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
1122         return (u8)XD_CARD;
1123     else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
1124         return (u8)SD_CARD;
1125     else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
1126         return (u8)MS_CARD;
1127 
1128     return 0;
1129 }
1130 
1131 void eject_card(struct rtsx_chip *chip, unsigned int lun)
1132 {
1133     do_remaining_work(chip);
1134 
1135     if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1136         release_sd_card(chip);
1137         chip->card_ejected |= SD_CARD;
1138         chip->card_ready &= ~SD_CARD;
1139         chip->capacity[lun] = 0;
1140     } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1141         release_xd_card(chip);
1142         chip->card_ejected |= XD_CARD;
1143         chip->card_ready &= ~XD_CARD;
1144         chip->capacity[lun] = 0;
1145     } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1146         release_ms_card(chip);
1147         chip->card_ejected |= MS_CARD;
1148         chip->card_ready &= ~MS_CARD;
1149         chip->capacity[lun] = 0;
1150     }
1151 }
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