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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /******************************************************************************
0003  *
0004  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
0005  *
0006  ******************************************************************************/
0007 
0008 
0009 #ifndef __HALDMOUTSRC_H__
0010 #define __HALDMOUTSRC_H__
0011 
0012 #include "odm_EdcaTurboCheck.h"
0013 #include "odm_DIG.h"
0014 #include "odm_DynamicBBPowerSaving.h"
0015 #include "odm_DynamicTxPower.h"
0016 #include "odm_CfoTracking.h"
0017 #include "odm_NoiseMonitor.h"
0018 
0019 #define TP_MODE     0
0020 #define RSSI_MODE       1
0021 #define TRAFFIC_LOW 0
0022 #define TRAFFIC_HIGH    1
0023 #define NONE            0
0024 
0025 /* 3 Tx Power Tracking */
0026 /* 3 ============================================================ */
0027 #define     DPK_DELTA_MAPPING_NUM   13
0028 #define     index_mapping_HP_NUM    15
0029 #define OFDM_TABLE_SIZE     43
0030 #define CCK_TABLE_SIZE          33
0031 #define TXSCALE_TABLE_SIZE      37
0032 #define TXPWR_TRACK_TABLE_SIZE  30
0033 #define DELTA_SWINGIDX_SIZE     30
0034 #define BAND_NUM                4
0035 
0036 /* 3 PSD Handler */
0037 /* 3 ============================================================ */
0038 
0039 #define AFH_PSD     1   /* 0:normal PSD scan, 1: only do 20 pts PSD */
0040 #define MODE_40M        0   /* 0:20M, 1:40M */
0041 #define PSD_TH2     3
0042 #define PSD_CHMIN       20   /*  Minimum channel number for BT AFH */
0043 #define SIR_STEP_SIZE   3
0044 #define   Smooth_Size_1     5
0045 #define Smooth_TH_1 3
0046 #define   Smooth_Size_2     10
0047 #define Smooth_TH_2 4
0048 #define   Smooth_Size_3     20
0049 #define Smooth_TH_3 4
0050 #define   Smooth_Step_Size 5
0051 #define Adaptive_SIR    1
0052 #define PSD_RESCAN      4
0053 #define PSD_SCAN_INTERVAL   700 /* ms */
0054 
0055 /* 8723A High Power IGI Setting */
0056 #define     DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
0057 #define         DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
0058 #define     DM_DIG_HIGH_PWR_THRESHOLD   0x3a
0059 #define     DM_DIG_LOW_PWR_THRESHOLD    0x14
0060 
0061 /* ANT Test */
0062 #define         ANTTESTALL      0x00        /* Ant A or B will be Testing */
0063 #define     ANTTESTA        0x01        /* Ant A will be Testing */
0064 #define     ANTTESTB        0x02        /* Ant B will be testing */
0065 
0066 #define PS_MODE_ACTIVE 0x01
0067 
0068 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
0069 #define     MAIN_ANT        1       /* Ant A or Ant Main */
0070 #define     AUX_ANT     2       /* AntB or Ant Aux */
0071 #define     MAX_ANT     3       /*  3 for AP using */
0072 
0073 /* Antenna Diversity Type */
0074 #define SW_ANTDIV   0
0075 #define HW_ANTDIV   1
0076 /*  structure and define */
0077 
0078 /* Remove DIG by Yuchen */
0079 
0080 /* Remoce BB power saving by Yuchn */
0081 
0082 /* Remove DIG by yuchen */
0083 
0084 struct dynamic_primary_CCA {
0085     u8 PriCCA_flag;
0086     u8 intf_flag;
0087     u8 intf_type;
0088     u8 DupRTS_flag;
0089     u8 Monitor_flag;
0090     u8 CH_offset;
0091     u8 MF_state;
0092 };
0093 
0094 struct ra_t {
0095     u8 firstconnect;
0096 };
0097 
0098 struct rxhp_t {
0099     u8 RXHP_flag;
0100     u8 PSD_func_trigger;
0101     u8 PSD_bitmap_RXHP[80];
0102     u8 Pre_IGI;
0103     u8 Cur_IGI;
0104     u8 Pre_pw_th;
0105     u8 Cur_pw_th;
0106     bool First_time_enter;
0107     bool RXHP_enable;
0108     u8 TP_Mode;
0109     struct timer_list PSDTimer;
0110 };
0111 
0112 #define ASSOCIATE_ENTRY_NUM                 32 /*  Max size of AsocEntry[]. */
0113 #define ODM_ASSOCIATE_ENTRY_NUM             ASSOCIATE_ENTRY_NUM
0114 
0115 /*  This indicates two different the steps. */
0116 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
0117 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
0118 /*  with original RSSI to determine if it is necessary to switch antenna. */
0119 #define SWAW_STEP_PEAK      0
0120 #define SWAW_STEP_DETERMINE 1
0121 
0122 #define TP_MODE     0
0123 #define RSSI_MODE       1
0124 #define TRAFFIC_LOW 0
0125 #define TRAFFIC_HIGH    1
0126 #define TRAFFIC_UltraLOW    2
0127 
0128 struct swat_t { /* _SW_Antenna_Switch_ */
0129     u8 Double_chk_flag;
0130     u8 try_flag;
0131     s32 PreRSSI;
0132     u8 CurAntenna;
0133     u8 PreAntenna;
0134     u8 RSSI_Trying;
0135     u8 TestMode;
0136     u8 bTriggerAntennaSwitch;
0137     u8 SelectAntennaMap;
0138     u8 RSSI_target;
0139     u8 reset_idx;
0140     u16 Single_Ant_Counter;
0141     u16 Dual_Ant_Counter;
0142     u16 Aux_FailDetec_Counter;
0143     u16 Retry_Counter;
0144 
0145     /*  Before link Antenna Switch check */
0146     u8 SWAS_NoLink_State;
0147     u32 SWAS_NoLink_BK_Reg860;
0148     u32 SWAS_NoLink_BK_Reg92c;
0149     u32 SWAS_NoLink_BK_Reg948;
0150     bool ANTA_ON;   /* To indicate Ant A is or not */
0151     bool ANTB_ON;   /* To indicate Ant B is on or not */
0152     bool Pre_Aux_FailDetec;
0153     bool RSSI_AntDect_bResult;
0154     u8 Ant2G;
0155 
0156     s32 RSSI_sum_A;
0157     s32 RSSI_sum_B;
0158     s32 RSSI_cnt_A;
0159     s32 RSSI_cnt_B;
0160 
0161     u64 lastTxOkCnt;
0162     u64 lastRxOkCnt;
0163     u64 TXByteCnt_A;
0164     u64 TXByteCnt_B;
0165     u64 RXByteCnt_A;
0166     u64 RXByteCnt_B;
0167     u8 TrafficLoad;
0168     u8 Train_time;
0169     u8 Train_time_flag;
0170     struct timer_list SwAntennaSwitchTimer;
0171     struct timer_list SwAntennaSwitchTimer_8723B;
0172     u32 PktCnt_SWAntDivByCtrlFrame;
0173     bool bSWAntDivByCtrlFrame;
0174 };
0175 
0176 /* Remove Edca by YuChen */
0177 
0178 
0179 struct odm_rate_adaptive {
0180     u8 Type;                /*  DM_Type_ByFW/DM_Type_ByDriver */
0181     u8 LdpcThres;           /*  if RSSI > LdpcThres => switch from LPDC to BCC */
0182     bool bUseLdpc;
0183     bool bLowerRtsRate;
0184     u8 HighRSSIThresh;      /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
0185     u8 LowRSSIThresh;       /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
0186     u8 RATRState;           /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
0187 
0188 };
0189 
0190 #define IQK_MAC_REG_NUM     4
0191 #define IQK_ADDA_REG_NUM        16
0192 #define IQK_BB_REG_NUM_MAX  10
0193 #define IQK_BB_REG_NUM      9
0194 #define HP_THERMAL_NUM      8
0195 
0196 #define AVG_THERMAL_NUM     8
0197 #define IQK_Matrix_REG_NUM  8
0198 #define IQK_Matrix_Settings_NUM 14 /* Channels_2_4G_NUM */
0199 
0200 #define     DM_Type_ByFW            0
0201 #define     DM_Type_ByDriver        1
0202 
0203 /*  */
0204 /*  Declare for common info */
0205 /*  */
0206 #define MAX_PATH_NUM_92CS       2
0207 #define MAX_PATH_NUM_8188E      1
0208 #define MAX_PATH_NUM_8192E      2
0209 #define MAX_PATH_NUM_8723B      1
0210 #define MAX_PATH_NUM_8812A      2
0211 #define MAX_PATH_NUM_8821A      1
0212 #define MAX_PATH_NUM_8814A      4
0213 #define MAX_PATH_NUM_8822B      2
0214 
0215 #define IQK_THRESHOLD           8
0216 #define DPK_THRESHOLD           4
0217 
0218 struct odm_phy_info {
0219     /*
0220      *  Be care, if you want to add any element, please insert it between
0221      *  rx_pwd_ball and signal_strength.
0222      */
0223     u8 rx_pwd_ba11;
0224 
0225     u8 signal_quality;             /* in 0-100 index. */
0226     s8 rx_mimo_signal_quality[4];  /* per-path's EVM */
0227     u8 rx_mimo_evm_dbm[4];         /* per-path's EVM dbm */
0228 
0229     u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
0230 
0231     u16 cfo_short[4];              /* per-path's Cfo_short */
0232     u16 cfo_tail[4];               /* per-path's Cfo_tail */
0233 
0234     s8 rx_power;                   /* in dBm Translate from PWdB */
0235 
0236     /*
0237      * Real power in dBm for this packet, no beautification and
0238      * aggregation. Keep this raw info to be used for the other procedures.
0239      */
0240     s8 recv_signal_power;
0241     u8 bt_rx_rssi_percentage;
0242     u8 signal_strength;        /* in 0-100 index. */
0243 
0244     s8 rx_pwr[4];                  /* per-path's pwdb */
0245 
0246     u8 rx_snr[4];                  /* per-path's SNR */
0247     u8 band_width;
0248     u8 bt_coex_pwr_adjust;
0249 };
0250 
0251 struct odm_packet_info {
0252     u8 data_rate;
0253     u8 station_id;
0254     bool bssid_match;
0255     bool to_self;
0256     bool is_beacon;
0257 };
0258 
0259 struct odm_phy_dbg_info {
0260     /* ODM Write, debug info */
0261     s8 RxSNRdB[4];
0262     u32 NumQryPhyStatus;
0263     u32 NumQryPhyStatusCCK;
0264     u32 NumQryPhyStatusOFDM;
0265     u8 NumQryBeaconPkt;
0266     /* Others */
0267     s32 RxEVM[4];
0268 
0269 };
0270 
0271 struct odm_mac_status_info {
0272     u8 test;
0273 };
0274 
0275 /*  */
0276 /*  2011/10/20 MH Define Common info enum for all team. */
0277 /*  */
0278 enum odm_cmninfo_e {
0279     /*  Fixed value: */
0280 
0281     /* HOOK BEFORE REG INIT----------- */
0282     ODM_CMNINFO_PLATFORM = 0,
0283     ODM_CMNINFO_ABILITY,                    /*  ODM_ABILITY_E */
0284     ODM_CMNINFO_INTERFACE,              /*  ODM_INTERFACE_E */
0285     ODM_CMNINFO_IC_TYPE,                    /*  ODM_IC_TYPE_E */
0286     ODM_CMNINFO_CUT_VER,                    /*  ODM_CUT_VERSION_E */
0287     ODM_CMNINFO_FAB_VER,                    /*  ODM_FAB_E */
0288     ODM_CMNINFO_RFE_TYPE,
0289     ODM_CMNINFO_PACKAGE_TYPE,
0290     ODM_CMNINFO_EXT_LNA,                    /*  true */
0291     ODM_CMNINFO_EXT_PA,
0292     ODM_CMNINFO_GPA,
0293     ODM_CMNINFO_APA,
0294     ODM_CMNINFO_GLNA,
0295     ODM_CMNINFO_ALNA,
0296     ODM_CMNINFO_EXT_TRSW,
0297     ODM_CMNINFO_PATCH_ID,               /* CUSTOMER ID */
0298     ODM_CMNINFO_BINHCT_TEST,
0299     ODM_CMNINFO_BWIFI_TEST,
0300     ODM_CMNINFO_SMART_CONCURRENT,
0301     /* HOOK BEFORE REG INIT----------- */
0302 
0303     /*  Dynamic value: */
0304 /*  POINTER REFERENCE----------- */
0305     ODM_CMNINFO_MAC_PHY_MODE,   /*  ODM_MAC_PHY_MODE_E */
0306     ODM_CMNINFO_TX_UNI,
0307     ODM_CMNINFO_RX_UNI,
0308     ODM_CMNINFO_WM_MODE,        /*  ODM_WIRELESS_MODE_E */
0309     ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
0310     ODM_CMNINFO_SEC_MODE,       /*  ODM_SECURITY_E */
0311     ODM_CMNINFO_BW,         /*  ODM_BW_E */
0312     ODM_CMNINFO_CHNL,
0313     ODM_CMNINFO_FORCED_RATE,
0314 
0315     ODM_CMNINFO_DMSP_GET_VALUE,
0316     ODM_CMNINFO_BUDDY_ADAPTOR,
0317     ODM_CMNINFO_DMSP_IS_MASTER,
0318     ODM_CMNINFO_SCAN,
0319     ODM_CMNINFO_POWER_SAVING,
0320     ODM_CMNINFO_ONE_PATH_CCA,   /*  ODM_CCA_PATH_E */
0321     ODM_CMNINFO_DRV_STOP,
0322     ODM_CMNINFO_PNP_IN,
0323     ODM_CMNINFO_INIT_ON,
0324     ODM_CMNINFO_ANT_TEST,
0325     ODM_CMNINFO_NET_CLOSED,
0326     ODM_CMNINFO_MP_MODE,
0327     /* ODM_CMNINFO_RTSTA_AID,    For win driver only? */
0328     ODM_CMNINFO_FORCED_IGI_LB,
0329     ODM_CMNINFO_IS1ANTENNA,
0330     ODM_CMNINFO_RFDEFAULTPATH,
0331 /*  POINTER REFERENCE----------- */
0332 
0333 /* CALL BY VALUE------------- */
0334     ODM_CMNINFO_WIFI_DIRECT,
0335     ODM_CMNINFO_WIFI_DISPLAY,
0336     ODM_CMNINFO_LINK_IN_PROGRESS,
0337     ODM_CMNINFO_LINK,
0338     ODM_CMNINFO_STATION_STATE,
0339     ODM_CMNINFO_RSSI_MIN,
0340     ODM_CMNINFO_DBG_COMP,           /*  u64 */
0341     ODM_CMNINFO_DBG_LEVEL,          /*  u32 */
0342     ODM_CMNINFO_RA_THRESHOLD_HIGH,      /*  u8 */
0343     ODM_CMNINFO_RA_THRESHOLD_LOW,       /*  u8 */
0344     ODM_CMNINFO_RF_ANTENNA_TYPE,        /*  u8 */
0345     ODM_CMNINFO_BT_ENABLED,
0346     ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
0347     ODM_CMNINFO_BT_HS_RSSI,
0348     ODM_CMNINFO_BT_OPERATION,
0349     ODM_CMNINFO_BT_LIMITED_DIG,     /* Need to Limited Dig or not */
0350     ODM_CMNINFO_BT_DISABLE_EDCA,
0351 /* CALL BY VALUE------------- */
0352 
0353     /*  Dynamic ptr array hook itms. */
0354     ODM_CMNINFO_STA_STATUS,
0355     ODM_CMNINFO_PHY_STATUS,
0356     ODM_CMNINFO_MAC_STATUS,
0357 
0358     ODM_CMNINFO_MAX,
0359 };
0360 
0361 /*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
0362 enum { /* _ODM_Support_Ability_Definition */
0363     /*  */
0364     /*  BB ODM section BIT 0-15 */
0365     /*  */
0366     ODM_BB_DIG          = BIT0,
0367     ODM_BB_RA_MASK          = BIT1,
0368     ODM_BB_DYNAMIC_TXPWR        = BIT2,
0369     ODM_BB_FA_CNT           = BIT3,
0370     ODM_BB_RSSI_MONITOR     = BIT4,
0371     ODM_BB_CCK_PD           = BIT5,
0372     ODM_BB_ANT_DIV          = BIT6,
0373     ODM_BB_PWR_SAVE         = BIT7,
0374     ODM_BB_PWR_TRAIN        = BIT8,
0375     ODM_BB_RATE_ADAPTIVE        = BIT9,
0376     ODM_BB_PATH_DIV         = BIT10,
0377     ODM_BB_PSD          = BIT11,
0378     ODM_BB_RXHP         = BIT12,
0379     ODM_BB_ADAPTIVITY       = BIT13,
0380     ODM_BB_CFO_TRACKING     = BIT14,
0381 
0382     /*  MAC DM section BIT 16-23 */
0383     ODM_MAC_EDCA_TURBO      = BIT16,
0384     ODM_MAC_EARLY_MODE      = BIT17,
0385 
0386     /*  RF ODM section BIT 24-31 */
0387     ODM_RF_TX_PWR_TRACK     = BIT24,
0388     ODM_RF_RX_GAIN_TRACK    = BIT25,
0389     ODM_RF_CALIBRATION      = BIT26,
0390 };
0391 
0392 /*  ODM_CMNINFO_INTERFACE */
0393 enum { /* tag_ODM_Support_Interface_Definition */
0394     ODM_ITRF_SDIO   =   0x4,
0395     ODM_ITRF_ALL    =   0x7,
0396 };
0397 
0398 /*  ODM_CMNINFO_IC_TYPE */
0399 enum { /* tag_ODM_Support_IC_Type_Definition */
0400     ODM_RTL8723B    =   BIT8,
0401 };
0402 
0403 /* ODM_CMNINFO_CUT_VER */
0404 enum { /* tag_ODM_Cut_Version_Definition */
0405     ODM_CUT_A       =   0,
0406     ODM_CUT_B       =   1,
0407     ODM_CUT_C       =   2,
0408     ODM_CUT_D       =   3,
0409     ODM_CUT_E       =   4,
0410     ODM_CUT_F       =   5,
0411 
0412     ODM_CUT_I       =   8,
0413     ODM_CUT_J       =   9,
0414     ODM_CUT_K       =   10,
0415     ODM_CUT_TEST    =   15,
0416 };
0417 
0418 /*  ODM_CMNINFO_FAB_VER */
0419 enum { /* tag_ODM_Fab_Version_Definition */
0420     ODM_TSMC    =   0,
0421     ODM_UMC     =   1,
0422 };
0423 
0424 /*  */
0425 /*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
0426 /*  */
0427 enum { /* tag_ODM_RF_Type_Definition */
0428     ODM_1T1R    =   0,
0429     ODM_1T2R    =   1,
0430     ODM_2T2R    =   2,
0431     ODM_2T3R    =   3,
0432     ODM_2T4R    =   4,
0433     ODM_3T3R    =   5,
0434     ODM_3T4R    =   6,
0435     ODM_4T4R    =   7,
0436 };
0437 
0438 /*  */
0439 /*  ODM Dynamic common info value definition */
0440 /*  */
0441 
0442 /*  ODM_CMNINFO_WM_MODE */
0443 enum { /* tag_Wireless_Mode_Definition */
0444     ODM_WM_UNKNOWN    = 0x0,
0445     ODM_WM_B          = BIT0,
0446     ODM_WM_G          = BIT1,
0447     ODM_WM_N24G       = BIT3,
0448     ODM_WM_AUTO       = BIT5,
0449 };
0450 
0451 /*  ODM_CMNINFO_BW */
0452 enum { /* tag_Bandwidth_Definition */
0453     ODM_BW20M       = 0,
0454     ODM_BW40M       = 1,
0455 };
0456 
0457 /*  For AC-series IC, external PA & LNA can be individually added on 2.4G */
0458 
0459 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */
0460     TYPE_GPA0 = 0,
0461     TYPE_GPA1 = BIT(1)|BIT(0)
0462 };
0463 
0464 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */
0465     TYPE_APA0 = 0,
0466     TYPE_APA1 = BIT(1)|BIT(0)
0467 };
0468 
0469 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */
0470     TYPE_GLNA0 = 0,
0471     TYPE_GLNA1 = BIT(2)|BIT(0),
0472     TYPE_GLNA2 = BIT(3)|BIT(1),
0473     TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
0474 };
0475 
0476 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */
0477     TYPE_ALNA0 = 0,
0478     TYPE_ALNA1 = BIT(2)|BIT(0),
0479     TYPE_ALNA2 = BIT(3)|BIT(1),
0480     TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
0481 };
0482 
0483 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */
0484     bool bIQKDone;
0485     s32 Value[3][IQK_Matrix_REG_NUM];
0486     bool bBWIqkResultSaved[3];
0487 };
0488 
0489 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */
0490 
0491 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */
0492     /* for tx power tracking */
0493 
0494     u32 RegA24; /*  for TempCCK */
0495     s32 RegE94;
0496     s32 RegE9C;
0497     s32 RegEB4;
0498     s32 RegEBC;
0499 
0500     u8 TXPowercount;
0501     bool bTXPowerTrackingInit;
0502     bool bTXPowerTracking;
0503     u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
0504     u8 TM_Trigger;
0505 
0506     u8 ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
0507     u8 ThermalValue;
0508     u8 ThermalValue_LCK;
0509     u8 ThermalValue_IQK;
0510     u8 ThermalValue_DPK;
0511     u8 ThermalValue_AVG[AVG_THERMAL_NUM];
0512     u8 ThermalValue_AVG_index;
0513     u8 ThermalValue_RxGain;
0514     u8 ThermalValue_Crystal;
0515     u8 ThermalValue_DPKstore;
0516     u8 ThermalValue_DPKtrack;
0517     bool TxPowerTrackingInProgress;
0518 
0519     bool bReloadtxpowerindex;
0520     u8 bRfPiEnable;
0521     u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
0522 
0523     /*  Tx power Tracking ------------------------- */
0524     u8 bCCKinCH14;
0525     u8 CCK_index;
0526     u8 OFDM_index[MAX_RF_PATH];
0527     s8 PowerIndexOffset[MAX_RF_PATH];
0528     s8 DeltaPowerIndex[MAX_RF_PATH];
0529     s8 DeltaPowerIndexLast[MAX_RF_PATH];
0530     bool bTxPowerChanged;
0531 
0532     u8 ThermalValue_HP[HP_THERMAL_NUM];
0533     u8 ThermalValue_HP_index;
0534     struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
0535     bool bNeedIQK;
0536     bool bIQKInProgress;
0537     u8 Delta_IQK;
0538     u8 Delta_LCK;
0539     s8 BBSwingDiff2G; /*  Unit: dB */
0540     u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
0541     u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
0542     u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
0543     u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
0544     u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
0545     u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
0546     u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
0547     u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
0548     u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
0549     u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
0550 
0551     /*  */
0552 
0553     /* for IQK */
0554     u32 RegC04;
0555     u32 Reg874;
0556     u32 RegC08;
0557     u32 RegB68;
0558     u32 RegB6C;
0559     u32 Reg870;
0560     u32 Reg860;
0561     u32 Reg864;
0562 
0563     bool bIQKInitialized;
0564     bool bLCKInProgress;
0565     bool bAntennaDetected;
0566     u32 ADDA_backup[IQK_ADDA_REG_NUM];
0567     u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
0568     u32 IQK_BB_backup_recover[9];
0569     u32 IQK_BB_backup[IQK_BB_REG_NUM];
0570     u32 TxIQC_8723B[2][3][2]; /*  { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
0571     u32 RxIQC_8723B[2][2][2]; /*  { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
0572 
0573     /* for APK */
0574     u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
0575     u8 bAPKdone;
0576     u8 bAPKThermalMeterIgnore;
0577 
0578     /*  DPK */
0579     bool bDPKFail;
0580     u8 bDPdone;
0581     u8 bDPPathAOK;
0582     u8 bDPPathBOK;
0583 
0584     u32 TxLOK[2];
0585 
0586 };
0587 /*  */
0588 /*  ODM Dynamic common info value definition */
0589 /*  */
0590 
0591 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */
0592     u8 Bssid[6];
0593     u8 antsel_rx_keep_0;
0594     u8 antsel_rx_keep_1;
0595     u8 antsel_rx_keep_2;
0596     u8 antsel_rx_keep_3;
0597     u32 antSumRSSI[7];
0598     u32 antRSSIcnt[7];
0599     u32 antAveRSSI[7];
0600     u8 FAT_State;
0601     u32 TrainIdx;
0602     u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
0603     u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
0604     u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
0605     u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
0606     u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
0607     u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
0608     u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
0609     u8 RxIdleAnt;
0610     bool    bBecomeLinked;
0611     u32 MinMaxRSSI;
0612     u8 idx_AntDiv_counter_2G;
0613     u32 CCK_counter_main;
0614     u32 CCK_counter_aux;
0615     u32 OFDM_counter_main;
0616     u32 OFDM_counter_aux;
0617 
0618     u32 CCK_CtrlFrame_Cnt_main;
0619     u32 CCK_CtrlFrame_Cnt_aux;
0620     u32 OFDM_CtrlFrame_Cnt_main;
0621     u32 OFDM_CtrlFrame_Cnt_aux;
0622     u32 MainAnt_CtrlFrame_Sum;
0623     u32 AuxAnt_CtrlFrame_Sum;
0624     u32 MainAnt_CtrlFrame_Cnt;
0625     u32 AuxAnt_CtrlFrame_Cnt;
0626 
0627 };
0628 
0629 enum {
0630     NO_ANTDIV           = 0xFF,
0631     CG_TRX_HW_ANTDIV        = 0x01,
0632     CGCS_RX_HW_ANTDIV   = 0x02,
0633     FIXED_HW_ANTDIV     = 0x03,
0634     CG_TRX_SMART_ANTDIV = 0x04,
0635     CGCS_RX_SW_ANTDIV   = 0x05,
0636     S0S1_SW_ANTDIV          = 0x06 /* 8723B intrnal switch S0 S1 */
0637 };
0638 
0639 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */
0640     u8 RespTxPath;
0641     u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
0642     u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
0643     u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
0644     u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
0645     u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
0646 };
0647 
0648 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */
0649     PHY_REG_PG_RELATIVE_VALUE = 0,
0650     PHY_REG_PG_EXACT_VALUE = 1
0651 };
0652 
0653 /*  */
0654 /*  Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
0655 /*  */
0656 struct ant_detected_info {
0657     bool bAntDetected;
0658     u32 dBForAntA;
0659     u32 dBForAntB;
0660     u32 dBForAntO;
0661 };
0662 
0663 /*  */
0664 /*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
0665 /*  */
0666 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */
0667     /* struct timer_list    FastAntTrainingTimer; */
0668     /*  */
0669     /*  Add for different team use temporarily */
0670     /*  */
0671     struct adapter *Adapter;        /*  For CE/NIC team */
0672     /*  WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
0673     bool odm_ready;
0674 
0675     enum phy_reg_pg_type PhyRegPgValueType;
0676     u8 PhyRegPgVersion;
0677 
0678     u32 NumQryPhyStatusAll; /* CCK + OFDM */
0679     u32 LastNumQryPhyStatusAll;
0680     u32 RxPWDBAve;
0681     bool MPDIG_2G;      /* off MPDIG */
0682     u8 Times_2G;
0683 
0684 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
0685     bool bCckHighPower;
0686     u8 RFPathRxEnable;      /*  ODM_CMNINFO_RFPATH_ENABLE */
0687     u8 ControlChannel;
0688 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
0689 
0690 /* REMOVED COMMON INFO---------- */
0691     /* u8       PseudoMacPhyMode; */
0692     /* bool         *BTCoexist; */
0693     /* bool         PseudoBtCoexist; */
0694     /* u8       OPMode; */
0695     /* bool         bAPMode; */
0696     /* bool         bClientMode; */
0697     /* bool         bAdHocMode; */
0698     /* bool         bSlaveOfDMSP; */
0699 /* REMOVED COMMON INFO---------- */
0700 
0701 /* 1  COMMON INFORMATION */
0702 
0703     /*  */
0704     /*  Init Value */
0705     /*  */
0706 /* HOOK BEFORE REG INIT----------- */
0707     /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
0708     u8 SupportPlatform;
0709     /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */
0710     u32 SupportAbility;
0711     /*  ODM PCIE/USB/SDIO = 1/2/3 */
0712     u8 SupportInterface;
0713     /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
0714     u32 SupportICType;
0715     /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
0716     u8 CutVersion;
0717     /*  Fab Version TSMC/UMC = 0/1 */
0718     u8 FabVersion;
0719     /*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
0720     u8 RFEType;
0721     /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
0722     u8 BoardType;
0723     u8 PackageType;
0724     u8 TypeGLNA;
0725     u8 TypeGPA;
0726     u8 TypeALNA;
0727     u8 TypeAPA;
0728     /*  with external LNA  NO/Yes = 0/1 */
0729     u8 ExtLNA;
0730     /*  with external PA  NO/Yes = 0/1 */
0731     u8 ExtPA;
0732     /*  with external TRSW  NO/Yes = 0/1 */
0733     u8 ExtTRSW;
0734     u8 PatchID; /* Customer ID */
0735     bool bInHctTest;
0736     bool bWIFITest;
0737 
0738     bool bDualMacSmartConcurrent;
0739     u32 BK_SupportAbility;
0740     u8 AntDivType;
0741 /* HOOK BEFORE REG INIT----------- */
0742 
0743     /*  */
0744     /*  Dynamic Value */
0745     /*  */
0746 /*  POINTER REFERENCE----------- */
0747 
0748     u8 u8_temp;
0749     bool bool_temp;
0750     struct adapter *adapter_temp;
0751 
0752     /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
0753     u8 *pMacPhyMode;
0754     /* TX Unicast byte count */
0755     u64 *pNumTxBytesUnicast;
0756     /* RX Unicast byte count */
0757     u64 *pNumRxBytesUnicast;
0758     /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
0759     u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
0760     /*  Secondary channel offset don't_care/below/above = 0/1/2 */
0761     u8 *pSecChOffset;
0762     /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
0763     u8 *pSecurity;
0764     /*  BW info 20M/40M/80M = 0/1/2 */
0765     u8 *pBandWidth;
0766     /*  Central channel location Ch1/Ch2/.... */
0767     u8 *pChannel; /* central channel number */
0768     bool DPK_Done;
0769     /*  Common info for 92D DMSP */
0770 
0771     bool *pbGetValueFromOtherMac;
0772     struct adapter **pBuddyAdapter;
0773     bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
0774     /*  Common info for Status */
0775     bool *pbScanInProcess;
0776     bool *pbPowerSaving;
0777     /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
0778     u8 *pOnePathCCA;
0779     /* pMgntInfo->AntennaTest */
0780     u8 *pAntennaTest;
0781     bool *pbNet_closed;
0782     u8 *mp_mode;
0783     /* u8   *pAidMap; */
0784     u8 *pu1ForcedIgiLb;
0785 /*  For 8723B IQK----------- */
0786     bool *pIs1Antenna;
0787     u8 *pRFDefaultPath;
0788     /*  0:S1, 1:S0 */
0789 
0790 /*  POINTER REFERENCE----------- */
0791     u16 *pForcedDataRate;
0792 /* CALL BY VALUE------------- */
0793     bool bLinkInProcess;
0794     bool bWIFI_Direct;
0795     bool bWIFI_Display;
0796     bool bLinked;
0797 
0798     bool bsta_state;
0799     u8 RSSI_Min;
0800     u8 InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
0801     bool bOneEntryOnly;
0802     /*  Common info for BTDM */
0803     bool bBtEnabled;            /*  BT is disabled */
0804     bool bBtConnectProcess; /*  BT HS is under connection progress. */
0805     u8 btHsRssi;                /*  BT HS mode wifi rssi value. */
0806     bool bBtHsOperation;        /*  BT HS mode is under progress */
0807     bool bBtDisableEdcaTurbo;   /*  Under some condition, don't enable the EDCA Turbo */
0808     bool bBtLimitedDig;         /*  BT is busy. */
0809 /* CALL BY VALUE------------- */
0810     u8 RSSI_A;
0811     u8 RSSI_B;
0812     u64 RSSI_TRSW;
0813     u64 RSSI_TRSW_H;
0814     u64 RSSI_TRSW_L;
0815     u64 RSSI_TRSW_iso;
0816 
0817     u8 RxRate;
0818     bool bNoisyState;
0819     u8 TxRate;
0820     u8 LinkedInterval;
0821     u8 preChannel;
0822     u32 TxagcOffsetValueA;
0823     bool IsTxagcOffsetPositiveA;
0824     u32 TxagcOffsetValueB;
0825     bool IsTxagcOffsetPositiveB;
0826     u64 lastTxOkCnt;
0827     u64 lastRxOkCnt;
0828     u32 BbSwingOffsetA;
0829     bool IsBbSwingOffsetPositiveA;
0830     u32 BbSwingOffsetB;
0831     bool IsBbSwingOffsetPositiveB;
0832     s8 TH_L2H_ini;
0833     s8 TH_EDCCA_HL_diff;
0834     s8 IGI_Base;
0835     u8 IGI_target;
0836     bool ForceEDCCA;
0837     u8 AdapEn_RSSI;
0838     s8 Force_TH_H;
0839     s8 Force_TH_L;
0840     u8 IGI_LowerBound;
0841     u8 antdiv_rssi;
0842     u8 AntType;
0843     u8 pre_AntType;
0844     u8 antdiv_period;
0845     u8 antdiv_select;
0846     u8 NdpaPeriod;
0847     bool H2C_RARpt_connect;
0848 
0849     /*  add by Yu Cehn for adaptivtiy */
0850     bool adaptivity_flag;
0851     bool NHM_disable;
0852     bool TxHangFlg;
0853     bool Carrier_Sense_enable;
0854     u8 tolerance_cnt;
0855     u64 NHMCurTxOkcnt;
0856     u64 NHMCurRxOkcnt;
0857     u64 NHMLastTxOkcnt;
0858     u64 NHMLastRxOkcnt;
0859     u8 txEdcca1;
0860     u8 txEdcca0;
0861     s8 H2L_lb;
0862     s8 L2H_lb;
0863     u8 Adaptivity_IGI_upper;
0864     u8 NHM_cnt_0;
0865 
0866     struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */
0867     /*  */
0868     /* 2 Define STA info. */
0869     /*  _ODM_STA_INFO */
0870     /*  2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
0871     PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
0872 
0873     /*  */
0874     /*  2012/02/14 MH Add to share 88E ra with other SW team. */
0875     /*  We need to colelct all support abilit to a proper area. */
0876     /*  */
0877     bool RaSupport88E;
0878 
0879     /*  Define ........... */
0880 
0881     /*  Latest packet phy info (ODM write) */
0882     struct odm_phy_dbg_info PhyDbgInfo;
0883     /* PHY_INFO_88E     PhyInfo; */
0884 
0885     /*  Latest packet phy info (ODM write) */
0886     struct odm_mac_status_info *pMacInfo;
0887     /* MAC_INFO_88E     MacInfo; */
0888 
0889     /*  Different Team independt structure?? */
0890 
0891     /*  */
0892     /* TX_RTP_CMN       TX_retrpo; */
0893     /* TX_RTP_88E       TX_retrpo; */
0894     /* TX_RTP_8195      TX_retrpo; */
0895 
0896     /*  */
0897     /* ODM Structure */
0898     /*  */
0899     struct fat_t DM_FatTable;
0900     struct dig_t DM_DigTable;
0901     struct ps_t DM_PSTable;
0902     struct dynamic_primary_CCA DM_PriCCA;
0903     struct rxhp_t dM_RXHP_Table;
0904     struct ra_t DM_RA_Table;
0905     struct false_ALARM_STATISTICS FalseAlmCnt;
0906     struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
0907     struct swat_t DM_SWAT_Table;
0908     bool RSSI_test;
0909     struct cfo_tracking DM_CfoTrack;
0910 
0911     struct edca_t DM_EDCA_Table;
0912     u32 WMMEDCA_BE;
0913     struct pathdiv_t DM_PathDiv;
0914     /*  Copy from SD4 structure */
0915     /*  */
0916     /*  ================================================== */
0917     /*  */
0918 
0919     /* common */
0920     /* u8 DM_Type; */
0921     /* u8    PSD_Report_RXHP[80];    Add By Gary */
0922     /* u8    PSD_func_flag;                Add By Gary */
0923     /* for DIG */
0924     /* u8 bDMInitialGainEnable; */
0925     /* u8 binitialized;  for dm_initial_gain_Multi_STA use. */
0926     /* for Antenna diversity */
0927     /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
0928     /* PSTA_INFO_T RSSI_target; */
0929 
0930     bool *pbDriverStopped;
0931     bool *pbDriverIsGoingToPnpSetPowerSleep;
0932     bool *pinit_adpt_in_progress;
0933 
0934     /* PSD */
0935     bool bUserAssignLevel;
0936     struct timer_list PSDTimer;
0937     u8 RSSI_BT;         /* come from BT */
0938     bool bPSDinProcess;
0939     bool bPSDactive;
0940     bool bDMInitialGainEnable;
0941 
0942     /* MPT DIG */
0943     struct timer_list MPT_DIGTimer;
0944 
0945     /* for rate adaptive, in fact,  88c/92c fw will handle this */
0946     u8 bUseRAMask;
0947 
0948     struct odm_rate_adaptive RateAdaptive;
0949 
0950     struct ant_detected_info AntDetectedInfo; /*  Antenna detected information for RSSI tool */
0951 
0952     struct odm_rf_cal_t RFCalibrateInfo;
0953 
0954     /*  */
0955     /*  TX power tracking */
0956     /*  */
0957     u8 BbSwingIdxOfdm[MAX_RF_PATH];
0958     u8 BbSwingIdxOfdmCurrent;
0959     u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
0960     bool BbSwingFlagOfdm;
0961     u8 BbSwingIdxCck;
0962     u8 BbSwingIdxCckCurrent;
0963     u8 BbSwingIdxCckBase;
0964     u8 DefaultOfdmIndex;
0965     u8 DefaultCckIndex;
0966     bool BbSwingFlagCck;
0967 
0968     s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
0969     s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
0970     s8 Remnant_CCKSwingIdx;
0971     s8 Modify_TxAGC_Value;       /* Remnat compensate value at TxAGC */
0972     bool Modify_TxAGC_Flag_PathA;
0973     bool Modify_TxAGC_Flag_PathB;
0974     bool Modify_TxAGC_Flag_PathC;
0975     bool Modify_TxAGC_Flag_PathD;
0976     bool Modify_TxAGC_Flag_PathA_CCK;
0977 
0978     s8 KfreeOffset[MAX_RF_PATH];
0979     /*  */
0980     /*  ODM system resource. */
0981     /*  */
0982 
0983     /*  ODM relative time. */
0984     struct timer_list PathDivSwitchTimer;
0985     /* 2011.09.27 add for Path Diversity */
0986     struct timer_list CCKPathDiversityTimer;
0987     struct timer_list FastAntTrainingTimer;
0988 
0989     /*  ODM relative workitem. */
0990 
0991     #if (BEAMFORMING_SUPPORT == 1)
0992     RT_BEAMFORMING_INFO BeamformingInfo;
0993     #endif
0994 };
0995 
0996  enum odm_rf_content {
0997     odm_radioa_txt = 0x1000,
0998     odm_radiob_txt = 0x1001,
0999     odm_radioc_txt = 0x1002,
1000     odm_radiod_txt = 0x1003
1001 };
1002 
1003 enum ODM_BB_Config_Type {
1004     CONFIG_BB_PHY_REG,
1005     CONFIG_BB_AGC_TAB,
1006     CONFIG_BB_AGC_TAB_2G,
1007     CONFIG_BB_PHY_REG_PG,
1008     CONFIG_BB_PHY_REG_MP,
1009     CONFIG_BB_AGC_TAB_DIFF,
1010 };
1011 
1012 enum ODM_RF_Config_Type {
1013     CONFIG_RF_RADIO,
1014     CONFIG_RF_TXPWR_LMT,
1015 };
1016 
1017 enum ODM_FW_Config_Type {
1018     CONFIG_FW_NIC,
1019     CONFIG_FW_NIC_2,
1020     CONFIG_FW_AP,
1021     CONFIG_FW_WoWLAN,
1022     CONFIG_FW_WoWLAN_2,
1023     CONFIG_FW_AP_WoWLAN,
1024     CONFIG_FW_BT,
1025 };
1026 
1027 #ifdef REMOVE_PACK
1028 #pragma pack()
1029 #endif
1030 
1031 /* include "odm_function.h" */
1032 
1033 /* 3 =========================================================== */
1034 /* 3 DIG */
1035 /* 3 =========================================================== */
1036 
1037 /* Remove DIG by Yuchen */
1038 
1039 /* 3 =========================================================== */
1040 /* 3 AGC RX High Power Mode */
1041 /* 3 =========================================================== */
1042 #define          LNA_Low_Gain_1                      0x64
1043 #define          LNA_Low_Gain_2                      0x5A
1044 #define          LNA_Low_Gain_3                      0x58
1045 
1046 #define          FA_RXHP_TH1                           5000
1047 #define          FA_RXHP_TH2                           1500
1048 #define          FA_RXHP_TH3                             800
1049 #define          FA_RXHP_TH4                             600
1050 #define          FA_RXHP_TH5                             500
1051 
1052 /* 3 =========================================================== */
1053 /* 3 EDCA */
1054 /* 3 =========================================================== */
1055 
1056 /* 3 =========================================================== */
1057 /* 3 Dynamic Tx Power */
1058 /* 3 =========================================================== */
1059 /* Dynamic Tx Power Control Threshold */
1060 
1061 /* 3 =========================================================== */
1062 /* 3 Rate Adaptive */
1063 /* 3 =========================================================== */
1064 #define     DM_RATR_STA_INIT            0
1065 #define     DM_RATR_STA_HIGH            1
1066 #define     DM_RATR_STA_MIDDLE          2
1067 #define     DM_RATR_STA_LOW             3
1068 
1069 /* 3 =========================================================== */
1070 /* 3 BB Power Save */
1071 /* 3 =========================================================== */
1072 
1073 enum { /* tag_1R_CCA_Type_Definition */
1074     CCA_1R = 0,
1075     CCA_2R = 1,
1076     CCA_MAX = 2,
1077 };
1078 
1079 enum { /* tag_RF_Type_Definition */
1080     RF_Save = 0,
1081     RF_Normal = 1,
1082     RF_MAX = 2,
1083 };
1084 
1085 /*  Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1086 #define MAX_ANTENNA_DETECTION_CNT   10
1087 
1088 /*  */
1089 /*  Extern Global Variables. */
1090 /*  */
1091 extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1092 extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1093 extern  u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1094 
1095 extern  u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1096 extern  u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1097 extern  u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1098 
1099 extern  u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1100 
1101 /*  */
1102 /*  check Sta pointer valid or not */
1103 /*  */
1104 #define IS_STA_VALID(pSta)      (pSta)
1105 /*  20100514 Joseph: Add definition for antenna switching test after link. */
1106 /*  This indicates two different the steps. */
1107 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1108 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1109 /*  with original RSSI to determine if it is necessary to switch antenna. */
1110 #define SWAW_STEP_PEAK      0
1111 #define SWAW_STEP_DETERMINE 1
1112 
1113 /* Remove BB power saving by Yuchen */
1114 
1115 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1116 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm);
1117 
1118 bool ODM_RAStateCheck(
1119     struct dm_odm_t *pDM_Odm,
1120     s32 RSSI,
1121     bool bForceUpdate,
1122     u8 *pRATRState
1123 );
1124 
1125 #define dm_SWAW_RSSI_Check  ODM_SwAntDivChkPerPktRssi
1126 void ODM_SwAntDivChkPerPktRssi(
1127     struct dm_odm_t *pDM_Odm,
1128     u8 StationID,
1129     struct odm_phy_info *pPhyInfo
1130 );
1131 
1132 u32 ODM_Get_Rate_Bitmap(
1133     struct dm_odm_t *pDM_Odm,
1134     u32 macid,
1135     u32 ra_mask,
1136     u8 rssi_level
1137 );
1138 
1139 #if (BEAMFORMING_SUPPORT == 1)
1140 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1141 #endif
1142 
1143 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm);
1144 
1145 void ODM_DMInit(struct dm_odm_t *pDM_Odm);
1146 
1147 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /*  For common use in the future */
1148 
1149 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value);
1150 
1151 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue);
1152 
1153 void ODM_CmnInfoPtrArrayHook(
1154     struct dm_odm_t *pDM_Odm,
1155     enum odm_cmninfo_e CmnInfo,
1156     u16 Index,
1157     void *pValue
1158 );
1159 
1160 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value);
1161 
1162 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm);
1163 
1164 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm);
1165 
1166 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm);
1167 
1168 void ODM_AntselStatistics_88C(
1169     struct dm_odm_t *pDM_Odm,
1170     u8 MacId,
1171     u32 PWDBAll,
1172     bool isCCKrate
1173 );
1174 
1175 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State);
1176 
1177 #endif
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