rtl8723bs/hal/HalPwrSeqCmd.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /******************************************************************************
0003  *
0004  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
0005  *
0006  ******************************************************************************/
0007 /*++
0008 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
0009
0010 Module Name:
0011     HalPwrSeqCmd.c
0012
0013 Abstract:
0014     Implement HW Power sequence configuration CMD handling routine for Realtek devices.
0015
0016 Major Change History:
0017     When       Who               What
0018     ---------- ---------------   -------------------------------
0019     2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
0020     2011-07-07 Roger            Create.
0021
0022 --*/
0023 #include <drv_types.h>
0024 #include <rtw_debug.h>
0025 #include <HalPwrSeqCmd.h>
0026
0027
0028 /*  */
0029 /*  Description: */
0030 /*  This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
0031 /*  */
0032 /*  Assumption: */
0033 /*  We should follow specific format which was released from HW SD. */
0034 /*  */
0035 /*  2011.07.07, added by Roger. */
0036 /*  */
0037 u8 HalPwrSeqCmdParsing(
0038     struct adapter *padapter,
0039     u8 CutVersion,
0040     u8 FabVersion,
0041     u8 InterfaceType,
0042     struct wlan_pwr_cfg PwrSeqCmd[]
0043 )
0044 {
0045     struct wlan_pwr_cfg PwrCfgCmd;
0046     u8 bPollingBit = false;
0047     u32 AryIdx = 0;
0048     u8 value = 0;
0049     u32 offset = 0;
0050     u32 pollingCount = 0; /*  polling autoload done. */
0051     u32 maxPollingCnt = 5000;
0052
0053     do {
0054         PwrCfgCmd = PwrSeqCmd[AryIdx];
0055
0056         /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
0057         if (
0058             (GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
0059             (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
0060             (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)
0061         ) {
0062             switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
0063             case PWR_CMD_READ:
0064                 break;
0065
0066             case PWR_CMD_WRITE:
0067                 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
0068
0069                 /*  */
0070                 /*  <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
0071                 /*  2011.07.07. */
0072                 /*  */
0073                 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
0074                     /*  Read Back SDIO Local value */
0075                     value = SdioLocalCmd52Read1Byte(padapter, offset);
0076
0077                     value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
0078                     value |= (
0079                         GET_PWR_CFG_VALUE(PwrCfgCmd) &
0080                         GET_PWR_CFG_MASK(PwrCfgCmd)
0081                     );
0082
0083                     /*  Write Back SDIO Local value */
0084                     SdioLocalCmd52Write1Byte(padapter, offset, value);
0085                 } else {
0086                     /*  Read the value from system register */
0087                     value = rtw_read8(padapter, offset);
0088
0089                     value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
0090                     value |= (
0091                         GET_PWR_CFG_VALUE(PwrCfgCmd)
0092                         &GET_PWR_CFG_MASK(PwrCfgCmd)
0093                     );
0094
0095                     /*  Write the value back to system register */
0096                     rtw_write8(padapter, offset, value);
0097                 }
0098                 break;
0099
0100             case PWR_CMD_POLLING:
0101
0102                 bPollingBit = false;
0103                 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
0104                 do {
0105                     if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
0106                         value = SdioLocalCmd52Read1Byte(padapter, offset);
0107                     else
0108                         value = rtw_read8(padapter, offset);
0109
0110                     value = value&GET_PWR_CFG_MASK(PwrCfgCmd);
0111                     if (
0112                         value == (GET_PWR_CFG_VALUE(PwrCfgCmd) &
0113                         GET_PWR_CFG_MASK(PwrCfgCmd))
0114                     )
0115                         bPollingBit = true;
0116                     else
0117                         udelay(10);
0118
0119                     if (pollingCount++ > maxPollingCnt)
0120                         return false;
0121
0122                 } while (!bPollingBit);
0123
0124                 break;
0125
0126             case PWR_CMD_DELAY:
0127                 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
0128                     udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
0129                 else
0130                     udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
0131                 break;
0132
0133             case PWR_CMD_END:
0134                 /*  When this command is parsed, end the process */
0135                 return true;
0136
0137             default:
0138                 break;
0139             }
0140         }
0141
0142         AryIdx++;/* Add Array Index */
0143     } while (1);
0144
0145     return true;
0146 }