staging/rtl8712/usb_halinit.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /******************************************************************************
0003  * usb_halinit.c
0004  *
0005  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
0006  * Linux device driver for RTL8192SU
0007  *
0008  * Modifications for inclusion into the Linux staging tree are
0009  * Copyright(c) 2010 Larry Finger. All rights reserved.
0010  *
0011  * Contact information:
0012  * WLAN FAE <wlanfae@realtek.com>
0013  * Larry Finger <Larry.Finger@lwfinger.net>
0014  *
0015  ******************************************************************************/
0016
0017 #define _HCI_HAL_INIT_C_
0018
0019 #include "osdep_service.h"
0020 #include "drv_types.h"
0021 #include "usb_ops.h"
0022 #include "usb_osintf.h"
0023
0024 u8 r8712_usb_hal_bus_init(struct _adapter *adapter)
0025 {
0026     u8 val8 = 0;
0027     u8 ret = _SUCCESS;
0028     int PollingCnt = 20;
0029     struct registry_priv *registrypriv = &adapter->registrypriv;
0030
0031     if (registrypriv->chip_version == RTL8712_FPGA) {
0032         val8 = 0x01;
0033         /* switch to 80M clock */
0034         r8712_write8(adapter, SYS_CLKR, val8);
0035         val8 = r8712_read8(adapter, SPS1_CTRL);
0036         val8 = val8 | 0x01;
0037         /* enable VSPS12 LDO Macro block */
0038         r8712_write8(adapter, SPS1_CTRL, val8);
0039         val8 = r8712_read8(adapter, AFE_MISC);
0040         val8 = val8 | 0x01;
0041         /* Enable AFE Macro Block's Bandgap */
0042         r8712_write8(adapter, AFE_MISC, val8);
0043         val8 = r8712_read8(adapter, LDOA15_CTRL);
0044         val8 = val8 | 0x01;
0045         /* enable LDOA15 block */
0046         r8712_write8(adapter, LDOA15_CTRL, val8);
0047         val8 = r8712_read8(adapter, SPS1_CTRL);
0048         val8 = val8 | 0x02;
0049         /* Enable VSPS12_SW Macro Block */
0050         r8712_write8(adapter, SPS1_CTRL, val8);
0051         val8 = r8712_read8(adapter, AFE_MISC);
0052         val8 = val8 | 0x02;
0053         /* Enable AFE Macro Block's Mbias */
0054         r8712_write8(adapter, AFE_MISC, val8);
0055         val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1);
0056         val8 = val8 | 0x08;
0057         /* isolate PCIe Analog 1.2V to PCIe 3.3V and PCIE Digital */
0058         r8712_write8(adapter, SYS_ISO_CTRL + 1, val8);
0059         val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1);
0060         val8 = val8 & 0xEF;
0061         /* attach AFE PLL to MACTOP/BB/PCIe Digital */
0062         r8712_write8(adapter, SYS_ISO_CTRL + 1, val8);
0063         val8 = r8712_read8(adapter, AFE_XTAL_CTRL + 1);
0064         val8 = val8 & 0xFB;
0065         /* enable AFE clock */
0066         r8712_write8(adapter, AFE_XTAL_CTRL + 1, val8);
0067         val8 = r8712_read8(adapter, AFE_PLL_CTRL);
0068         val8 = val8 | 0x01;
0069         /* Enable AFE PLL Macro Block */
0070         r8712_write8(adapter, AFE_PLL_CTRL, val8);
0071         val8 = 0xEE;
0072         /* release isolation AFE PLL & MD */
0073         r8712_write8(adapter, SYS_ISO_CTRL, val8);
0074         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0075         val8 = val8 | 0x08;
0076         /* enable MAC clock */
0077         r8712_write8(adapter, SYS_CLKR + 1, val8);
0078         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0079         val8 = val8 | 0x08;
0080         /* enable Core digital and enable IOREG R/W */
0081         r8712_write8(adapter, SYS_FUNC_EN + 1, val8);
0082         val8 = val8 | 0x80;
0083         /* enable REG_EN */
0084         r8712_write8(adapter, SYS_FUNC_EN + 1, val8);
0085         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0086         val8 = (val8 | 0x80) & 0xBF;
0087         /* switch the control path */
0088         r8712_write8(adapter, SYS_CLKR + 1, val8);
0089         val8 = 0xFC;
0090         r8712_write8(adapter, CR, val8);
0091         val8 = 0x37;
0092         r8712_write8(adapter, CR + 1, val8);
0093         /* reduce EndPoint & init it */
0094         r8712_write8(adapter, 0x102500ab, r8712_read8(adapter,
0095                  0x102500ab) | BIT(6) | BIT(7));
0096         /* consideration of power consumption - init */
0097         r8712_write8(adapter, 0x10250008, r8712_read8(adapter,
0098                  0x10250008) & 0xfffffffb);
0099     } else if (registrypriv->chip_version == RTL8712_1stCUT) {
0100         /* Initialization for power on sequence, */
0101         r8712_write8(adapter, SPS0_CTRL + 1, 0x53);
0102         r8712_write8(adapter, SPS0_CTRL, 0x57);
0103         /* Enable AFE Macro Block's Bandgap and Enable AFE Macro
0104          * Block's Mbias
0105          */
0106         val8 = r8712_read8(adapter, AFE_MISC);
0107         r8712_write8(adapter, AFE_MISC, (val8 | AFE_MISC_BGEN |
0108                  AFE_MISC_MBEN));
0109         /* Enable LDOA15 block */
0110         val8 = r8712_read8(adapter, LDOA15_CTRL);
0111         r8712_write8(adapter, LDOA15_CTRL, (val8 | LDA15_EN));
0112         val8 = r8712_read8(adapter, SPS1_CTRL);
0113         r8712_write8(adapter, SPS1_CTRL, (val8 | SPS1_LDEN));
0114         msleep(20);
0115         /* Enable Switch Regulator Block */
0116         val8 = r8712_read8(adapter, SPS1_CTRL);
0117         r8712_write8(adapter, SPS1_CTRL, (val8 | SPS1_SWEN));
0118         r8712_write32(adapter, SPS1_CTRL, 0x00a7b267);
0119         val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1);
0120         r8712_write8(adapter, SYS_ISO_CTRL + 1, (val8 | 0x08));
0121         /* Engineer Packet CP test Enable */
0122         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0123         r8712_write8(adapter, SYS_FUNC_EN + 1, (val8 | 0x20));
0124         val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1);
0125         r8712_write8(adapter, SYS_ISO_CTRL + 1, (val8 & 0x6F));
0126         /* Enable AFE clock */
0127         val8 = r8712_read8(adapter, AFE_XTAL_CTRL + 1);
0128         r8712_write8(adapter, AFE_XTAL_CTRL + 1, (val8 & 0xfb));
0129         /* Enable AFE PLL Macro Block */
0130         val8 = r8712_read8(adapter, AFE_PLL_CTRL);
0131         r8712_write8(adapter, AFE_PLL_CTRL, (val8 | 0x11));
0132         /* Attach AFE PLL to MACTOP/BB/PCIe Digital */
0133         val8 = r8712_read8(adapter, SYS_ISO_CTRL);
0134         r8712_write8(adapter, SYS_ISO_CTRL, (val8 & 0xEE));
0135         /* Switch to 40M clock */
0136         val8 = r8712_read8(adapter, SYS_CLKR);
0137         r8712_write8(adapter, SYS_CLKR, val8 & (~SYS_CLKSEL));
0138         /* SSC Disable */
0139         val8 = r8712_read8(adapter, SYS_CLKR);
0140         /* Enable MAC clock */
0141         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0142         r8712_write8(adapter, SYS_CLKR + 1, (val8 | 0x18));
0143         /* Revised POS, */
0144         r8712_write8(adapter, PMC_FSM, 0x02);
0145         /* Enable Core digital and enable IOREG R/W */
0146         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0147         r8712_write8(adapter, SYS_FUNC_EN + 1, (val8 | 0x08));
0148         /* Enable REG_EN */
0149         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0150         r8712_write8(adapter, SYS_FUNC_EN + 1, (val8 | 0x80));
0151         /* Switch the control path to FW */
0152         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0153         r8712_write8(adapter, SYS_CLKR + 1, (val8 | 0x80) & 0xBF);
0154         r8712_write8(adapter, CR, 0xFC);
0155         r8712_write8(adapter, CR + 1, 0x37);
0156         /* Fix the RX FIFO issue(usb error), */
0157         val8 = r8712_read8(adapter, 0x1025FE5c);
0158         r8712_write8(adapter, 0x1025FE5c, (val8 | BIT(7)));
0159         val8 = r8712_read8(adapter, 0x102500ab);
0160         r8712_write8(adapter, 0x102500ab, (val8 | BIT(6) | BIT(7)));
0161         /* For power save, used this in the bit file after 970621 */
0162         val8 = r8712_read8(adapter, SYS_CLKR);
0163         r8712_write8(adapter, SYS_CLKR, val8 & (~CPU_CLKSEL));
0164     } else if (registrypriv->chip_version == RTL8712_2ndCUT ||
0165            registrypriv->chip_version == RTL8712_3rdCUT) {
0166         /* Initialization for power on sequence,
0167          * E-Fuse leakage prevention sequence
0168          */
0169         r8712_write8(adapter, 0x37, 0xb0);
0170         msleep(20);
0171         r8712_write8(adapter, 0x37, 0x30);
0172         /* Set control path switch to HW control and reset Digital Core,
0173          * CPU Core and MAC I/O to solve FW download fail when system
0174          * from resume sate.
0175          */
0176         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0177         if (val8 & 0x80) {
0178             val8 &= 0x3f;
0179             r8712_write8(adapter, SYS_CLKR + 1, val8);
0180         }
0181         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0182         val8 &= 0x73;
0183         r8712_write8(adapter, SYS_FUNC_EN + 1, val8);
0184         msleep(20);
0185         /* Revised POS, */
0186         /* Enable AFE Macro Block's Bandgap and Enable AFE Macro
0187          * Block's Mbias
0188          */
0189         r8712_write8(adapter, SPS0_CTRL + 1, 0x53);
0190         r8712_write8(adapter, SPS0_CTRL, 0x57);
0191         val8 = r8712_read8(adapter, AFE_MISC);
0192         /*Bandgap*/
0193         r8712_write8(adapter, AFE_MISC, (val8 | AFE_MISC_BGEN));
0194         r8712_write8(adapter, AFE_MISC, (val8 | AFE_MISC_BGEN |
0195                  AFE_MISC_MBEN | AFE_MISC_I32_EN));
0196         /* Enable PLL Power (LDOA15V) */
0197         val8 = r8712_read8(adapter, LDOA15_CTRL);
0198         r8712_write8(adapter, LDOA15_CTRL, (val8 | LDA15_EN));
0199         /* Enable LDOV12D block */
0200         val8 = r8712_read8(adapter, LDOV12D_CTRL);
0201         r8712_write8(adapter, LDOV12D_CTRL, (val8 | LDV12_EN));
0202         val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1);
0203         r8712_write8(adapter, SYS_ISO_CTRL + 1, (val8 | 0x08));
0204         /* Engineer Packet CP test Enable */
0205         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0206         r8712_write8(adapter, SYS_FUNC_EN + 1, (val8 | 0x20));
0207         /* Support 64k IMEM */
0208         val8 = r8712_read8(adapter, SYS_ISO_CTRL + 1);
0209         r8712_write8(adapter, SYS_ISO_CTRL + 1, (val8 & 0x68));
0210         /* Enable AFE clock */
0211         val8 = r8712_read8(adapter, AFE_XTAL_CTRL + 1);
0212         r8712_write8(adapter, AFE_XTAL_CTRL + 1, (val8 & 0xfb));
0213         /* Enable AFE PLL Macro Block */
0214         val8 = r8712_read8(adapter, AFE_PLL_CTRL);
0215         r8712_write8(adapter, AFE_PLL_CTRL, (val8 | 0x11));
0216         /* Some sample will download fw failure. The clock will be
0217          * stable with 500 us delay after reset the PLL
0218          * TODO: When usleep is added to kernel, change next 3
0219          * udelay(500) to usleep(500)
0220          */
0221         udelay(500);
0222         r8712_write8(adapter, AFE_PLL_CTRL, (val8 | 0x51));
0223         udelay(500);
0224         r8712_write8(adapter, AFE_PLL_CTRL, (val8 | 0x11));
0225         udelay(500);
0226         /* Attach AFE PLL to MACTOP/BB/PCIe Digital */
0227         val8 = r8712_read8(adapter, SYS_ISO_CTRL);
0228         r8712_write8(adapter, SYS_ISO_CTRL, (val8 & 0xEE));
0229         /* Switch to 40M clock */
0230         r8712_write8(adapter, SYS_CLKR, 0x00);
0231         /* CPU Clock and 80M Clock SSC Disable to overcome FW download
0232          * fail timing issue.
0233          */
0234         val8 = r8712_read8(adapter, SYS_CLKR);
0235         r8712_write8(adapter, SYS_CLKR, (val8 | 0xa0));
0236         /* Enable MAC clock */
0237         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0238         r8712_write8(adapter, SYS_CLKR + 1, (val8 | 0x18));
0239         /* Revised POS, */
0240         r8712_write8(adapter, PMC_FSM, 0x02);
0241         /* Enable Core digital and enable IOREG R/W */
0242         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0243         r8712_write8(adapter, SYS_FUNC_EN + 1, (val8 | 0x08));
0244         /* Enable REG_EN */
0245         val8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
0246         r8712_write8(adapter, SYS_FUNC_EN + 1, (val8 | 0x80));
0247         /* Switch the control path to FW */
0248         val8 = r8712_read8(adapter, SYS_CLKR + 1);
0249         r8712_write8(adapter, SYS_CLKR + 1, (val8 | 0x80) & 0xBF);
0250         r8712_write8(adapter, CR, 0xFC);
0251         r8712_write8(adapter, CR + 1, 0x37);
0252         /* Fix the RX FIFO issue(usb error), 970410 */
0253         val8 = r8712_read8(adapter, 0x1025FE5c);
0254         r8712_write8(adapter, 0x1025FE5c, (val8 | BIT(7)));
0255         /* For power save, used this in the bit file after 970621 */
0256         val8 = r8712_read8(adapter, SYS_CLKR);
0257         r8712_write8(adapter, SYS_CLKR, val8 & (~CPU_CLKSEL));
0258         /* Revised for 8051 ROM code wrong operation. */
0259         r8712_write8(adapter, 0x1025fe1c, 0x80);
0260         /* To make sure that TxDMA can ready to download FW.
0261          * We should reset TxDMA if IMEM RPT was not ready.
0262          */
0263         do {
0264             val8 = r8712_read8(adapter, TCR);
0265             if ((val8 & _TXDMA_INIT_VALUE) == _TXDMA_INIT_VALUE)
0266                 break;
0267             udelay(5); /* PlatformStallExecution(5); */
0268         } while (PollingCnt--); /* Delay 1ms */
0269
0270         if (PollingCnt <= 0) {
0271             val8 = r8712_read8(adapter, CR);
0272             r8712_write8(adapter, CR, val8 & (~_TXDMA_EN));
0273             udelay(2); /* PlatformStallExecution(2); */
0274             /* Reset TxDMA */
0275             r8712_write8(adapter, CR, val8 | _TXDMA_EN);
0276         }
0277     } else {
0278         ret = _FAIL;
0279     }
0280     return ret;
0281 }
0282
0283 unsigned int r8712_usb_inirp_init(struct _adapter *adapter)
0284 {
0285     u8 i;
0286     struct recv_buf *recvbuf;
0287     struct intf_hdl *intfhdl = &adapter->pio_queue->intf;
0288     struct recv_priv *recvpriv = &(adapter->recvpriv);
0289
0290     recvpriv->ff_hwaddr = RTL8712_DMA_RX0FF; /* mapping rx fifo address */
0291     /* issue Rx irp to receive data */
0292     recvbuf = (struct recv_buf *)recvpriv->precv_buf;
0293     for (i = 0; i < NR_RECVBUFF; i++) {
0294         if (r8712_usb_read_port(intfhdl, recvpriv->ff_hwaddr, 0,
0295                     (unsigned char *)recvbuf) == false)
0296             return _FAIL;
0297         recvbuf++;
0298         recvpriv->free_recv_buf_queue_cnt--;
0299     }
0300     return _SUCCESS;
0301 }
0302
0303 unsigned int r8712_usb_inirp_deinit(struct _adapter *adapter)
0304 {
0305     r8712_usb_read_port_cancel(adapter);
0306     return _SUCCESS;
0307 }