staging/rtl8712/rtl871x_mp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /******************************************************************************
0003  *
0004  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
0005  *
0006  * Modifications for inclusion into the Linux staging tree are
0007  * Copyright(c) 2010 Larry Finger. All rights reserved.
0008  *
0009  * Contact information:
0010  * WLAN FAE <wlanfae@realtek.com>
0011  * Larry Finger <Larry.Finger@lwfinger.net>
0012  *
0013  ******************************************************************************/
0014 #define _RTL871X_MP_C_
0015
0016 #include "osdep_service.h"
0017 #include "drv_types.h"
0018 #include "rtl871x_mp_phy_regdef.h"
0019 #include "rtl8712_cmd.h"
0020
0021 static void _init_mp_priv_(struct mp_priv *pmp_priv)
0022 {
0023     pmp_priv->mode = _LOOPBOOK_MODE_;
0024     pmp_priv->curr_ch = 1;
0025     pmp_priv->curr_modem = MIXED_PHY;
0026     pmp_priv->curr_rateidx = 0;
0027     pmp_priv->curr_txpoweridx = 0x14;
0028     pmp_priv->antenna_tx = ANTENNA_A;
0029     pmp_priv->antenna_rx = ANTENNA_AB;
0030     pmp_priv->check_mp_pkt = 0;
0031     pmp_priv->tx_pktcount = 0;
0032     pmp_priv->rx_pktcount = 0;
0033     pmp_priv->rx_crcerrpktcount = 0;
0034 }
0035
0036 static int init_mp_priv(struct mp_priv *pmp_priv)
0037 {
0038     int i;
0039     struct mp_xmit_frame *pmp_xmitframe;
0040
0041     _init_mp_priv_(pmp_priv);
0042     _init_queue(&pmp_priv->free_mp_xmitqueue);
0043     pmp_priv->pallocated_mp_xmitframe_buf = NULL;
0044     pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
0045                 sizeof(struct mp_xmit_frame) + 4,
0046                 GFP_ATOMIC);
0047     if (!pmp_priv->pallocated_mp_xmitframe_buf)
0048         return -ENOMEM;
0049
0050     pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
0051              4 -
0052              ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
0053     pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
0054     for (i = 0; i < NR_MP_XMITFRAME; i++) {
0055         INIT_LIST_HEAD(&(pmp_xmitframe->list));
0056         list_add_tail(&(pmp_xmitframe->list),
0057                  &(pmp_priv->free_mp_xmitqueue.queue));
0058         pmp_xmitframe->pkt = NULL;
0059         pmp_xmitframe->frame_tag = MP_FRAMETAG;
0060         pmp_xmitframe->padapter = pmp_priv->papdater;
0061         pmp_xmitframe++;
0062     }
0063     pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
0064     return 0;
0065 }
0066
0067 static int free_mp_priv(struct mp_priv *pmp_priv)
0068 {
0069     kfree(pmp_priv->pallocated_mp_xmitframe_buf);
0070     return 0;
0071 }
0072
0073 void mp871xinit(struct _adapter *padapter)
0074 {
0075     struct mp_priv *pmppriv = &padapter->mppriv;
0076
0077     pmppriv->papdater = padapter;
0078     init_mp_priv(pmppriv);
0079 }
0080
0081 void mp871xdeinit(struct _adapter *padapter)
0082 {
0083     struct mp_priv *pmppriv = &padapter->mppriv;
0084
0085     free_mp_priv(pmppriv);
0086 }
0087
0088 /*
0089  * Special for bb and rf reg read/write
0090  */
0091 static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
0092 {
0093     u32 cmd32 = 0, val32 = 0;
0094     u8 iocmd_class  = iocmd.cmdclass;
0095     u16 iocmd_value = iocmd.value;
0096     u8 iocmd_idx    = iocmd.index;
0097
0098     cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
0099     if (r8712_fw_cmd(pAdapter, cmd32))
0100         r8712_fw_cmd_data(pAdapter, &val32, 1);
0101     else
0102         val32 = 0;
0103     return val32;
0104 }
0105
0106 static u8 fw_iocmd_write(struct _adapter *pAdapter,
0107              struct IOCMD_STRUCT iocmd, u32 value)
0108 {
0109     u32 cmd32 = 0;
0110     u8 iocmd_class  = iocmd.cmdclass;
0111     u32 iocmd_value = iocmd.value;
0112     u8 iocmd_idx    = iocmd.index;
0113
0114     r8712_fw_cmd_data(pAdapter, &value, 0);
0115     msleep(100);
0116     cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
0117     return r8712_fw_cmd(pAdapter, cmd32);
0118 }
0119
0120 /* offset : 0X800~0XFFF */
0121 u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
0122 {
0123     u8 shift = offset & 0x0003; /* 4 byte access */
0124     u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
0125     u32 bb_val = 0;
0126     struct IOCMD_STRUCT iocmd;
0127
0128     iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
0129     iocmd.value = bb_addr;
0130     iocmd.index = IOCMD_BB_READ_IDX;
0131     bb_val = fw_iocmd_read(pAdapter, iocmd);
0132     if (shift != 0) {
0133         u32 bb_val2 = 0;
0134
0135         bb_val >>= (shift * 8);
0136         iocmd.value += 4;
0137         bb_val2 = fw_iocmd_read(pAdapter, iocmd);
0138         bb_val2 <<= ((4 - shift) * 8);
0139         bb_val |= bb_val2;
0140     }
0141     return bb_val;
0142 }
0143
0144 /* offset : 0X800~0XFFF */
0145 u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
0146 {
0147     u8 shift = offset & 0x0003; /* 4 byte access */
0148     u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
0149     struct IOCMD_STRUCT iocmd;
0150
0151     iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
0152     iocmd.value = bb_addr;
0153     iocmd.index = IOCMD_BB_WRITE_IDX;
0154     if (shift != 0) {
0155         u32 oldValue = 0;
0156         u32 newValue = value;
0157
0158         oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
0159         oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
0160         value = oldValue | (newValue << (shift * 8));
0161         if (!fw_iocmd_write(pAdapter, iocmd, value))
0162             return false;
0163         iocmd.value += 4;
0164         oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
0165         oldValue &= (0xFFFFFFFF << (shift * 8));
0166         value = oldValue | (newValue >> ((4 - shift) * 8));
0167     }
0168     return fw_iocmd_write(pAdapter, iocmd, value);
0169 }
0170
0171 /* offset : 0x00 ~ 0xFF */
0172 u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
0173 {
0174     u16 rf_addr = (path << 8) | offset;
0175     struct IOCMD_STRUCT iocmd;
0176
0177     iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
0178     iocmd.value = rf_addr;
0179     iocmd.index = IOCMD_RF_READ_IDX;
0180     return fw_iocmd_read(pAdapter, iocmd);
0181 }
0182
0183 u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
0184 {
0185     u16 rf_addr = (path << 8) | offset;
0186     struct IOCMD_STRUCT iocmd;
0187
0188     iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
0189     iocmd.value = rf_addr;
0190     iocmd.index = IOCMD_RF_WRIT_IDX;
0191     return fw_iocmd_write(pAdapter, iocmd, value);
0192 }
0193
0194 static u32 bitshift(u32 bitmask)
0195 {
0196     u32 i;
0197
0198     for (i = 0; i <= 31; i++)
0199         if (((bitmask >> i) &  0x1) == 1)
0200             break;
0201     return i;
0202 }
0203
0204 static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
0205 {
0206     u32 org_value, bit_shift;
0207
0208     org_value = r8712_bb_reg_read(pAdapter, offset);
0209     bit_shift = bitshift(bitmask);
0210     return (org_value & bitmask) >> bit_shift;
0211 }
0212
0213 static u8 set_bb_reg(struct _adapter *pAdapter,
0214              u16 offset,
0215              u32 bitmask,
0216              u32 value)
0217 {
0218     u32 org_value, bit_shift, new_value;
0219
0220     if (bitmask != bMaskDWord) {
0221         org_value = r8712_bb_reg_read(pAdapter, offset);
0222         bit_shift = bitshift(bitmask);
0223         new_value = (org_value & (~bitmask)) | (value << bit_shift);
0224     } else {
0225         new_value = value;
0226     }
0227     return r8712_bb_reg_write(pAdapter, offset, new_value);
0228 }
0229
0230 static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
0231               u32 bitmask)
0232 {
0233     u32 org_value, bit_shift;
0234
0235     org_value = r8712_rf_reg_read(pAdapter, path, offset);
0236     bit_shift = bitshift(bitmask);
0237     return (org_value & bitmask) >> bit_shift;
0238 }
0239
0240 static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
0241           u32 value)
0242 {
0243     u32 org_value, bit_shift, new_value;
0244
0245     if (bitmask != bMaskDWord) {
0246         org_value = r8712_rf_reg_read(pAdapter, path, offset);
0247         bit_shift = bitshift(bitmask);
0248         new_value = (org_value & (~bitmask)) | (value << bit_shift);
0249     } else {
0250         new_value = value;
0251     }
0252     return r8712_rf_reg_write(pAdapter, path, offset, new_value);
0253 }
0254
0255 /*
0256  * SetChannel
0257  * Description
0258  *  Use H2C command to change channel,
0259  *  not only modify rf register, but also other setting need to be done.
0260  */
0261 void r8712_SetChannel(struct _adapter *pAdapter)
0262 {
0263     struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
0264     struct cmd_obj *pcmd = NULL;
0265     struct SetChannel_parm *pparm = NULL;
0266     u16 code = GEN_CMD_CODE(_SetChannel);
0267
0268     pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
0269     if (!pcmd)
0270         return;
0271     pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
0272     if (!pparm) {
0273         kfree(pcmd);
0274         return;
0275     }
0276     pparm->curr_ch = pAdapter->mppriv.curr_ch;
0277     init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
0278     r8712_enqueue_cmd(pcmdpriv, pcmd);
0279 }
0280
0281 static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
0282 {
0283     u16 TxAGC = 0;
0284
0285     TxAGC = TxPower;
0286     set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
0287 }
0288
0289 static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
0290 {
0291     u32 TxAGC = 0;
0292
0293     TxAGC |= ((TxPower << 24) | (TxPower << 16) | (TxPower << 8) |
0294           TxPower);
0295     set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
0296     set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
0297     set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
0298     set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
0299     set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
0300     set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
0301 }
0302
0303 void r8712_SetTxPower(struct _adapter *pAdapter)
0304 {
0305     u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
0306
0307     SetCCKTxPower(pAdapter, TxPower);
0308     SetOFDMTxPower(pAdapter, TxPower);
0309 }
0310
0311 void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
0312 {
0313     u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
0314
0315     TxAGCOffset_B = ulTxAGCOffset & 0x000000ff;
0316     TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
0317     TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
0318     tmpAGC = TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B;
0319     set_bb_reg(pAdapter, rFPGA0_TxGainStage,
0320             (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
0321 }
0322
0323 void r8712_SetDataRate(struct _adapter *pAdapter)
0324 {
0325     u8 path = RF_PATH_A;
0326     u8 offset = RF_SYN_G2;
0327     u32 value;
0328
0329     value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
0330     r8712_rf_reg_write(pAdapter, path, offset, value);
0331 }
0332
0333 void r8712_SwitchBandwidth(struct _adapter *pAdapter)
0334 {
0335     /* 3 1.Set MAC register : BWOPMODE  bit2:1 20MhzBW */
0336     u8 regBwOpMode = 0;
0337     u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
0338
0339     regBwOpMode = r8712_read8(pAdapter, 0x10250203);
0340     if (Bandwidth == HT_CHANNEL_WIDTH_20)
0341         regBwOpMode |= BIT(2);
0342     else
0343         regBwOpMode &= ~(BIT(2));
0344     r8712_write8(pAdapter, 0x10250203, regBwOpMode);
0345     /* 3 2.Set PHY related register */
0346     switch (Bandwidth) {
0347     /* 20 MHz channel*/
0348     case HT_CHANNEL_WIDTH_20:
0349         set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
0350         set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
0351         /* Use PHY_REG.txt default value. Do not need to change.
0352          * Correct the tx power for CCK rate in 40M.
0353          * It is set in Tx descriptor for 8192x series
0354          */
0355         set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
0356         break;
0357     /* 40 MHz channel*/
0358     case HT_CHANNEL_WIDTH_40:
0359         set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
0360         set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
0361         /* Use PHY_REG.txt default value. Do not need to change.
0362          * Correct the tx power for CCK rate in 40M.
0363          * Set Control channel to upper or lower. These settings are
0364          * required only for 40MHz
0365          */
0366         set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
0367                (HAL_PRIME_CHNL_OFFSET_DONT_CARE >> 1));
0368         set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
0369                HAL_PRIME_CHNL_OFFSET_DONT_CARE);
0370         set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
0371         break;
0372     default:
0373         break;
0374     }
0375
0376     /* 3 3.Set RF related register */
0377     switch (Bandwidth) {
0378     case HT_CHANNEL_WIDTH_20:
0379         set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
0380                BIT(10) | BIT(11), 0x01);
0381         break;
0382     case HT_CHANNEL_WIDTH_40:
0383         set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
0384                BIT(10) | BIT(11), 0x00);
0385         break;
0386     default:
0387         break;
0388     }
0389 }
0390
0391 /*------------------------------Define structure----------------------------*/
0392 struct R_ANTENNA_SELECT_OFDM {
0393     u32 r_tx_antenna:4;
0394     u32 r_ant_l:4;
0395     u32 r_ant_non_ht:4;
0396     u32 r_ant_ht1:4;
0397     u32 r_ant_ht2:4;
0398     u32 r_ant_ht_s1:4;
0399     u32 r_ant_non_ht_s1:4;
0400     u32 OFDM_TXSC:2;
0401     u32 Reserved:2;
0402 };
0403
0404 struct R_ANTENNA_SELECT_CCK {
0405     u8  r_cckrx_enable_2:2;
0406     u8  r_cckrx_enable:2;
0407     u8  r_ccktx_enable:4;
0408 };
0409
0410 void r8712_SwitchAntenna(struct _adapter *pAdapter)
0411 {
0412     u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
0413     u8  ofdm_rx_ant_sel_val = 0;
0414     u8  cck_ant_select_val = 0;
0415     u32 cck_ant_sel_val = 0;
0416     struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
0417
0418     p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
0419
0420     switch (pAdapter->mppriv.antenna_tx) {
0421     case ANTENNA_A:
0422         /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
0423         set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
0424         set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
0425         ofdm_tx_en_val = 0x3;
0426         ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
0427         p_cck_txrx->r_ccktx_enable = 0x8;
0428         break;
0429     case ANTENNA_B:
0430         set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
0431         set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
0432         ofdm_tx_en_val = 0x3;
0433         ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
0434         p_cck_txrx->r_ccktx_enable = 0x4;
0435         break;
0436     case ANTENNA_AB:    /* For 8192S */
0437         set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
0438         set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
0439         ofdm_tx_en_val = 0x3;
0440         ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
0441         p_cck_txrx->r_ccktx_enable = 0xC;
0442         break;
0443     default:
0444         break;
0445     }
0446     /*OFDM Tx*/
0447     set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
0448     /*OFDM Tx*/
0449     set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
0450     switch (pAdapter->mppriv.antenna_rx) {
0451     case ANTENNA_A:
0452         ofdm_rx_ant_sel_val = 0x1;  /* A */
0453         p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
0454         p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
0455         break;
0456     case ANTENNA_B:
0457         ofdm_rx_ant_sel_val = 0x2;  /* B */
0458         p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
0459         p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
0460         break;
0461     case ANTENNA_AB:
0462         ofdm_rx_ant_sel_val = 0x3; /* AB */
0463         p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
0464         p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
0465         break;
0466     default:
0467         break;
0468     }
0469     /*OFDM Rx*/
0470     set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
0471            ofdm_rx_ant_sel_val);
0472     /*OFDM Rx*/
0473     set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
0474            ofdm_rx_ant_sel_val);
0475
0476     cck_ant_sel_val = cck_ant_select_val;
0477     /*CCK TxRx*/
0478     set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
0479 }
0480
0481 static void TriggerRFThermalMeter(struct _adapter *pAdapter)
0482 {
0483     /* 0x24: RF Reg[6:5] */
0484     set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
0485 }
0486
0487 static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
0488 {
0489     /* 0x24: RF Reg[4:0] */
0490     return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
0491 }
0492
0493 void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
0494 {
0495     TriggerRFThermalMeter(pAdapter);
0496     msleep(1000);
0497     *value = ReadRFThermalMeter(pAdapter);
0498 }
0499
0500 void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
0501 {
0502     if (bStart) { /* Start Single Carrier. */
0503         /* 1. if OFDM block on? */
0504         if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
0505             /*set OFDM block on*/
0506             set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
0507         /* 2. set CCK test mode off, set to CCK normal mode */
0508         set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
0509         /* 3. turn on scramble setting */
0510         set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
0511         /* 4. Turn On Single Carrier Tx and off the other test modes. */
0512         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
0513         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
0514         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
0515     } else { /* Stop Single Carrier.*/
0516         /* Turn off all test modes.*/
0517         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
0518         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
0519                bDisable);
0520         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
0521         msleep(20);
0522         /*BB Reset*/
0523         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
0524         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
0525     }
0526 }
0527
0528 void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
0529 {
0530     u8 rfPath;
0531
0532     switch (pAdapter->mppriv.antenna_tx) {
0533     case ANTENNA_B:
0534         rfPath = RF_PATH_B;
0535         break;
0536     case ANTENNA_A:
0537     default:
0538         rfPath = RF_PATH_A;
0539         break;
0540     }
0541     if (bStart) { /* Start Single Tone.*/
0542         set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
0543         set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
0544         set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
0545                0xd4000);
0546         msleep(100);
0547         /* PAD all on.*/
0548         set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
0549         msleep(100);
0550     } else { /* Stop Single Tone.*/
0551         set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
0552         set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
0553         set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
0554                0x54000);
0555         msleep(100);
0556         /* PAD all on.*/
0557         set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
0558         msleep(100);
0559     }
0560 }
0561
0562 void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
0563 {
0564     if (bStart) { /* Start Carrier Suppression.*/
0565         if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
0566             /* 1. if CCK block on? */
0567             if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
0568                 /*set CCK block on*/
0569                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
0570                        bEnable);
0571             }
0572             /* Turn Off All Test Mode */
0573             set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
0574                    bDisable);
0575             set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
0576                    bDisable);
0577             set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
0578                    bDisable);
0579             /*transmit mode*/
0580             set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
0581             /*turn off scramble setting*/
0582             set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
0583                    bDisable);
0584             /*Set CCK Tx Test Rate*/
0585             /*Set FTxRate to 1Mbps*/
0586             set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
0587         }
0588     } else { /* Stop Carrier Suppression. */
0589         if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
0590             /*normal mode*/
0591             set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
0592             /*turn on scramble setting*/
0593             set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
0594                    bEnable);
0595             /*BB Reset*/
0596             set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
0597             set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
0598         }
0599     }
0600 }
0601
0602 static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
0603 {
0604     u32 cckrate;
0605
0606     if (bStart) {
0607         /* 1. if CCK block on? */
0608         if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
0609             /*set CCK block on*/
0610             set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
0611         }
0612         /* Turn Off All Test Mode */
0613         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
0614         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
0615         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
0616         /*Set CCK Tx Test Rate*/
0617         cckrate  = pAdapter->mppriv.curr_rateidx;
0618         set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
0619         /*transmit mode*/
0620         set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
0621         /*turn on scramble setting*/
0622         set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
0623     } else {
0624         /*normal mode*/
0625         set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
0626         /*turn on scramble setting*/
0627         set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
0628         /*BB Reset*/
0629         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
0630         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
0631     }
0632 } /* mpt_StartCckContTx */
0633
0634 static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
0635 {
0636     if (bStart) {
0637         /* 1. if OFDM block on? */
0638         if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
0639             /*set OFDM block on*/
0640             set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
0641         }
0642         /* 2. set CCK test mode off, set to CCK normal mode*/
0643         set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
0644         /* 3. turn on scramble setting */
0645         set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
0646         /* 4. Turn On Continue Tx and turn off the other test modes.*/
0647         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
0648         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
0649         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
0650     } else {
0651         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
0652         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
0653                bDisable);
0654         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
0655         msleep(20);
0656         /*BB Reset*/
0657         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
0658         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
0659     }
0660 } /* mpt_StartOfdmContTx */
0661
0662 void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
0663 {
0664     /* ADC turn off [bit24-21] adc port0 ~ port1 */
0665     if (bStart) {
0666         r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
0667                    r8712_bb_reg_read(pAdapter,
0668                    rRx_Wait_CCCA) & 0xFE1FFFFF);
0669         msleep(100);
0670     }
0671     if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
0672         SetCCKContinuousTx(pAdapter, bStart);
0673     else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
0674          (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
0675         SetOFDMContinuousTx(pAdapter, bStart);
0676     /* ADC turn on [bit24-21] adc port0 ~ port1 */
0677     if (!bStart)
0678         r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
0679                    r8712_bb_reg_read(pAdapter,
0680                    rRx_Wait_CCCA) | 0x01E00000);
0681 }
0682
0683 void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
0684 {
0685     u32 i, phyrx_set = 0;
0686
0687     for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
0688         phyrx_set = 0;
0689         phyrx_set |= (i << 28);     /*select*/
0690         phyrx_set |= 0x08000000;    /* set counter to zero*/
0691         r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
0692     }
0693 }
0694
0695 static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
0696 {
0697     /*selection*/
0698     u32 phyrx_set = 0;
0699     u32 SelectBit;
0700
0701     SelectBit = selbit << 28;
0702     phyrx_set |= (SelectBit & 0xF0000000);
0703     r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
0704     /*Read packet count*/
0705     return r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
0706 }
0707
0708 u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
0709 {
0710     u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
0711     u32 CCK_cnt  = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
0712     u32 HT_cnt   = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
0713
0714     return OFDM_cnt + CCK_cnt + HT_cnt;
0715 }
0716
0717 u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
0718 {
0719     u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
0720     u32 CCK_cnt  = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
0721     u32 HT_cnt   = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
0722
0723     return OFDM_cnt + CCK_cnt + HT_cnt;
0724 }