staging/rtl8712/rtl8712_spec.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /******************************************************************************
0003  *
0004  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
0005  *
0006  * Modifications for inclusion into the Linux staging tree are
0007  * Copyright(c) 2010 Larry Finger. All rights reserved.
0008  *
0009  * Contact information:
0010  * WLAN FAE <wlanfae@realtek.com>
0011  * Larry Finger <Larry.Finger@lwfinger.net>
0012  *
0013  ******************************************************************************/
0014 #ifndef __RTL8712_SPEC_H__
0015 #define __RTL8712_SPEC_H__
0016
0017 #define RTL8712_IOBASE_TXPKT        0x10200000  /*IOBASE_TXPKT*/
0018 #define RTL8712_IOBASE_RXPKT        0x10210000  /*IOBASE_RXPKT*/
0019 #define RTL8712_IOBASE_RXCMD        0x10220000  /*IOBASE_RXCMD*/
0020 #define RTL8712_IOBASE_TXSTATUS     0x10230000  /*IOBASE_TXSTATUS*/
0021 #define RTL8712_IOBASE_RXSTATUS     0x10240000  /*IOBASE_RXSTATUS*/
0022 #define RTL8712_IOBASE_IOREG        0x10250000  /*IOBASE_IOREG ADDR*/
0023 #define RTL8712_IOBASE_SCHEDULER    0x10260000  /*IOBASE_SCHEDULE*/
0024
0025 #define RTL8712_IOBASE_TRXDMA       0x10270000  /*IOBASE_TRXDMA*/
0026 #define RTL8712_IOBASE_TXLLT        0x10280000  /*IOBASE_TXLLT*/
0027 #define RTL8712_IOBASE_WMAC     0x10290000  /*IOBASE_WMAC*/
0028 #define RTL8712_IOBASE_FW2HW        0x102A0000  /*IOBASE_FW2HW*/
0029 #define RTL8712_IOBASE_ACCESS_PHYREG    0x102B0000  /*IOBASE_ACCESS_PHYREG*/
0030
0031 #define RTL8712_IOBASE_FF   0x10300000 /*IOBASE_FIFO 0x1031000~0x103AFFFF*/
0032
0033 /*IOREG Offset for 8712*/
0034 #define RTL8712_SYSCFG_     RTL8712_IOBASE_IOREG
0035 #define RTL8712_CMDCTRL_    (RTL8712_IOBASE_IOREG + 0x40)
0036 #define RTL8712_MACIDSETTING_   (RTL8712_IOBASE_IOREG + 0x50)
0037 #define RTL8712_TIMECTRL_   (RTL8712_IOBASE_IOREG + 0x80)
0038 #define RTL8712_FIFOCTRL_   (RTL8712_IOBASE_IOREG + 0xA0)
0039 #define RTL8712_RATECTRL_   (RTL8712_IOBASE_IOREG + 0x160)
0040 #define RTL8712_EDCASETTING_    (RTL8712_IOBASE_IOREG + 0x1D0)
0041 #define RTL8712_WMAC_       (RTL8712_IOBASE_IOREG + 0x200)
0042 #define RTL8712_SECURITY_   (RTL8712_IOBASE_IOREG + 0x240)
0043 #define RTL8712_POWERSAVE_  (RTL8712_IOBASE_IOREG + 0x260)
0044 #define RTL8712_GP_     (RTL8712_IOBASE_IOREG + 0x2E0)
0045 #define RTL8712_INTERRUPT_  (RTL8712_IOBASE_IOREG + 0x300)
0046 #define RTL8712_DEBUGCTRL_  (RTL8712_IOBASE_IOREG + 0x310)
0047 #define RTL8712_OFFLOAD_    (RTL8712_IOBASE_IOREG + 0x2D0)
0048
0049 /*FIFO for 8712*/
0050 #define RTL8712_DMA_BCNQ    (RTL8712_IOBASE_FF + 0x10000)
0051 #define RTL8712_DMA_MGTQ    (RTL8712_IOBASE_FF + 0x20000)
0052 #define RTL8712_DMA_BMCQ    (RTL8712_IOBASE_FF + 0x30000)
0053 #define RTL8712_DMA_VOQ     (RTL8712_IOBASE_FF + 0x40000)
0054 #define RTL8712_DMA_VIQ     (RTL8712_IOBASE_FF + 0x50000)
0055 #define RTL8712_DMA_BEQ     (RTL8712_IOBASE_FF + 0x60000)
0056 #define RTL8712_DMA_BKQ     (RTL8712_IOBASE_FF + 0x70000)
0057 #define RTL8712_DMA_RX0FF   (RTL8712_IOBASE_FF + 0x80000)
0058 #define RTL8712_DMA_H2CCMD  (RTL8712_IOBASE_FF + 0x90000)
0059 #define RTL8712_DMA_C2HCMD  (RTL8712_IOBASE_FF + 0xA0000)
0060
0061 /*------------------------------*/
0062
0063 /*BIT 16 15*/
0064 #define DID_SDIO_LOCAL          0   /* 0 0*/
0065 #define DID_WLAN_IOREG          1   /* 0 1*/
0066 #define DID_WLAN_FIFO           3   /* 1 1*/
0067 #define   DID_UNDEFINE              (-1)
0068
0069 #define CMD_ADDR_MAPPING_SHIFT      2   /*SDIO CMD ADDR MAPPING,
0070                          *shift 2 bit for match
0071                          * offset[14:2]
0072                          */
0073
0074 /*Offset for SDIO LOCAL*/
0075 #define OFFSET_SDIO_LOCAL               0x0FFF
0076
0077 /*Offset for WLAN IOREG*/
0078 #define OFFSET_WLAN_IOREG               0x0FFF
0079
0080 /*Offset for WLAN FIFO*/
0081 #define OFFSET_TX_BCNQ              0x0300
0082 #define OFFSET_TX_HIQ                   0x0310
0083 #define OFFSET_TX_CMDQ              0x0320
0084 #define OFFSET_TX_MGTQ              0x0330
0085 #define OFFSET_TX_HCCAQ             0x0340
0086 #define OFFSET_TX_VOQ                   0x0350
0087 #define OFFSET_TX_VIQ                   0x0360
0088 #define OFFSET_TX_BEQ                   0x0370
0089 #define OFFSET_TX_BKQ                   0x0380
0090 #define OFFSET_RX_RX0FFQ                0x0390
0091 #define OFFSET_RX_C2HFFQ                0x03A0
0092
0093 #define BK_QID_01   1
0094 #define BK_QID_02   2
0095 #define BE_QID_01   0
0096 #define BE_QID_02   3
0097 #define VI_QID_01   4
0098 #define VI_QID_02   5
0099 #define VO_QID_01   6
0100 #define VO_QID_02   7
0101 #define HCCA_QID_01 8
0102 #define HCCA_QID_02 9
0103 #define HCCA_QID_03 10
0104 #define HCCA_QID_04 11
0105 #define HCCA_QID_05 12
0106 #define HCCA_QID_06 13
0107 #define HCCA_QID_07 14
0108 #define HCCA_QID_08 15
0109 #define HI_QID      17
0110 #define CMD_QID 19
0111 #define MGT_QID 18
0112 #define BCN_QID 16
0113
0114 #include "rtl8712_regdef.h"
0115
0116 #include "rtl8712_bitdef.h"
0117
0118 #include "basic_types.h"
0119
0120 #endif /* __RTL8712_SPEC_H__ */
0121