staging/rtl8192u/r819xU_phyreg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _R819XU_PHYREG_H
0003 #define _R819XU_PHYREG_H
0004
0005 #define   RF_DATA               0x1d4                   /* FW will write RF data in the register.*/
0006
0007 /* page8 */
0008 #define rFPGA0_RFMOD                0x800  /* RF mode & CCK TxSC */
0009 #define rFPGA0_TxGainStage          0x80c
0010 #define rFPGA0_XA_HSSIParameter1    0x820
0011 #define rFPGA0_XA_HSSIParameter2    0x824
0012 #define rFPGA0_XB_HSSIParameter1    0x828
0013 #define rFPGA0_XB_HSSIParameter2    0x82c
0014 #define rFPGA0_XC_HSSIParameter1    0x830
0015 #define rFPGA0_XC_HSSIParameter2    0x834
0016 #define rFPGA0_XD_HSSIParameter1    0x838
0017 #define rFPGA0_XD_HSSIParameter2    0x83c
0018 #define rFPGA0_XA_LSSIParameter     0x840
0019 #define rFPGA0_XB_LSSIParameter     0x844
0020 #define rFPGA0_XC_LSSIParameter     0x848
0021 #define rFPGA0_XD_LSSIParameter     0x84c
0022 #define rFPGA0_XAB_SwitchControl    0x858
0023 #define rFPGA0_XCD_SwitchControl    0x85c
0024 #define rFPGA0_XA_RFInterfaceOE     0x860
0025 #define rFPGA0_XB_RFInterfaceOE     0x864
0026 #define rFPGA0_XC_RFInterfaceOE     0x868
0027 #define rFPGA0_XD_RFInterfaceOE     0x86c
0028 #define rFPGA0_XAB_RFInterfaceSW    0x870
0029 #define rFPGA0_XCD_RFInterfaceSW    0x874
0030 #define rFPGA0_XAB_RFParameter      0x878
0031 #define rFPGA0_XCD_RFParameter      0x87c
0032 #define rFPGA0_AnalogParameter1     0x880
0033 #define rFPGA0_AnalogParameter4     0x88c
0034 #define rFPGA0_XA_LSSIReadBack      0x8a0
0035 #define rFPGA0_XB_LSSIReadBack      0x8a4
0036 #define rFPGA0_XC_LSSIReadBack      0x8a8
0037 #define rFPGA0_XD_LSSIReadBack      0x8ac
0038 #define rFPGA0_XAB_RFInterfaceRB    0x8e0
0039 #define rFPGA0_XCD_RFInterfaceRB    0x8e4
0040
0041 /* page 9 */
0042 #define rFPGA1_RFMOD                0x900  /* RF mode & OFDM TxSC */
0043
0044 /* page a */
0045 #define rCCK0_System                0xa00
0046 #define rCCK0_AFESetting            0xa04
0047 #define rCCK0_CCA                   0xa08
0048 #define rCCK0_TxFilter1             0xa20
0049 #define rCCK0_TxFilter2             0xa24
0050 #define rCCK0_DebugPort             0xa28  /* debug port and Tx filter3 */
0051
0052 /* page c */
0053 #define rOFDM0_TRxPathEnable        0xc04
0054 #define rOFDM0_XARxAFE              0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
0055 #define rOFDM0_XARxIQImbalance      0xc14  /* RxIQ imbalance matrix */
0056 #define rOFDM0_XBRxAFE              0xc18
0057 #define rOFDM0_XBRxIQImbalance      0xc1c
0058 #define rOFDM0_XCRxAFE              0xc20
0059 #define rOFDM0_XCRxIQImbalance      0xc24
0060 #define rOFDM0_XDRxAFE              0xc28
0061 #define rOFDM0_XDRxIQImbalance      0xc2c
0062 #define rOFDM0_RxDetector1          0xc30  /* PD,BW & SBD */
0063 #define rOFDM0_RxDetector2          0xc34  /* SBD & Fame Sync.*/
0064 #define rOFDM0_RxDetector3          0xc38  /* Frame Sync.*/
0065 #define rOFDM0_ECCAThreshold        0xc4c /* energy CCA */
0066 #define rOFDM0_XAAGCCore1       0xc50
0067 #define rOFDM0_XAAGCCore2       0xc54
0068 #define rOFDM0_XBAGCCore1       0xc58
0069 #define rOFDM0_XBAGCCore2       0xc5c
0070 #define rOFDM0_XCAGCCore1       0xc60
0071 #define rOFDM0_XCAGCCore2       0xc64
0072 #define rOFDM0_XDAGCCore1       0xc68
0073 #define rOFDM0_XDAGCCore2       0xc6c
0074 #define rOFDM0_XATxIQImbalance      0xc80
0075 #define rOFDM0_XATxAFE              0xc84
0076 #define rOFDM0_XBTxIQImbalance      0xc88
0077 #define rOFDM0_XBTxAFE              0xc8c
0078 #define rOFDM0_XCTxIQImbalance      0xc90
0079 #define rOFDM0_XCTxAFE              0xc94
0080 #define rOFDM0_XDTxIQImbalance      0xc98
0081 #define rOFDM0_XDTxAFE              0xc9c
0082
0083 /* page d */
0084 #define rOFDM1_LSTF             0xd00
0085 #define rOFDM1_TRxPathEnable        0xd04
0086
0087 /* page e */
0088 #define rTxAGC_Rate18_06            0xe00
0089 #define rTxAGC_Rate54_24            0xe04
0090 #define rTxAGC_CCK_Mcs32            0xe08
0091 #define rTxAGC_Mcs03_Mcs00          0xe10
0092 #define rTxAGC_Mcs07_Mcs04          0xe14
0093 #define rTxAGC_Mcs11_Mcs08          0xe18
0094 #define rTxAGC_Mcs15_Mcs12          0xe1c
0095
0096 /* RF
0097  * Zebra1
0098  */
0099 #define rZebra1_Channel             0x7
0100
0101 /* Zebra4 */
0102 #define rGlobalCtrl             0
0103
0104 /* Bit Mask
0105  * page-8
0106  */
0107 #define bRFMOD                      0x1
0108 #define bCCKEn                      0x1000000
0109 #define bOFDMEn                     0x2000000
0110 #define bXBTxAGC                    0xf00
0111 #define bXCTxAGC                    0xf000
0112 #define b3WireDataLength            0x800
0113 #define b3WireAddressLength         0x400
0114 #define bRFSI_RFENV             0x10
0115 #define bLSSIReadAddress            0x3f000000   /* LSSI "Read" Address */
0116 #define bLSSIReadEdge               0x80000000   /* LSSI "Read" edge signal */
0117 #define bLSSIReadBackData           0xfff
0118 #define bXtalCap                    0x0f000000
0119
0120 /* page-a */
0121 #define bCCKSideBand                0x10
0122
0123 /* page e */
0124 #define bTxAGCRateCCK           0x7f00
0125
0126 /* RF
0127  * Zebra1
0128  */
0129 #define bZebra1_ChannelNum        0xf80
0130
0131 /* RTL8258 */
0132 /* for PutRegsetting & GetRegSetting BitMask */
0133 #define bMaskByte0                0xff
0134 #define bMaskByte1                0xff00
0135 #define bMaskByte2                0xff0000
0136 #define bMaskHWord                0xffff0000
0137 #define bMaskLWord                0x0000ffff
0138 #define bMaskDWord                0xffffffff
0139
0140 /* for PutRFRegsetting & GetRFRegSetting BitMask */
0141 #define bMask12Bits               0xfff
0142
0143 #endif  /* __INC_HAL8190PCIPHYREG_H */