staging/rtl8192u/r819xU_cmdpkt.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef R819XUSB_CMDPKT_H
0003 #define R819XUSB_CMDPKT_H
0004 /* Different command packet have dedicated message length and definition. */
0005 #define     CMPK_RX_TX_FB_SIZE      sizeof(struct cmd_pkt_tx_feedback)  /* 20 */
0006 #define     CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(struct cmd_pkt_set_configuration)    /* 16 */
0007 #define     CMPK_RX_TX_STS_SIZE     sizeof(cmpk_tx_status_t)
0008 #define     CMPK_TX_RAHIS_SIZE      sizeof(cmpk_tx_rahis_t)
0009
0010 /* 2008/05/08 amy For USB constant. */
0011 #define ISR_TX_BCN_OK       BIT(27)     /* Transmit Beacon OK */
0012 #define ISR_TX_BCN_ERR      BIT(26)     /* Transmit Beacon Error */
0013 #define ISR_BCN_TIMER_INTR  BIT(13)     /* Beacon Timer Interrupt */
0014
0015 /* Define element ID of command packet. */
0016
0017 /*------------------------------Define structure----------------------------*/
0018 /* Define different command packet structure. */
0019 /* 1. RX side: TX feedback packet. */
0020 struct cmd_pkt_tx_feedback {
0021     /* DWORD 0 */
0022     u8  element_id;         /* Command packet type. */
0023     u8  length;             /* Command packet length. */
0024     /* Change tx feedback info field. */
0025     /*------TX Feedback Info Field */
0026     u8  TID:4;
0027     u8  fail_reason:3;
0028     u8  tok:1;              /* Transmit ok. */
0029     u8  reserve1:4;
0030     u8  pkt_type:2;
0031     u8  bandwidth:1;
0032     u8  qos_pkt:1;
0033
0034     /* DWORD 1 */
0035     u8  reserve2;
0036     /*------TX Feedback Info Field */
0037     u8  retry_cnt;
0038     u16 pkt_id;
0039
0040     /* DWORD 3 */
0041     u16 seq_num;
0042     u8  s_rate;             /* Start rate. */
0043     u8  f_rate;             /* Final rate. */
0044
0045     /* DWORD 4 */
0046     u8  s_rts_rate;
0047     u8  f_rts_rate;
0048     u16 pkt_length;
0049
0050     /* DWORD 5 */
0051     u16 reserve3;
0052     u16 duration;
0053 };
0054
0055 /* 2. RX side: Interrupt status packet. It includes Beacon State,
0056  * Beacon Timer Interrupt and other useful information in MAC ISR Reg.
0057  */
0058 struct cmd_pkt_interrupt_status {
0059     u8  element_id;         /* Command packet type. */
0060     u8  length;             /* Command packet length. */
0061     u16 reserve;
0062     u32 interrupt_status;       /* Interrupt Status. */
0063 };
0064
0065 /* 3. TX side: Set configuration packet. */
0066 struct cmd_pkt_set_configuration {
0067     u8  element_id;         /* Command packet type. */
0068     u8  length;             /* Command packet length. */
0069     u16 reserve1;
0070     /* Configuration info. */
0071     u8  cfg_reserve1:3;
0072     u8  cfg_size:2;
0073     u8  cfg_type:2;
0074     u8  cfg_action:1;
0075     u8  cfg_reserve2;
0076     u8  cfg_page:4;
0077     u8  cfg_reserve3:4;
0078     u8  cfg_offset;
0079     u32 value;
0080     u32 mask;
0081 };
0082
0083 /* 4. Both side : TX/RX query configuration packet. The query structure is the
0084  *    same as set configuration.
0085  */
0086 #define     cmpk_query_cfg  cmd_pkt_set_configuration
0087
0088 /* 5. Multi packet feedback status. */
0089 typedef struct tag_tx_stats_feedback {
0090     /* For endian transfer --> Driver will not the same as
0091      *  firmware structure.
0092      */
0093     /* DW 0 */
0094     u16 reserve1;
0095     u8  length;             /* Command packet length */
0096     u8  element_id;         /* Command packet type */
0097
0098     /* DW 1 */
0099     u16 txfail;             /* Tx fail count */
0100     u16 txok;               /* Tx ok count */
0101
0102     /* DW 2 */
0103     u16 txmcok;             /* Tx multicast */
0104     u16 txretry;            /* Tx retry count */
0105
0106     /* DW 3 */
0107     u16 txucok;             /* Tx unicast */
0108     u16 txbcok;             /* Tx broadcast */
0109
0110     /* DW 4 */
0111     u16 txbcfail;
0112     u16 txmcfail;
0113
0114     /* DW 5 */
0115     u16 reserve2;
0116     u16 txucfail;
0117
0118     /* DW 6-8 */
0119     u32 txmclength;
0120     u32 txbclength;
0121     u32 txuclength;
0122
0123     /* DW 9 */
0124     u16 reserve3_23;
0125     u8  reserve3_1;
0126     u8  rate;
0127 } __packed cmpk_tx_status_t;
0128
0129 /* 6. Debug feedback message. */
0130 /* Define RX debug message  */
0131 typedef struct tag_rx_debug_message_feedback {
0132     /* For endian transfer --> for driver */
0133     /* DW 0 */
0134     u16 reserve1;
0135     u8  length;             /* Command packet length */
0136     u8  element_id;         /* Command packet type */
0137
0138     /* DW 1-?? */
0139     /* Variable debug message. */
0140
0141 } cmpk_rx_dbginfo_t;
0142
0143 /* Define transmit rate history. For big endian format. */
0144 typedef struct tag_tx_rate_history {
0145     /* For endian transfer --> for driver */
0146     /* DW 0 */
0147     u8  element_id;         /* Command packet type */
0148     u8  length;             /* Command packet length */
0149     u16 reserved1;
0150
0151     /* DW 1-2   CCK rate counter */
0152     u16 cck[4];
0153
0154     /* DW 3-6 */
0155     u16 ofdm[8];
0156
0157     /* DW 7-14  BW=0 SG=0
0158      * DW 15-22 BW=1 SG=0
0159      * DW 23-30 BW=0 SG=1
0160      * DW 31-38 BW=1 SG=1
0161      */
0162     u16 ht_mcs[4][16];
0163
0164 } __packed cmpk_tx_rahis_t;
0165
0166 typedef enum tag_command_packet_directories {
0167     RX_TX_FEEDBACK          = 0,
0168     RX_INTERRUPT_STATUS     = 1,
0169     TX_SET_CONFIG           = 2,
0170     BOTH_QUERY_CONFIG       = 3,
0171     RX_TX_STATUS            = 4,
0172     RX_DBGINFO_FEEDBACK     = 5,
0173     RX_TX_PER_PKT_FEEDBACK      = 6,
0174     RX_TX_RATE_HISTORY      = 7,
0175     RX_CMD_ELE_MAX
0176 } cmpk_element_e;
0177
0178 typedef enum _rt_status {
0179     RT_STATUS_SUCCESS,
0180     RT_STATUS_FAILURE,
0181     RT_STATUS_PENDING,
0182     RT_STATUS_RESOURCE
0183 } rt_status, *prt_status;
0184
0185 u32 cmpk_message_handle_rx(struct net_device *dev,
0186                struct ieee80211_rx_stats *pstats);
0187 rt_status SendTxCommandPacket(struct net_device *dev,
0188                   void *pData, u32 DataLen);
0189
0190 #endif