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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This is part of rtl8187 OpenSource driver.
0004  * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
0005  * Released under the terms of GPL (General Public Licence)
0006  *
0007  * Parts of this driver are based on the GPL part of the
0008  * official realtek driver
0009  *
0010  * Parts of this driver are based on the rtl8192 driver skeleton
0011  * from Patric Schenke & Andres Salomon
0012  *
0013  * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
0014  *
0015  * We want to thank the Authors of those projects and the Ndiswrapper
0016  * project Authors.
0017  */
0018 
0019 #ifndef R8192U_H
0020 #define R8192U_H
0021 
0022 #include <linux/compiler.h>
0023 #include <linux/module.h>
0024 #include <linux/kernel.h>
0025 #include <linux/ioport.h>
0026 #include <linux/sched.h>
0027 #include <linux/types.h>
0028 #include <linux/slab.h>
0029 #include <linux/netdevice.h>
0030 #include <linux/usb.h>
0031 #include <linux/etherdevice.h>
0032 #include <linux/delay.h>
0033 #include <linux/rtnetlink.h>
0034 #include <linux/wireless.h>
0035 #include <linux/timer.h>
0036 #include <linux/proc_fs.h>
0037 #include <linux/if_arp.h>
0038 #include <linux/random.h>
0039 #include <linux/io.h>
0040 #include "ieee80211/ieee80211.h"
0041 
0042 #define RTL8192U
0043 #define RTL819XU_MODULE_NAME "rtl819xU"
0044 /* HW security */
0045 #define MAX_KEY_LEN     61
0046 #define KEY_BUF_SIZE    5
0047 
0048 #define RX_SMOOTH_FACTOR        20
0049 #define DMESG(x, a...)  no_printk(x, ##a)
0050 #define DMESGW(x, a...) no_printk(x, ##a)
0051 #define DMESGE(x, a...) no_printk(x, ##a)
0052 extern u32 rt_global_debug_component;
0053 #define RT_TRACE(component, x, args...) \
0054     do {                            \
0055         if (rt_global_debug_component & (component))    \
0056             pr_debug("RTL8192U: " x "\n", ##args);  \
0057     } while (0)
0058 
0059 #define COMP_TRACE              BIT(0)  /* Function call tracing. */
0060 #define COMP_DBG                BIT(1)
0061 #define COMP_INIT               BIT(2)  /* Driver initialization/halt/reset. */
0062 
0063 #define COMP_RECV               BIT(3)  /* Receive data path. */
0064 #define COMP_SEND               BIT(4)  /* Send data path. */
0065 #define COMP_IO                 BIT(5)
0066 /* 802.11 Power Save mode or System/Device Power state. */
0067 #define COMP_POWER              BIT(6)
0068 /* 802.11 link related: join/start BSS, leave BSS. */
0069 #define COMP_EPROM              BIT(7)
0070 #define COMP_SWBW               BIT(8)  /* Bandwidth switch. */
0071 #define COMP_POWER_TRACKING     BIT(9)  /* 8190 TX Power Tracking */
0072 #define COMP_TURBO              BIT(10) /* Turbo Mode */
0073 #define COMP_QOS                BIT(11)
0074 #define COMP_RATE               BIT(12) /* Rate Adaptive mechanism */
0075 #define COMP_RM                 BIT(13) /* Radio Measurement */
0076 #define COMP_DIG                BIT(14)
0077 #define COMP_PHY                BIT(15)
0078 #define COMP_CH                 BIT(16) /* Channel setting debug */
0079 #define COMP_TXAGC              BIT(17) /* Tx power */
0080 #define COMP_HIPWR              BIT(18) /* High Power Mechanism */
0081 #define COMP_HALDM              BIT(19) /* HW Dynamic Mechanism */
0082 #define COMP_SEC                BIT(20) /* Event handling */
0083 #define COMP_LED                BIT(21)
0084 #define COMP_RF                 BIT(22)
0085 #define COMP_RXDESC             BIT(23) /* Rx desc information for SD3 debug */
0086 
0087 /* 11n or 8190 specific code */
0088 
0089 #define COMP_FIRMWARE           BIT(24) /* Firmware downloading */
0090 #define COMP_HT                 BIT(25) /* 802.11n HT related information */
0091 #define COMP_AMSDU              BIT(26) /* A-MSDU Debugging */
0092 #define COMP_SCAN               BIT(27)
0093 #define COMP_DOWN               BIT(29) /* rm driver module */
0094 #define COMP_RESET              BIT(30) /* Silent reset */
0095 #define COMP_ERR                BIT(31) /* Error out, always on */
0096 
0097 #define RTL819x_DEBUG
0098 #ifdef RTL819x_DEBUG
0099 #define RTL8192U_ASSERT(expr) \
0100     do {                                \
0101         if (!(expr)) {                      \
0102             pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
0103                  #expr, __FILE__, __func__, __LINE__);  \
0104         }                           \
0105     } while (0)
0106 /*
0107  * Debug out data buf.
0108  * If you want to print DATA buffer related BA,
0109  * please set ieee80211_debug_level to DATA|BA
0110  */
0111 #define RT_DEBUG_DATA(level, data, datalen) \
0112     do {                                \
0113         if ((rt_global_debug_component & (level)) == (level)) { \
0114             int i;                      \
0115             u8 *pdata = (u8 *)data;             \
0116             pr_debug("RTL8192U: %s()\n", __func__);     \
0117             for (i = 0; i < (int)(datalen); i++) {      \
0118                 printk("%2x ", pdata[i]);               \
0119                 if ((i+1)%16 == 0)          \
0120                     printk("\n");           \
0121             }                       \
0122             printk("\n");                   \
0123         }                           \
0124     } while (0)
0125 #else
0126 #define RTL8192U_ASSERT(expr) do {} while (0)
0127 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
0128 #endif /* RTL8169_DEBUG */
0129 
0130 /* Queue Select Value in TxDesc */
0131 #define QSLT_BK                                 0x1
0132 #define QSLT_BE                                 0x0
0133 #define QSLT_VI                                 0x4
0134 #define QSLT_VO                                 0x6
0135 #define QSLT_BEACON                             0x10
0136 #define QSLT_HIGH                               0x11
0137 #define QSLT_MGNT                               0x12
0138 #define QSLT_CMD                                0x13
0139 
0140 #define DESC90_RATE1M                           0x00
0141 #define DESC90_RATE2M                           0x01
0142 #define DESC90_RATE5_5M                         0x02
0143 #define DESC90_RATE11M                          0x03
0144 #define DESC90_RATE6M                           0x04
0145 #define DESC90_RATE9M                           0x05
0146 #define DESC90_RATE12M                          0x06
0147 #define DESC90_RATE18M                          0x07
0148 #define DESC90_RATE24M                          0x08
0149 #define DESC90_RATE36M                          0x09
0150 #define DESC90_RATE48M                          0x0a
0151 #define DESC90_RATE54M                          0x0b
0152 #define DESC90_RATEMCS0                         0x00
0153 #define DESC90_RATEMCS1                         0x01
0154 #define DESC90_RATEMCS2                         0x02
0155 #define DESC90_RATEMCS3                         0x03
0156 #define DESC90_RATEMCS4                         0x04
0157 #define DESC90_RATEMCS5                         0x05
0158 #define DESC90_RATEMCS6                         0x06
0159 #define DESC90_RATEMCS7                         0x07
0160 #define DESC90_RATEMCS8                         0x08
0161 #define DESC90_RATEMCS9                         0x09
0162 #define DESC90_RATEMCS10                        0x0a
0163 #define DESC90_RATEMCS11                        0x0b
0164 #define DESC90_RATEMCS12                        0x0c
0165 #define DESC90_RATEMCS13                        0x0d
0166 #define DESC90_RATEMCS14                        0x0e
0167 #define DESC90_RATEMCS15                        0x0f
0168 #define DESC90_RATEMCS32                        0x20
0169 
0170 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
0171 
0172 #define IEEE80211_WATCH_DOG_TIME    2000
0173 #define     PHY_Beacon_RSSI_SLID_WIN_MAX        10
0174 /* For Tx Power Tracking */
0175 #define     OFDM_Table_Length   19
0176 #define CCK_Table_length    12
0177 
0178 /* For rtl819x */
0179 struct tx_desc_819x_usb {
0180     /* DWORD 0 */
0181     u16 PktSize;
0182     u8  Offset;
0183     u8  Reserved0:3;
0184     u8  CmdInit:1;
0185     u8  LastSeg:1;
0186     u8  FirstSeg:1;
0187     u8  LINIP:1;
0188     u8  OWN:1;
0189 
0190     /* DWORD 1 */
0191     u8  TxFWInfoSize;
0192     u8  RATid:3;
0193     u8  DISFB:1;
0194     u8  USERATE:1;
0195     u8  MOREFRAG:1;
0196     u8  NoEnc:1;
0197     u8  PIFS:1;
0198     u8  QueueSelect:5;
0199     u8  NoACM:1;
0200     u8  Reserved1:2;
0201     u8  SecCAMID:5;
0202     u8  SecDescAssign:1;
0203     u8  SecType:2;
0204 
0205     /* DWORD 2 */
0206     u16 TxBufferSize;
0207     u8  ResvForPaddingLen:7;
0208     u8  Reserved3:1;
0209     u8  Reserved4;
0210 
0211     /* DWORD 3, 4, 5 */
0212     u32 Reserved5;
0213     u32 Reserved6;
0214     u32 Reserved7;
0215 };
0216 
0217 struct tx_desc_cmd_819x_usb {
0218     /* DWORD 0 */
0219     u16 Reserved0;
0220     u8  Reserved1;
0221     u8  Reserved2:3;
0222     u8  CmdInit:1;
0223     u8  LastSeg:1;
0224     u8  FirstSeg:1;
0225     u8  LINIP:1;
0226     u8  OWN:1;
0227 
0228     /* DOWRD 1 */
0229     u8  TxFWInfoSize;
0230     u8  Reserved3;
0231     u8  QueueSelect;
0232     u8  Reserved4;
0233 
0234     /* DOWRD 2 */
0235     u16 TxBufferSize;
0236     u16 Reserved5;
0237 
0238     /* DWORD 3, 4, 5 */
0239     u32 Reserved6;
0240     u32 Reserved7;
0241     u32 Reserved8;
0242 };
0243 
0244 struct tx_fwinfo_819x_usb {
0245     /* DOWRD 0 */
0246     u8  TxRate:7;
0247     u8  CtsEnable:1;
0248     u8  RtsRate:7;
0249     u8  RtsEnable:1;
0250     u8  TxHT:1;
0251     u8  Short:1;        /* Error out, always on */
0252     u8  TxBandwidth:1;  /* Used for HT MCS rate only */
0253     u8  TxSubCarrier:2; /* Used for legacy OFDM rate only */
0254     u8  STBC:2;
0255     u8  AllowAggregation:1;
0256     /* Interpret RtsRate field as high throughput data rate */
0257     u8  RtsHT:1;
0258     u8  RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
0259     u8  RtsBandwidth:1; /* Used for HT MCS rate only */
0260     u8  RtsSubcarrier:2;/* Used for legacy OFDM rate only */
0261     u8  RtsSTBC:2;
0262     /* Enable firmware to recalculate and assign packet duration */
0263     u8  EnableCPUDur:1;
0264 
0265     /* DWORD 1 */
0266     u32 RxMF:2;
0267     u32 RxAMD:3;
0268     /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
0269     u32 TxPerPktInfoFeedback:1;
0270     u32 Reserved1:2;
0271     u32 TxAGCOffSet:4;
0272     u32 TxAGCSign:1;
0273     u32 Tx_INFO_RSVD:6;
0274     u32 PacketID:13;
0275 };
0276 
0277 struct rtl8192_rx_info {
0278     struct urb *urb;
0279     struct net_device *dev;
0280     u8 out_pipe;
0281 };
0282 
0283 struct rx_desc_819x_usb {
0284     /* DOWRD 0 */
0285     u16                 Length:14;
0286     u16                 CRC32:1;
0287     u16                 ICV:1;
0288     u8                  RxDrvInfoSize;
0289     u8                  Shift:2;
0290     u8                  PHYStatus:1;
0291     u8                  SWDec:1;
0292     u8                  Reserved1:4;
0293 
0294     /* DWORD 1 */
0295     u32                 Reserved2;
0296 };
0297 
0298 struct rx_drvinfo_819x_usb {
0299     /* DWORD 0 */
0300     u16                 Reserved1:12;
0301     u16                 PartAggr:1;
0302     u16                 FirstAGGR:1;
0303     u16                 Reserved2:2;
0304 
0305     u8                  RxRate:7;
0306     u8                  RxHT:1;
0307 
0308     u8                  BW:1;
0309     u8                  SPLCP:1;
0310     u8                  Reserved3:2;
0311     u8                  PAM:1;
0312     u8                  Mcast:1;
0313     u8                  Bcast:1;
0314     u8                  Reserved4:1;
0315 
0316     /* DWORD 1 */
0317     u32                  TSFL;
0318 
0319 };
0320 
0321 /* Support till 64 bit bus width OS */
0322 #define MAX_DEV_ADDR_SIZE       8
0323 /* For RTL8190 */
0324 #define MAX_FIRMWARE_INFORMATION_SIZE   32
0325 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
0326 #define ENCRYPTION_MAX_OVERHEAD     128
0327 #define USB_HWDESC_HEADER_LEN       sizeof(struct tx_desc_819x_usb)
0328 #define TX_PACKET_SHIFT_BYTES       (USB_HWDESC_HEADER_LEN + sizeof(struct tx_fwinfo_819x_usb))
0329 #define MAX_FRAGMENT_COUNT      8
0330 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
0331 #define MAX_TRANSMIT_BUFFER_SIZE            32000
0332 #else
0333 #define MAX_TRANSMIT_BUFFER_SIZE            8000
0334 #endif
0335 /* Octets for crc32 (FCS, ICV) */
0336 #define scrclng                 4
0337 
0338 enum rf_op_type {
0339     RF_OP_By_SW_3wire = 0,
0340     RF_OP_By_FW,
0341     RF_OP_MAX
0342 };
0343 
0344 /* 8190 Loopback Mode definition */
0345 typedef enum _rtl819xUsb_loopback {
0346     RTL819xU_NO_LOOPBACK = 0,
0347     RTL819xU_MAC_LOOPBACK = 1,
0348     RTL819xU_DMA_LOOPBACK = 2,
0349     RTL819xU_CCK_LOOPBACK = 3,
0350 } rtl819xUsb_loopback_e;
0351 
0352 /* due to rtl8192 firmware */
0353 typedef enum _desc_packet_type_e {
0354     DESC_PACKET_TYPE_INIT = 0,
0355     DESC_PACKET_TYPE_NORMAL = 1,
0356 } desc_packet_type_e;
0357 
0358 typedef enum _firmware_status {
0359     FW_STATUS_0_INIT = 0,
0360     FW_STATUS_1_MOVE_BOOT_CODE = 1,
0361     FW_STATUS_2_MOVE_MAIN_CODE = 2,
0362     FW_STATUS_3_TURNON_CPU = 3,
0363     FW_STATUS_4_MOVE_DATA_CODE = 4,
0364     FW_STATUS_5_READY = 5,
0365 } firmware_status_e;
0366 
0367 typedef struct _fw_seg_container {
0368     u16 seg_size;
0369     u8  *seg_ptr;
0370 } fw_seg_container, *pfw_seg_container;
0371 typedef struct _rt_firmware {
0372     firmware_status_e firmware_status;
0373     u16               cmdpacket_frag_threshold;
0374 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
0375     u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
0376     u16               firmware_buf_size;
0377 } rt_firmware, *prt_firmware;
0378 
0379 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
0380 #define MAX_RECEIVE_BUFFER_SIZE 9100
0381 
0382 typedef struct _rt_firmware_info_819xUsb {
0383     u8      sz_info[16];
0384 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
0385 
0386 /* Firmware Queue Layout */
0387 #define NUM_OF_FIRMWARE_QUEUE       10
0388 #define NUM_OF_PAGES_IN_FW      0x100
0389 
0390 #ifdef USE_ONE_PIPE
0391 #define NUM_OF_PAGE_IN_FW_QUEUE_BE  0x000
0392 #define NUM_OF_PAGE_IN_FW_QUEUE_BK  0x000
0393 #define NUM_OF_PAGE_IN_FW_QUEUE_VI  0x0ff
0394 #define NUM_OF_PAGE_IN_FW_QUEUE_VO  0x000
0395 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
0396 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
0397 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
0398 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
0399 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0
0400 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00
0401 #else
0402 
0403 #define NUM_OF_PAGE_IN_FW_QUEUE_BE  0x020
0404 #define NUM_OF_PAGE_IN_FW_QUEUE_BK  0x020
0405 #define NUM_OF_PAGE_IN_FW_QUEUE_VI  0x040
0406 #define NUM_OF_PAGE_IN_FW_QUEUE_VO  0x040
0407 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
0408 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
0409 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
0410 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
0411 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
0412 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
0413 
0414 #endif
0415 
0416 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
0417 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
0418 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
0419 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
0420 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
0421 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
0422 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
0423 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
0424 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
0425 
0426 /*
0427  * =================================================================
0428  * =================================================================
0429  */
0430 
0431 #define EPROM_93c46 0
0432 #define EPROM_93c56 1
0433 
0434 #define DEFAULT_FRAG_THRESHOLD 2342U
0435 #define MIN_FRAG_THRESHOLD     256U
0436 #define DEFAULT_BEACONINTERVAL 0x64U
0437 #define DEFAULT_BEACON_ESSID "Rtl819xU"
0438 
0439 #define DEFAULT_SSID ""
0440 #define DEFAULT_RETRY_RTS 7
0441 #define DEFAULT_RETRY_DATA 7
0442 #define PRISM_HDR_SIZE 64
0443 
0444 #define     PHY_RSSI_SLID_WIN_MAX               100
0445 
0446 typedef enum _WIRELESS_MODE {
0447     WIRELESS_MODE_UNKNOWN = 0x00,
0448     WIRELESS_MODE_A = 0x01,
0449     WIRELESS_MODE_B = 0x02,
0450     WIRELESS_MODE_G = 0x04,
0451     WIRELESS_MODE_AUTO = 0x08,
0452     WIRELESS_MODE_N_24G = 0x10,
0453     WIRELESS_MODE_N_5G = 0x20
0454 } WIRELESS_MODE;
0455 
0456 #define RTL_IOCTL_WPA_SUPPLICANT        (SIOCIWFIRSTPRIV + 30)
0457 
0458 typedef struct buffer {
0459     struct buffer *next;
0460     u32 *buf;
0461 
0462 } buffer;
0463 
0464 typedef struct rtl_reg_debug {
0465     unsigned int  cmd;
0466     struct {
0467         unsigned char type;
0468         unsigned char addr;
0469         unsigned char page;
0470         unsigned char length;
0471     } head;
0472     unsigned char buf[0xff];
0473 } rtl_reg_debug;
0474 
0475 typedef struct _rt_9x_tx_rate_history {
0476     u32             cck[4];
0477     u32             ofdm[8];
0478     u32             ht_mcs[4][16];
0479 } rt_tx_rahis_t, *prt_tx_rahis_t;
0480 typedef struct _RT_SMOOTH_DATA_4RF {
0481     s8    elements[4][100]; /* array to store values */
0482     u32     index;            /* index to current array to store */
0483     u32     TotalNum;         /* num of valid elements */
0484     u32     TotalVal[4];      /* sum of valid elements */
0485 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
0486 
0487 /* This maybe changed for D-cut larger aggregation size */
0488 #define MAX_8192U_RX_SIZE           8192
0489 /* Stats seems messed up, clean it ASAP */
0490 typedef struct Stats {
0491     unsigned long txrdu;
0492     unsigned long rxok;
0493     unsigned long rxframgment;
0494     unsigned long rxurberr;
0495     unsigned long rxstaterr;
0496     /* 0: Total, 1: OK, 2: CRC, 3: ICV */
0497     unsigned long received_rate_histogram[4][32];
0498     /* 0: Long preamble/GI, 1: Short preamble/GI */
0499     unsigned long received_preamble_GI[2][32];
0500     /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
0501     unsigned long rx_AMPDUsize_histogram[5];
0502     /* level: (<5), (5~10), (10~20), (20~40), (>40) */
0503     unsigned long rx_AMPDUnum_histogram[5];
0504     unsigned long numpacket_matchbssid;
0505     unsigned long numpacket_toself;
0506     unsigned long num_process_phyinfo;
0507     unsigned long numqry_phystatus;
0508     unsigned long numqry_phystatusCCK;
0509     unsigned long numqry_phystatusHT;
0510     /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
0511     unsigned long received_bwtype[5];
0512     unsigned long txnperr;
0513     unsigned long txnpdrop;
0514     unsigned long txresumed;
0515     unsigned long txnpokint;
0516     unsigned long txoverflow;
0517     unsigned long txlpokint;
0518     unsigned long txlpdrop;
0519     unsigned long txlperr;
0520     unsigned long txbeokint;
0521     unsigned long txbedrop;
0522     unsigned long txbeerr;
0523     unsigned long txbkokint;
0524     unsigned long txbkdrop;
0525     unsigned long txbkerr;
0526     unsigned long txviokint;
0527     unsigned long txvidrop;
0528     unsigned long txvierr;
0529     unsigned long txvookint;
0530     unsigned long txvodrop;
0531     unsigned long txvoerr;
0532     unsigned long txbeaconokint;
0533     unsigned long txbeacondrop;
0534     unsigned long txbeaconerr;
0535     unsigned long txmanageokint;
0536     unsigned long txmanagedrop;
0537     unsigned long txmanageerr;
0538     unsigned long txdatapkt;
0539     unsigned long txfeedback;
0540     unsigned long txfeedbackok;
0541 
0542     unsigned long txoktotal;
0543     unsigned long txokbytestotal;
0544     unsigned long txokinperiod;
0545     unsigned long txmulticast;
0546     unsigned long txbytesmulticast;
0547     unsigned long txbroadcast;
0548     unsigned long txbytesbroadcast;
0549     unsigned long txunicast;
0550     unsigned long txbytesunicast;
0551 
0552     unsigned long rxoktotal;
0553     unsigned long rxbytesunicast;
0554     unsigned long txfeedbackfail;
0555     unsigned long txerrtotal;
0556     unsigned long txerrbytestotal;
0557     unsigned long txerrmulticast;
0558     unsigned long txerrbroadcast;
0559     unsigned long txerrunicast;
0560     unsigned long txretrycount;
0561     unsigned long txfeedbackretry;
0562     u8        last_packet_rate;
0563     unsigned long slide_signal_strength[100];
0564     unsigned long slide_evm[100];
0565     /* For recording sliding window's RSSI value */
0566     unsigned long slide_rssi_total;
0567     /* For recording sliding window's EVM value */
0568     unsigned long slide_evm_total;
0569     /* Transformed in dbm. Beautified signal strength for UI, not correct */
0570     long signal_strength;
0571     long signal_quality;
0572     long last_signal_strength_inpercent;
0573     /* Correct smoothed ss in dbm, only used in driver
0574      * to report real power now
0575      */
0576     long recv_signal_power;
0577     u8 rx_rssi_percentage[4];
0578     u8 rx_evm_percentage[2];
0579     long rxSNRdB[4];
0580     rt_tx_rahis_t txrate;
0581     /* For beacon RSSI */
0582     u32 Slide_Beacon_pwdb[100];
0583     u32 Slide_Beacon_Total;
0584     RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
0585 
0586     u32 CurrentShowTxate;
0587 } Stats;
0588 
0589 /* Bandwidth Offset */
0590 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE     0
0591 #define HAL_PRIME_CHNL_OFFSET_LOWER         1
0592 #define HAL_PRIME_CHNL_OFFSET_UPPER         2
0593 
0594 typedef struct  ChnlAccessSetting {
0595     u16 SIFS_Timer;
0596     u16 DIFS_Timer;
0597     u16 SlotTimeTimer;
0598     u16 EIFS_Timer;
0599     u16 CWminIndex;
0600     u16 CWmaxIndex;
0601 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
0602 
0603 typedef struct _BB_REGISTER_DEFINITION {
0604     /* set software control:        0x870~0x877 [8 bytes]  */
0605     u32 rfintfs;
0606     /* readback data:               0x8e0~0x8e7 [8 bytes]  */
0607     u32 rfintfi;
0608     /* output data:                 0x860~0x86f [16 bytes] */
0609     u32 rfintfo;
0610     /* output enable:               0x860~0x86f [16 bytes] */
0611     u32 rfintfe;
0612     /* LSSI data:                   0x840~0x84f [16 bytes] */
0613     u32 rf3wireOffset;
0614     /* BB Band Select:              0x878~0x87f [8 bytes]  */
0615     u32 rfLSSI_Select;
0616     /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
0617     u32 rfTxGainStage;
0618     /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
0619      *                              0x830~0x833, 0x838~0x83b [16 bytes]
0620      */
0621     u32 rfHSSIPara1;
0622     /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
0623      *                              0x834~0x837, 0x83c~0x83f [16 bytes]
0624      */
0625     u32 rfHSSIPara2;
0626     /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
0627     u32 rfSwitchControl;
0628     /* AGC parameter control1:  0xc50~0xc53, 0xc58~0xc5b,
0629      *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes]
0630      */
0631     u32 rfAGCControl1;
0632     /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
0633      *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
0634      */
0635     u32 rfAGCControl2;
0636     /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
0637      *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
0638      */
0639     u32 rfRxIQImbalance;
0640     /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
0641      *                              0xc10~0xc13, 0xc18~0xc1b,
0642      *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes]
0643      */
0644     u32 rfRxAFE;
0645     /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
0646      *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes]
0647      */
0648     u32 rfTxIQImbalance;
0649     /* Tx IQ DC Offset and Tx DFIR type:
0650      *                              0xc84~0xc87, 0xc8c~0xc8f,
0651      *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
0652      */
0653     u32 rfTxAFE;
0654     /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
0655     u32 rfLSSIReadBack;
0656 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
0657 
0658 typedef enum _RT_RF_TYPE_819xU {
0659     RF_TYPE_MIN = 0,
0660     RF_8225,
0661     RF_8256,
0662     RF_8258,
0663     RF_PSEUDO_11N = 4,
0664 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
0665 
0666 /* 2007/10/08 MH Define RATR state. */
0667 enum dynamic_ratr_state {
0668     DM_RATR_STA_HIGH = 0,
0669     DM_RATR_STA_MIDDLE = 1,
0670     DM_RATR_STA_LOW = 2,
0671     DM_RATR_STA_MAX
0672 };
0673 
0674 typedef struct _rate_adaptive {
0675     u8              rate_adaptive_disabled;
0676     enum dynamic_ratr_state     ratr_state;
0677     u16             reserve;
0678 
0679     u32             high_rssi_thresh_for_ra;
0680     u32             high2low_rssi_thresh_for_ra;
0681     u8              low2high_rssi_thresh_for_ra40M;
0682     u32             low_rssi_thresh_for_ra40M;
0683     u8              low2high_rssi_thresh_for_ra20M;
0684     u32             low_rssi_thresh_for_ra20M;
0685     u32             upper_rssi_threshold_ratr;
0686     u32             middle_rssi_threshold_ratr;
0687     u32             low_rssi_threshold_ratr;
0688     u32             low_rssi_threshold_ratr_40M;
0689     u32             low_rssi_threshold_ratr_20M;
0690     u8              ping_rssi_enable;
0691     u32             ping_rssi_ratr;
0692     u32             ping_rssi_thresh_for_ra;
0693     u32             last_ratr;
0694 
0695 } rate_adaptive, *prate_adaptive;
0696 
0697 #define TxBBGainTableLength 37
0698 #define CCKTxBBGainTableLength 23
0699 
0700 typedef struct _txbbgain_struct {
0701     long    txbb_iq_amplifygain;
0702     u32 txbbgain_value;
0703 } txbbgain_struct, *ptxbbgain_struct;
0704 
0705 typedef struct _ccktxbbgain_struct {
0706     /* The value is from a22 to a29, one byte one time is much safer */
0707     u8  ccktxbb_valuearray[8];
0708 } ccktxbbgain_struct, *pccktxbbgain_struct;
0709 
0710 typedef struct _init_gain {
0711     u8              xaagccore1;
0712     u8              xbagccore1;
0713     u8              xcagccore1;
0714     u8              xdagccore1;
0715     u8              cca;
0716 
0717 } init_gain, *pinit_gain;
0718 
0719 typedef struct _phy_ofdm_rx_status_report_819xusb {
0720     u8  trsw_gain_X[4];
0721     u8  pwdb_all;
0722     u8  cfosho_X[4];
0723     u8  cfotail_X[4];
0724     u8  rxevm_X[2];
0725     u8  rxsnr_X[4];
0726     u8  pdsnr_X[2];
0727     u8  csi_current_X[2];
0728     u8  csi_target_X[2];
0729     u8  sigevm;
0730     u8  max_ex_pwr;
0731     u8  sgi_en;
0732     u8  rxsc_sgien_exflg;
0733 } phy_sts_ofdm_819xusb_t;
0734 
0735 typedef struct _phy_cck_rx_status_report_819xusb {
0736     /* For CCK rate descriptor. This is an unsigned 8:1 variable.
0737      * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
0738      * Range from -64~+63.5.
0739      */
0740     u8  adc_pwdb_X[4];
0741     u8  sq_rpt;
0742     u8  cck_agc_rpt;
0743 } phy_sts_cck_819xusb_t;
0744 
0745 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
0746     u8          reserved:4;
0747     u8          rxsc:2;
0748     u8          sgi_en:1;
0749     u8          ex_intf_flag:1;
0750 };
0751 
0752 typedef enum _RT_CUSTOMER_ID {
0753     RT_CID_DEFAULT = 0,
0754     RT_CID_8187_ALPHA0 = 1,
0755     RT_CID_8187_SERCOMM_PS = 2,
0756     RT_CID_8187_HW_LED = 3,
0757     RT_CID_8187_NETGEAR = 4,
0758     RT_CID_WHQL = 5,
0759     RT_CID_819x_CAMEO  = 6,
0760     RT_CID_819x_RUNTOP = 7,
0761     RT_CID_819x_Senao = 8,
0762     RT_CID_TOSHIBA = 9,
0763     RT_CID_819x_Netcore = 10,
0764     RT_CID_Nettronix = 11,
0765     RT_CID_DLINK = 12,
0766     RT_CID_PRONET = 13,
0767 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
0768 
0769 /*
0770  * ==========================================================================
0771  * LED customization.
0772  * ==========================================================================
0773  */
0774 
0775 typedef enum _LED_STRATEGY_8190 {
0776     SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
0777     SW_LED_MODE1, /* SW control for PCI Express */
0778     SW_LED_MODE2, /* SW control for Cameo. */
0779     SW_LED_MODE3, /* SW control for RunTop. */
0780     SW_LED_MODE4, /* SW control for Netcore. */
0781     /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
0782     HW_LED,
0783 } LED_STRATEGY_8190, *PLED_STRATEGY_8190;
0784 
0785 typedef enum _RESET_TYPE {
0786     RESET_TYPE_NORESET = 0x00,
0787     RESET_TYPE_NORMAL = 0x01,
0788     RESET_TYPE_SILENT = 0x02
0789 } RESET_TYPE;
0790 
0791 /* The simple tx command OP code. */
0792 typedef enum _tag_TxCmd_Config_Index {
0793     TXCMD_TXRA_HISTORY_CTRL             = 0xFF900000,
0794     TXCMD_RESET_TX_PKT_BUFF             = 0xFF900001,
0795     TXCMD_RESET_RX_PKT_BUFF             = 0xFF900002,
0796     TXCMD_SET_TX_DURATION               = 0xFF900003,
0797     TXCMD_SET_RX_RSSI                       = 0xFF900004,
0798     TXCMD_SET_TX_PWR_TRACKING           = 0xFF900005,
0799     TXCMD_XXXX_CTRL,
0800 } DCMD_TXCMD_OP;
0801 
0802 enum version_819xu {
0803     VERSION_819XU_A, // A-cut
0804     VERSION_819XU_B, // B-cut
0805     VERSION_819XU_C,// C-cut
0806 };
0807 
0808 //added for different RF type
0809 enum rt_rf_type {
0810     RF_1T2R = 0,
0811     RF_2T4R,
0812 };
0813 
0814 typedef struct r8192_priv {
0815     struct usb_device *udev;
0816     /* For maintain info from eeprom */
0817     short epromtype;
0818     u16 eeprom_vid;
0819     u16 eeprom_pid;
0820     u8  eeprom_CustomerID;
0821     u8  eeprom_ChannelPlan;
0822     RT_CUSTOMER_ID CustomerID;
0823     LED_STRATEGY_8190   LedStrategy;
0824     u8  txqueue_to_outpipemap[9];
0825     int irq;
0826     struct ieee80211_device *ieee80211;
0827 
0828     /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
0829     short card_8192;
0830     /* If TCR reports card V B/C, this discriminates */
0831     enum version_819xu card_8192_version;
0832     short enable_gpio0;
0833     enum card_type {
0834         PCI, MINIPCI, CARDBUS, USB
0835     } card_type;
0836     short hw_plcp_len;
0837     short plcp_preamble_mode;
0838 
0839     spinlock_t irq_lock;
0840     spinlock_t tx_lock;
0841     struct mutex mutex;
0842 
0843     u16 irq_mask;
0844     short chan;
0845     short sens;
0846     short max_sens;
0847 
0848     short up;
0849     /* If 1, allow bad crc frame, reception in monitor mode */
0850     short crcmon;
0851 
0852     struct mutex wx_mutex;
0853 
0854     enum rt_rf_type   rf_type;      /* 0: 1T2R, 1: 2T4R */
0855     RT_RF_TYPE_819xU rf_chip;
0856 
0857     short (*rf_set_sens)(struct net_device *dev, short sens);
0858     u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
0859     void (*rf_close)(struct net_device *dev);
0860     void (*rf_init)(struct net_device *dev);
0861     short promisc;
0862     /* Stats */
0863     struct Stats stats;
0864     struct iw_statistics wstats;
0865 
0866     /* RX stuff */
0867     struct urb **rx_urb;
0868     struct urb **rx_cmd_urb;
0869 #ifdef THOMAS_BEACON
0870     u32 *oldaddr;
0871 #endif
0872 #ifdef THOMAS_TASKLET
0873     atomic_t irt_counter; /* count for irq_rx_tasklet */
0874 #endif
0875 #ifdef JACKSON_NEW_RX
0876     struct sk_buff **pp_rxskb;
0877     int     rx_inx;
0878 #endif
0879 
0880     struct sk_buff_head rx_queue;
0881     struct sk_buff_head skb_queue;
0882     struct work_struct qos_activate;
0883     short  tx_urb_index;
0884     atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
0885 
0886     struct tasklet_struct irq_rx_tasklet;
0887     struct urb *rxurb_task;
0888 
0889     /* Tx Related variables */
0890     u16 ShortRetryLimit;
0891     u16 LongRetryLimit;
0892     u32 TransmitConfig;
0893     u8  RegCWinMin; /* For turbo mode CW adaptive */
0894 
0895     u32     LastRxDescTSFHigh;
0896     u32     LastRxDescTSFLow;
0897 
0898     /* Rx Related variables */
0899     u16 EarlyRxThreshold;
0900     u32 ReceiveConfig;
0901     u8  AcmControl;
0902 
0903     u8  RFProgType;
0904 
0905     u8 retry_data;
0906     u8 retry_rts;
0907     u16 rts;
0908 
0909     struct  ChnlAccessSetting  ChannelAccessSetting;
0910     struct work_struct reset_wq;
0911 
0912 /**********************************************************/
0913     /* For rtl819xUsb */
0914     u16     basic_rate;
0915     u8      short_preamble;
0916     u8      slot_time;
0917     bool    bDcut;
0918     bool bCurrentRxAggrEnable;
0919     enum rf_op_type Rf_Mode;    /* For Firmware RF -R/W switch */
0920     prt_firmware        pFirmware;
0921     rtl819xUsb_loopback_e   LoopbackMode;
0922     u16 EEPROMTxPowerDiff;
0923     u8 EEPROMThermalMeter;
0924     u8 EEPROMPwDiff;
0925     u8 EEPROMCrystalCap;
0926     u8 EEPROM_Def_Ver;
0927     u8 EEPROMTxPowerLevelCCK;       /* CCK channel 1~14 */
0928     u8 EEPROMTxPowerLevelCCK_V1[3];
0929     u8 EEPROMTxPowerLevelOFDM24G[3];    /* OFDM 2.4G channel 1~14 */
0930     u8 EEPROMTxPowerLevelOFDM5G[24];    /* OFDM 5G */
0931 
0932     /* PHY related */
0933     BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
0934     /* Read/write are allow for following hardware information variables */
0935     u32 MCSTxPowerLevelOriginalOffset[6];
0936     u32 CCKTxPowerLevelOriginalOffset;
0937     u8  TxPowerLevelCCK[14];        /* CCK channel 1~14 */
0938     u8  TxPowerLevelOFDM24G[14];    /* OFDM 2.4G channel 1~14 */
0939     u8  TxPowerLevelOFDM5G[14];     /* OFDM 5G */
0940     u32 Pwr_Track;
0941     u8  TxPowerDiff;
0942     u8  AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
0943     u8  CrystalCap;
0944     u8  ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
0945 
0946     u8  CckPwEnl;
0947     /* Use to calculate PWBD */
0948     u8  bCckHighPower;
0949     long    undecorated_smoothed_pwdb;
0950 
0951     /* For set channel */
0952     u8  SwChnlInProgress;
0953     u8  SwChnlStage;
0954     u8  SwChnlStep;
0955     u8  SetBWModeInProgress;
0956     enum ht_channel_width   CurrentChannelBW;
0957     u8      ChannelPlan;
0958     /* 8190 40MHz mode */
0959     /* Control channel sub-carrier */
0960     u8  nCur40MhzPrimeSC;
0961     /* Test for shorten RF configuration time.
0962      * We save RF reg0 in this variable to reduce RF reading.
0963      */
0964     u32                 RfReg0Value[4];
0965     u8                  NumTotalRFPath;
0966     bool                brfpath_rxenable[4];
0967     /* RF set related */
0968     bool                SetRFPowerStateInProgress;
0969     struct timer_list watch_dog_timer;
0970 
0971     /* For dynamic mechanism */
0972     /* Tx Power Control for Near/Far Range */
0973     bool    bdynamic_txpower;
0974     bool    bDynamicTxHighPower;
0975     bool    bDynamicTxLowPower;
0976     bool    bLastDTPFlag_High;
0977     bool    bLastDTPFlag_Low;
0978 
0979     bool    bstore_last_dtpflag;
0980     /* Define to discriminate on High power State or
0981      * on sitesurvey to change Tx gain index
0982      */
0983     bool    bstart_txctrl_bydtp;
0984     rate_adaptive rate_adaptive;
0985     /* TX power tracking
0986      * OPEN/CLOSE TX POWER TRACKING
0987      */
0988     txbbgain_struct txbbgain_table[TxBBGainTableLength];
0989     u8      txpower_count; /* For 6 sec do tracking again */
0990     bool        btxpower_trackingInit;
0991     u8      OFDM_index;
0992     u8      CCK_index;
0993     /* CCK TX Power Tracking */
0994     ccktxbbgain_struct  cck_txbbgain_table[CCKTxBBGainTableLength];
0995     ccktxbbgain_struct  cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
0996     u8 rfa_txpowertrackingindex;
0997     u8 rfa_txpowertrackingindex_real;
0998     u8 rfa_txpowertracking_default;
0999     u8 rfc_txpowertrackingindex;
1000     u8 rfc_txpowertrackingindex_real;
1001 
1002     s8 cck_present_attenuation;
1003     u8 cck_present_attenuation_20Mdefault;
1004     u8 cck_present_attenuation_40Mdefault;
1005     s8 cck_present_attenuation_difference;
1006     bool btxpower_tracking;
1007     bool bcck_in_ch14;
1008     bool btxpowerdata_readfromEEPORM;
1009     u16 TSSI_13dBm;
1010     init_gain initgain_backup;
1011     u8 DefaultInitialGain[4];
1012     /* For EDCA Turbo mode */
1013     bool        bis_any_nonbepkts;
1014     bool        bcurrent_turbo_EDCA;
1015     bool        bis_cur_rdlstate;
1016     struct delayed_work fsync_work;
1017     bool bfsync_processing; /* 500ms Fsync timer is active or not */
1018     u32 rate_record;
1019     u32 rateCountDiffRecord;
1020     u32 ContinueDiffCount;
1021     bool bswitch_fsync;
1022 
1023     u8  framesync;
1024     u32 framesyncC34;
1025     u8  framesyncMonitor;
1026     u16 nrxAMPDU_size;
1027     u8  nrxAMPDU_aggr_num;
1028 
1029     /* For gpio */
1030     bool bHwRadioOff;
1031 
1032     u32 reset_count;
1033     bool bpbc_pressed;
1034     u32 txpower_checkcnt;
1035     u32 txpower_tracking_callback_cnt;
1036     u8 thermal_read_val[40];
1037     u8 thermal_readback_index;
1038     u32 ccktxpower_adjustcnt_not_ch14;
1039     u32 ccktxpower_adjustcnt_ch14;
1040     u8 tx_fwinfo_force_subcarriermode;
1041     u8 tx_fwinfo_force_subcarrierval;
1042     /* For silent reset */
1043     RESET_TYPE  ResetProgress;
1044     bool        bForcedSilentReset;
1045     bool        bDisableNormalResetCheck;
1046     u16     TxCounter;
1047     u16     RxCounter;
1048     int     IrpPendingCount;
1049     bool        bResetInProgress;
1050     bool        force_reset;
1051     u8      InitialGainOperateType;
1052 
1053     u16     SifsTime;
1054 
1055     /* Define work item */
1056 
1057     struct delayed_work update_beacon_wq;
1058     struct delayed_work watch_dog_wq;
1059     struct delayed_work txpower_tracking_wq;
1060     struct delayed_work rfpath_check_wq;
1061     struct delayed_work gpio_change_rf_wq;
1062     struct delayed_work initialgain_operate_wq;
1063     struct workqueue_struct *priv_wq;
1064 } r8192_priv;
1065 
1066 /* For rtl8187B */
1067 typedef enum{
1068     BULK_PRIORITY = 0x01,
1069     LOW_PRIORITY,
1070     NORM_PRIORITY,
1071     VO_PRIORITY,
1072     VI_PRIORITY,
1073     BE_PRIORITY,
1074     BK_PRIORITY,
1075     RSVD2,
1076     RSVD3,
1077     BEACON_PRIORITY,
1078     HIGH_PRIORITY,
1079     MANAGE_PRIORITY,
1080     RSVD4,
1081     RSVD5,
1082     UART_PRIORITY
1083 } priority_t;
1084 
1085 typedef enum {
1086     NIC_8192U = 1,
1087     NIC_8190P = 2,
1088     NIC_8192E = 3,
1089 } nic_t;
1090 
1091 bool init_firmware(struct net_device *dev);
1092 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1093 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1094 
1095 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1096 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1097 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1098 int read_nic_word(struct net_device *dev, int x, u16 *data);
1099 int write_nic_byte(struct net_device *dev, int x, u8 y);
1100 int write_nic_byte_E(struct net_device *dev, int x, u8 y);
1101 int write_nic_word(struct net_device *dev, int x, u16 y);
1102 int write_nic_dword(struct net_device *dev, int x, u32 y);
1103 void force_pci_posting(struct net_device *dev);
1104 
1105 void rtl8192_rtx_disable(struct net_device *dev);
1106 void rtl8192_rx_enable(struct net_device *dev);
1107 
1108 void rtl8192_update_msr(struct net_device *dev);
1109 int rtl8192_down(struct net_device *dev);
1110 int rtl8192_up(struct net_device *dev);
1111 void rtl8192_commit(struct net_device *dev);
1112 void rtl8192_set_chan(struct net_device *dev, short ch);
1113 void rtl8192_set_rxconf(struct net_device *dev);
1114 void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1115 
1116 void EnableHWSecurityConfig8192(struct net_device *dev);
1117 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType,
1118         const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1119 
1120 #endif
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