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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * This is part of the rtl8192 driver
0004  *
0005  * This files contains programming code for the rtl8256
0006  * radio frontend.
0007  *
0008  * *Many* thanks to Realtek Corp. for their great support!
0009  */
0010 
0011 #include "r8192U.h"
0012 #include "r8192U_hw.h"
0013 #include "r819xU_phyreg.h"
0014 #include "r819xU_phy.h"
0015 #include "r8190_rtl8256.h"
0016 
0017 /*
0018  * Forward declaration of local functions
0019  */
0020 static void phy_rf8256_config_para_file(struct net_device *dev);
0021 
0022 /*--------------------------------------------------------------------------
0023  * Overview:    set RF band width (20M or 40M)
0024  * Input:       struct net_device*  dev
0025  *      WIRELESS_BANDWIDTH_E    Bandwidth   //20M or 40M
0026  * Output:      NONE
0027  * Return:      NONE
0028  * Note:    8226 support both 20M  and 40 MHz
0029  *--------------------------------------------------------------------------
0030  */
0031 void phy_set_rf8256_bandwidth(struct net_device *dev, enum ht_channel_width Bandwidth)
0032 {
0033     u8  eRFPath;
0034     struct r8192_priv *priv = ieee80211_priv(dev);
0035 
0036     /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath;
0037      *  eRFPath++)
0038      */
0039     for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
0040         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
0041             continue;
0042 
0043         switch (Bandwidth) {
0044         case HT_CHANNEL_WIDTH_20:
0045                 if (priv->card_8192_version == VERSION_819XU_A ||
0046                     priv->card_8192_version == VERSION_819XU_B) {
0047                     /* 8256 D-cut, E-cut, xiong: consider it later! */
0048                     rtl8192_phy_SetRFReg(dev,
0049                         (enum rf90_radio_path_e)eRFPath,
0050                         0x0b, bMask12Bits, 0x100); /* phy para:1ba */
0051                     rtl8192_phy_SetRFReg(dev,
0052                         (enum rf90_radio_path_e)eRFPath,
0053                         0x2c, bMask12Bits, 0x3d7);
0054                     rtl8192_phy_SetRFReg(dev,
0055                         (enum rf90_radio_path_e)eRFPath,
0056                         0x0e, bMask12Bits, 0x021);
0057                     rtl8192_phy_SetRFReg(dev,
0058                         (enum rf90_radio_path_e)eRFPath,
0059                         0x14, bMask12Bits, 0x5ab);
0060                 } else {
0061                     RT_TRACE(COMP_ERR, "%s(): unknown hardware version\n", __func__);
0062                     }
0063                 break;
0064         case HT_CHANNEL_WIDTH_20_40:
0065                 if (priv->card_8192_version == VERSION_819XU_A || priv->card_8192_version == VERSION_819XU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
0066                     rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */
0067                     rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x2c, bMask12Bits, 0x3df);
0068                     rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0e, bMask12Bits, 0x0a1);
0069 
0070                     if (priv->chan == 3 || priv->chan == 9)
0071                         /* I need to set priv->chan whenever current channel changes */
0072                         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x14, bMask12Bits, 0x59b);
0073                     else
0074                         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x14, bMask12Bits, 0x5ab);
0075                 } else {
0076                     RT_TRACE(COMP_ERR, "%s(): unknown hardware version\n", __func__);
0077                     }
0078                 break;
0079         default:
0080                 RT_TRACE(COMP_ERR, "%s(): unknown Bandwidth: %#X\n", __func__, Bandwidth);
0081                 break;
0082         }
0083     }
0084 }
0085 
0086 /*--------------------------------------------------------------------------
0087  * Overview:    Interface to config 8256
0088  * Input:       struct net_device*  dev
0089  * Output:      NONE
0090  * Return:      NONE
0091  *--------------------------------------------------------------------------
0092  */
0093 void phy_rf8256_config(struct net_device *dev)
0094 {
0095     struct r8192_priv *priv = ieee80211_priv(dev);
0096     /* Initialize general global value
0097      *
0098      * TODO: Extend RF_PATH_C and RF_PATH_D in the future
0099      */
0100     priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
0101     /* Config BB and RF */
0102     phy_rf8256_config_para_file(dev);
0103 }
0104 
0105 /*--------------------------------------------------------------------------
0106  * Overview:    Interface to config 8256
0107  * Input:       struct net_device*  dev
0108  * Output:      NONE
0109  * Return:      NONE
0110  *--------------------------------------------------------------------------
0111  */
0112 static void phy_rf8256_config_para_file(struct net_device *dev)
0113 {
0114     u32 u4RegValue = 0;
0115     u8  eRFPath;
0116     BB_REGISTER_DEFINITION_T    *pPhyReg;
0117     struct r8192_priv *priv = ieee80211_priv(dev);
0118     u32 RegOffSetToBeCheck = 0x3;
0119     u32 RegValueToBeCheck = 0x7f1;
0120     u32 RF3_Final_Value = 0;
0121     u8  ConstRetryTimes = 5, RetryTimes = 5;
0122     u8 ret = 0;
0123     /* Initialize RF */
0124     for (eRFPath = (enum rf90_radio_path_e)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
0125         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
0126             continue;
0127 
0128         pPhyReg = &priv->PHYRegDef[eRFPath];
0129 
0130         /* Joseph test for shorten RF config
0131          * pHalData->RfReg0Value[eRFPath] =  rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, rGlobalCtrl, bMaskDWord);
0132          * ----Store original RFENV control type
0133          */
0134         switch (eRFPath) {
0135         case RF90_PATH_A:
0136         case RF90_PATH_C:
0137             u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
0138             break;
0139         case RF90_PATH_B:
0140         case RF90_PATH_D:
0141             u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV << 16);
0142             break;
0143         }
0144 
0145         /*----Set RF_ENV enable----*/
0146         rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
0147 
0148         /*----Set RF_ENV output high----*/
0149         rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
0150 
0151         /* Set bit number of Address and Data for RF register */
0152         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
0153         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
0154 
0155         rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path_e)eRFPath, 0x0, bMask12Bits, 0xbf);
0156 
0157         /* Check RF block (for FPGA platform only)----
0158          * TODO: this function should be removed on ASIC , Emily 2007.2.2
0159          */
0160         if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path_e)eRFPath)) {
0161             RT_TRACE(COMP_ERR, "phy_rf8256_config():Check Radio[%d] Fail!!\n", eRFPath);
0162             goto phy_RF8256_Config_ParaFile_Fail;
0163         }
0164 
0165         RetryTimes = ConstRetryTimes;
0166         RF3_Final_Value = 0;
0167         /*----Initialize RF fom connfiguration file----*/
0168         switch (eRFPath) {
0169         case RF90_PATH_A:
0170             while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
0171                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
0172                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
0173                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
0174                 RetryTimes--;
0175             }
0176             break;
0177         case RF90_PATH_B:
0178             while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
0179                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
0180                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
0181                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
0182                 RetryTimes--;
0183             }
0184             break;
0185         case RF90_PATH_C:
0186             while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
0187                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
0188                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
0189                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
0190                 RetryTimes--;
0191             }
0192             break;
0193         case RF90_PATH_D:
0194             while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
0195                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path_e)eRFPath);
0196                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path_e)eRFPath, RegOffSetToBeCheck, bMask12Bits);
0197                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
0198                 RetryTimes--;
0199             }
0200             break;
0201         }
0202 
0203         /*----Restore RFENV control type----*/
0204         switch (eRFPath) {
0205         case RF90_PATH_A:
0206         case RF90_PATH_C:
0207             rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
0208             break;
0209         case RF90_PATH_B:
0210         case RF90_PATH_D:
0211             rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
0212             break;
0213         }
0214 
0215         if (ret) {
0216             RT_TRACE(COMP_ERR, "%s():Radio[%d] Fail!!", __func__, eRFPath);
0217             goto phy_RF8256_Config_ParaFile_Fail;
0218         }
0219     }
0220 
0221     RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
0222     return;
0223 
0224 phy_RF8256_Config_ParaFile_Fail:
0225     RT_TRACE(COMP_ERR, "PHY Initialization failed\n");
0226 }
0227 
0228 void phy_set_rf8256_cck_tx_power(struct net_device *dev, u8 powerlevel)
0229 {
0230     u32 TxAGC = 0;
0231     struct r8192_priv *priv = ieee80211_priv(dev);
0232 
0233     TxAGC = powerlevel;
0234 
0235     if (priv->bDynamicTxLowPower) {
0236         if (priv->CustomerID == RT_CID_819x_Netcore)
0237             TxAGC = 0x22;
0238         else
0239             TxAGC += priv->CckPwEnl;
0240     }
0241 
0242     if (TxAGC > 0x24)
0243         TxAGC = 0x24;
0244     rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
0245 }
0246 
0247 void phy_set_rf8256_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
0248 {
0249     struct r8192_priv *priv = ieee80211_priv(dev);
0250     /* Joseph TxPower for 8192 testing */
0251     u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
0252     u8 index = 0;
0253     u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
0254     u8 byte0, byte1, byte2, byte3;
0255 
0256     powerBase0 = powerlevel + priv->TxPowerDiff;    /* OFDM rates */
0257     powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0;
0258     powerBase1 = powerlevel;                            /* MCS rates */
0259     powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
0260 
0261     for (index = 0; index < 6; index++) {
0262         writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2) ? powerBase0 : powerBase1);
0263         byte0 = (u8)(writeVal & 0x7f);
0264         byte1 = (u8)((writeVal & 0x7f00) >> 8);
0265         byte2 = (u8)((writeVal & 0x7f0000) >> 16);
0266         byte3 = (u8)((writeVal & 0x7f000000) >> 24);
0267 
0268         if (byte0 > 0x24)
0269             /* Max power index = 0x24 */
0270             byte0 = 0x24;
0271         if (byte1 > 0x24)
0272             byte1 = 0x24;
0273         if (byte2 > 0x24)
0274             byte2 = 0x24;
0275         if (byte3 > 0x24)
0276             byte3 = 0x24;
0277 
0278         /* for tx power track */
0279         if (index == 3) {
0280             writeVal_tmp = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
0281             priv->Pwr_Track = writeVal_tmp;
0282         }
0283 
0284         if (priv->bDynamicTxHighPower) {
0285             /*Add by Jacken 2008/03/06
0286              *Emily, 20080613. Set low tx power for both MCS and legacy OFDM
0287              */
0288             writeVal = 0x03030303;
0289         } else {
0290             writeVal = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
0291         }
0292         rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
0293     }
0294 }
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