staging/rtl8192u/r8180_93cx6.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  This files contains card eeprom (93c46 or 93c56) programming routines,
0004  *  memory is addressed by 16 bits words.
0005  *
0006  *  This is part of rtl8180 OpenSource driver.
0007  *  Copyright (C) Andrea Merello 2004  <andrea.merello@gmail.com>
0008  *
0009  *  Parts of this driver are based on the GPL part of the
0010  *  official realtek driver.
0011  *
0012  *  Parts of this driver are based on the rtl8180 driver skeleton
0013  *  from Patric Schenke & Andres Salomon.
0014  *
0015  *  Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
0016  *
0017  *  We want to thank the Authors of those projects and the Ndiswrapper
0018  *  project Authors.
0019  */
0020
0021 #include "r8180_93cx6.h"
0022
0023 static void eprom_cs(struct net_device *dev, short bit)
0024 {
0025     u8 cmdreg;
0026     int err;
0027
0028     err = read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
0029     if (err)
0030         return;
0031     if (bit)
0032         /* enable EPROM */
0033         write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CS_BIT);
0034     else
0035         /* disable EPROM */
0036         write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CS_BIT);
0037
0038     force_pci_posting(dev);
0039     udelay(EPROM_DELAY);
0040 }
0041
0042 static void eprom_ck_cycle(struct net_device *dev)
0043 {
0044     u8 cmdreg;
0045     int err;
0046
0047     err = read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
0048     if (err)
0049         return;
0050     write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CK_BIT);
0051     force_pci_posting(dev);
0052     udelay(EPROM_DELAY);
0053
0054     read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
0055     write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CK_BIT);
0056     force_pci_posting(dev);
0057     udelay(EPROM_DELAY);
0058 }
0059
0060 static void eprom_w(struct net_device *dev, short bit)
0061 {
0062     u8 cmdreg;
0063     int err;
0064
0065     err = read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
0066     if (err)
0067         return;
0068     if (bit)
0069         write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_W_BIT);
0070     else
0071         write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_W_BIT);
0072
0073     force_pci_posting(dev);
0074     udelay(EPROM_DELAY);
0075 }
0076
0077 static short eprom_r(struct net_device *dev)
0078 {
0079     u8 bit;
0080     int err;
0081
0082     err = read_nic_byte_E(dev, EPROM_CMD, &bit);
0083     if (err)
0084         return err;
0085
0086     udelay(EPROM_DELAY);
0087
0088     if (bit & EPROM_R_BIT)
0089         return 1;
0090
0091     return 0;
0092 }
0093
0094 static void eprom_send_bits_string(struct net_device *dev, short b[], int len)
0095 {
0096     int i;
0097
0098     for (i = 0; i < len; i++) {
0099         eprom_w(dev, b[i]);
0100         eprom_ck_cycle(dev);
0101     }
0102 }
0103
0104 int eprom_read(struct net_device *dev, u32 addr)
0105 {
0106     struct r8192_priv *priv = ieee80211_priv(dev);
0107     short read_cmd[] = {1, 1, 0};
0108     short addr_str[8];
0109     int i;
0110     int addr_len;
0111     u32 ret;
0112     int err;
0113
0114     ret = 0;
0115     /* enable EPROM programming */
0116     write_nic_byte_E(dev, EPROM_CMD,
0117                (EPROM_CMD_PROGRAM << EPROM_CMD_OPERATING_MODE_SHIFT));
0118     force_pci_posting(dev);
0119     udelay(EPROM_DELAY);
0120
0121     if (priv->epromtype == EPROM_93c56) {
0122         addr_str[7] = addr & 1;
0123         addr_str[6] = addr & BIT(1);
0124         addr_str[5] = addr & BIT(2);
0125         addr_str[4] = addr & BIT(3);
0126         addr_str[3] = addr & BIT(4);
0127         addr_str[2] = addr & BIT(5);
0128         addr_str[1] = addr & BIT(6);
0129         addr_str[0] = addr & BIT(7);
0130         addr_len = 8;
0131     } else {
0132         addr_str[5] = addr & 1;
0133         addr_str[4] = addr & BIT(1);
0134         addr_str[3] = addr & BIT(2);
0135         addr_str[2] = addr & BIT(3);
0136         addr_str[1] = addr & BIT(4);
0137         addr_str[0] = addr & BIT(5);
0138         addr_len = 6;
0139     }
0140     eprom_cs(dev, 1);
0141     eprom_ck_cycle(dev);
0142     eprom_send_bits_string(dev, read_cmd, 3);
0143     eprom_send_bits_string(dev, addr_str, addr_len);
0144
0145     /*
0146      * keep chip pin D to low state while reading.
0147      * I'm unsure if it is necessary, but anyway shouldn't hurt
0148      */
0149     eprom_w(dev, 0);
0150
0151     for (i = 0; i < 16; i++) {
0152         /* eeprom needs a clk cycle between writing opcode&adr
0153          * and reading data. (eeprom outs a dummy 0)
0154          */
0155         eprom_ck_cycle(dev);
0156         err = eprom_r(dev);
0157         if (err < 0)
0158             return err;
0159
0160         ret |= err << (15 - i);
0161     }
0162
0163     eprom_cs(dev, 0);
0164     eprom_ck_cycle(dev);
0165
0166     /* disable EPROM programming */
0167     write_nic_byte_E(dev, EPROM_CMD,
0168                (EPROM_CMD_NORMAL << EPROM_CMD_OPERATING_MODE_SHIFT));
0169     return ret;
0170 }