OSCL-LXR |
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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 0002 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 0003 0004 #ifndef __INC_HAL8188EPHYCFG_H__ 0005 #define __INC_HAL8188EPHYCFG_H__ 0006 0007 #define MAX_AGGR_NUM 0x07 0008 0009 enum rf_radio_path { 0010 RF_PATH_A = 0, /* Radio Path A */ 0011 RF_PATH_B = 1, /* Radio Path B */ 0012 }; 0013 0014 #define MAX_PG_GROUP 13 0015 0016 #define RF_PATH_MAX 3 0017 #define MAX_TX_COUNT 4 /* path numbers */ 0018 0019 #define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */ 0020 #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8, 0021 *ch9~11, ch12~13, CH 14 0022 * total three groups */ 0023 0024 struct bb_reg_def { 0025 u32 rfintfs; /* set software control: */ 0026 /* 0x870~0x877[8 bytes] */ 0027 u32 rfintfi; /* readback data: */ 0028 /* 0x8e0~0x8e7[8 bytes] */ 0029 u32 rfintfo; /* output data: */ 0030 /* 0x860~0x86f [16 bytes] */ 0031 u32 rfintfe; /* output enable: */ 0032 /* 0x860~0x86f [16 bytes] */ 0033 u32 rf3wireOffset; /* LSSI data: */ 0034 /* 0x840~0x84f [16 bytes] */ 0035 u32 rfLSSI_Select; /* BB Band Select: */ 0036 /* 0x878~0x87f [8 bytes] */ 0037 u32 rfTxGainStage; /* Tx gain stage: */ 0038 /* 0x80c~0x80f [4 bytes] */ 0039 u32 rfHSSIPara1; /* wire parameter control1 : */ 0040 /* 0x820~0x823,0x828~0x82b, 0041 * 0x830~0x833, 0x838~0x83b [16 bytes] */ 0042 u32 rfHSSIPara2; /* wire parameter control2 : */ 0043 /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0044 * 0x83c~0x83f [16 bytes] */ 0045 u32 rfSwitchControl; /* Tx Rx antenna control : */ 0046 /* 0x858~0x85f [16 bytes] */ 0047 u32 rfAGCControl1; /* AGC parameter control1 : */ 0048 /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0049 * 0xc68~0xc6b [16 bytes] */ 0050 u32 rfAGCControl2; /* AGC parameter control2 : */ 0051 /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0052 * 0xc6c~0xc6f [16 bytes] */ 0053 u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */ 0054 /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0055 * 0xc2c~0xc2f [16 bytes] */ 0056 u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, 0057 * Rx DC notch filter : */ 0058 /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0059 * 0xc28~0xc2b [16 bytes] */ 0060 u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */ 0061 /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0062 * 0xc98~0xc9b [16 bytes] */ 0063 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */ 0064 /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0065 * 0xc9c~0xc9f [16 bytes] */ 0066 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ 0067 /* 0x8a0~0x8af [16 bytes] */ 0068 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for 0069 * Path A and B */ 0070 }; 0071 0072 /* BB and RF register read/write */ 0073 u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask); 0074 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, 0075 u32 mask, u32 data); 0076 u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, u32 regaddr, u32 mask); 0077 void rtl8188e_PHY_SetRFReg(struct adapter *adapter, u32 regaddr, u32 mask, u32 data); 0078 0079 /* Initialization related function */ 0080 /* MAC/BB/RF HAL config */ 0081 int PHY_MACConfig8188E(struct adapter *adapter); 0082 int PHY_BBConfig8188E(struct adapter *adapter); 0083 int PHY_RFConfig8188E(struct adapter *adapter); 0084 0085 /* BB TX Power R/W */ 0086 void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel); 0087 0088 /* Switch bandwidth for 8192S */ 0089 void PHY_SetBWMode8188E(struct adapter *adapter, 0090 enum ht_channel_width chnlwidth, unsigned char offset); 0091 0092 /* channel switch related funciton */ 0093 void PHY_SwChnl8188E(struct adapter *adapter, u8 channel); 0094 0095 void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr, 0096 u32 mask, u32 data); 0097 0098 #endif
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