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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c) Realtek Semiconductor Corp. */
0003 
0004 #include "../include/drv_types.h"
0005 
0006 static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE + 1] = {
0007         {5, 4, 3, 2, 0, 3},      /* 92 , idx = 0 */
0008         {6, 5, 4, 3, 0, 4},      /* 86 , idx = 1 */
0009         {6, 5, 4, 2, 0, 4},      /* 81 , idx = 2 */
0010         {8, 7, 6, 4, 0, 6},      /* 75 , idx = 3 */
0011         {10, 9, 8, 6, 0, 8},     /* 71  , idx = 4 */
0012         {10, 9, 8, 4, 0, 8},     /* 66  , idx = 5 */
0013         {10, 9, 8, 2, 0, 8},     /* 62  , idx = 6 */
0014         {10, 9, 8, 0, 0, 8},     /* 59  , idx = 7 */
0015         {18, 17, 16, 8, 0, 16},  /* 53 , idx = 8 */
0016         {26, 25, 24, 16, 0, 24}, /* 50  , idx = 9 */
0017         {34, 33, 32, 24, 0, 32}, /* 47  , idx = 0x0a */
0018         {34, 31, 28, 20, 0, 32}, /* 43  , idx = 0x0b */
0019         {34, 31, 27, 18, 0, 32}, /* 40 , idx = 0x0c */
0020         {34, 31, 26, 16, 0, 32}, /* 37 , idx = 0x0d */
0021         {34, 30, 22, 16, 0, 32}, /* 32 , idx = 0x0e */
0022         {34, 30, 24, 16, 0, 32}, /* 26 , idx = 0x0f */
0023         {49, 46, 40, 16, 0, 48}, /* 20  , idx = 0x10 */
0024         {49, 45, 32, 0, 0, 48},  /* 17 , idx = 0x11 */
0025         {49, 45, 22, 18, 0, 48}, /* 15  , idx = 0x12 */
0026         {49, 40, 24, 16, 0, 48}, /* 12  , idx = 0x13 */
0027         {49, 32, 18, 12, 0, 48}, /* 9 , idx = 0x14 */
0028         {49, 22, 18, 14, 0, 48}, /* 6 , idx = 0x15 */
0029         {49, 16, 16, 0, 0, 48}
0030     }; /* 3, idx = 0x16 */
0031 
0032 static u8 PT_PENALTY[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32};
0033 
0034 /*  wilson modify */
0035 static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {
0036         {4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a,        /*  SS>TH */
0037         4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,
0038         5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f},              /*  0329 R01 */
0039         {0x0a, 0x0a, 0x0b, 0x0c, 0x0a,
0040         0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14,      /*  SS<TH */
0041         0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x15,
0042         9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13}
0043     };
0044 
0045 static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {
0046         0x0c, 0x0d, 0x0d, 0x0f, 0x0d, 0x0e,
0047         0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14,        /*  SS>TH */
0048         0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15,
0049         0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15};
0050 
0051 static u8 RSSI_THRESHOLD[RATESIZE] = {
0052         0, 0, 0, 0,
0053         0, 0, 0, 0, 0, 0x24, 0x26, 0x2a,
0054         0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a,
0055         0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c};
0056 
0057 static u16 N_THRESHOLD_HIGH[RATESIZE] = {
0058         4, 4, 8, 16,
0059         24, 36, 48, 72, 96, 144, 192, 216,
0060         60, 80, 100, 160, 240, 400, 560, 640,
0061         300, 320, 480, 720, 1000, 1200, 1600, 2000};
0062 static u16 N_THRESHOLD_LOW[RATESIZE] = {
0063         2, 2, 4, 8,
0064         12, 18, 24, 36, 48, 72, 96, 108,
0065         30, 40, 50, 80, 120, 200, 280, 320,
0066         150, 160, 240, 360, 500, 600, 800, 1000};
0067 
0068 static u8 DROPING_NECESSARY[RATESIZE] = {
0069         1, 1, 1, 1,
0070         1, 2, 3, 4, 5, 6, 7, 8,
0071         1, 2, 3, 4, 5, 6, 7, 8,
0072         5, 6, 7, 8, 9, 10, 11, 12};
0073 
0074 static u8 PendingForRateUpFail[5] = {2, 10, 24, 40, 60};
0075 static u16 DynamicTxRPTTiming[6] = {
0076     0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /*  200ms-1200ms */
0077 
0078 /*  End Rate adaptive parameters */
0079 
0080 static void odm_SetTxRPTTiming_8188E(
0081         struct odm_dm_struct *dm_odm,
0082         struct odm_ra_info *pRaInfo,
0083         u8 extend
0084     )
0085 {
0086     u8 idx = 0;
0087 
0088     for (idx = 0; idx < 5; idx++)
0089         if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
0090             break;
0091 
0092     if (extend == 0) { /*  back to default timing */
0093         idx = 0;  /* 200ms */
0094     } else if (extend == 1) {/*  increase the timing */
0095         idx += 1;
0096         if (idx > 5)
0097             idx = 5;
0098     } else if (extend == 2) {/*  decrease the timing */
0099         if (idx != 0)
0100             idx -= 1;
0101     }
0102     pRaInfo->RptTime = DynamicTxRPTTiming[idx];
0103 }
0104 
0105 static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo)
0106 {
0107     u8 RateID, LowestRate, HighestRate;
0108     u8 i;
0109 
0110     if (NULL == pRaInfo)
0111         return -1;
0112     RateID = pRaInfo->PreRate;
0113     LowestRate = pRaInfo->LowestRate;
0114     HighestRate = pRaInfo->HighestRate;
0115 
0116     if (RateID > HighestRate) {
0117         RateID = HighestRate;
0118     } else if (pRaInfo->RateSGI) {
0119         pRaInfo->RateSGI = 0;
0120     } else if (RateID > LowestRate) {
0121         if (RateID > 0) {
0122             for (i = RateID - 1; i > LowestRate; i--) {
0123                 if (pRaInfo->RAUseRate & BIT(i)) {
0124                     RateID = i;
0125                     goto RateDownFinish;
0126                 }
0127             }
0128         }
0129     } else if (RateID <= LowestRate) {
0130         RateID = LowestRate;
0131     }
0132 RateDownFinish:
0133     if (pRaInfo->RAWaitingCounter == 1) {
0134         pRaInfo->RAWaitingCounter += 1;
0135         pRaInfo->RAPendingCounter += 1;
0136     } else if (pRaInfo->RAWaitingCounter == 0) {
0137         ;
0138     } else {
0139         pRaInfo->RAWaitingCounter = 0;
0140         pRaInfo->RAPendingCounter = 0;
0141     }
0142 
0143     if (pRaInfo->RAPendingCounter >= 4)
0144         pRaInfo->RAPendingCounter = 4;
0145 
0146     pRaInfo->DecisionRate = RateID;
0147     odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 2);
0148     return 0;
0149 }
0150 
0151 static int odm_RateUp_8188E(
0152         struct odm_dm_struct *dm_odm,
0153         struct odm_ra_info *pRaInfo
0154     )
0155 {
0156     u8 RateID, HighestRate;
0157     u8 i;
0158 
0159     if (NULL == pRaInfo)
0160         return -1;
0161     RateID = pRaInfo->PreRate;
0162     HighestRate = pRaInfo->HighestRate;
0163     if (pRaInfo->RAWaitingCounter == 1) {
0164         pRaInfo->RAWaitingCounter = 0;
0165         pRaInfo->RAPendingCounter = 0;
0166     } else if (pRaInfo->RAWaitingCounter > 1) {
0167         pRaInfo->PreRssiStaRA = pRaInfo->RssiStaRA;
0168         goto RateUpfinish;
0169     }
0170     odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 0);
0171 
0172     if (RateID < HighestRate) {
0173         for (i = RateID + 1; i <= HighestRate; i++) {
0174             if (pRaInfo->RAUseRate & BIT(i)) {
0175                 RateID = i;
0176                 goto RateUpfinish;
0177             }
0178         }
0179     } else if (RateID == HighestRate) {
0180         if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1))
0181             pRaInfo->RateSGI = 1;
0182         else if ((pRaInfo->SGIEnable) != 1)
0183             pRaInfo->RateSGI = 0;
0184     } else {
0185         RateID = HighestRate;
0186     }
0187 RateUpfinish:
0188     if (pRaInfo->RAWaitingCounter == (4 + PendingForRateUpFail[pRaInfo->RAPendingCounter]))
0189         pRaInfo->RAWaitingCounter = 0;
0190     else
0191         pRaInfo->RAWaitingCounter++;
0192 
0193     pRaInfo->DecisionRate = RateID;
0194     return 0;
0195 }
0196 
0197 static void odm_ResetRaCounter_8188E(struct odm_ra_info *pRaInfo)
0198 {
0199     u8 RateID;
0200 
0201     RateID = pRaInfo->DecisionRate;
0202     pRaInfo->NscUp = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1;
0203     pRaInfo->NscDown = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1;
0204 }
0205 
0206 static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm,
0207         struct odm_ra_info *pRaInfo
0208     )
0209 {
0210     u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
0211     /* u32 pool_retry; */
0212     static u8 DynamicTxRPTTimingCounter;
0213 
0214     if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) { /*  STA used and data packet exits */
0215         if ((pRaInfo->RssiStaRA < (pRaInfo->PreRssiStaRA - 3)) ||
0216             (pRaInfo->RssiStaRA > (pRaInfo->PreRssiStaRA + 3))) {
0217             pRaInfo->RAWaitingCounter = 0;
0218             pRaInfo->RAPendingCounter = 0;
0219         }
0220         /*  Start RA decision */
0221         if (pRaInfo->PreRate > pRaInfo->HighestRate)
0222             RateID = pRaInfo->HighestRate;
0223         else
0224             RateID = pRaInfo->PreRate;
0225         if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID])
0226             RtyPtID = 0;
0227         else
0228             RtyPtID = 1;
0229         PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */
0230 
0231         pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0];
0232         pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1];
0233         pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2];
0234         pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3];
0235         pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4];
0236         if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))
0237             pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5];
0238         else
0239             pRaInfo->NscDown = 0;
0240 
0241         /*  rate up */
0242         PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID];
0243         pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0];
0244         pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1];
0245         pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2];
0246         pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3];
0247         pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4];
0248         if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))
0249             pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5];
0250         else
0251             pRaInfo->NscUp = 0;
0252 
0253         if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||
0254             (pRaInfo->DROP > DROPING_NECESSARY[RateID]))
0255             odm_RateDown_8188E(dm_odm, pRaInfo);
0256         else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])
0257             odm_RateUp_8188E(dm_odm, pRaInfo);
0258 
0259         if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
0260             pRaInfo->DecisionRate = pRaInfo->HighestRate;
0261 
0262         if ((pRaInfo->DecisionRate) == (pRaInfo->PreRate))
0263             DynamicTxRPTTimingCounter += 1;
0264         else
0265             DynamicTxRPTTimingCounter = 0;
0266 
0267         if (DynamicTxRPTTimingCounter >= 4) {
0268             odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 1);
0269             DynamicTxRPTTimingCounter = 0;
0270         }
0271 
0272         pRaInfo->PreRate = pRaInfo->DecisionRate;  /* YJ, add, 120120 */
0273 
0274         odm_ResetRaCounter_8188E(pRaInfo);
0275     }
0276 }
0277 
0278 static int odm_ARFBRefresh_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo)
0279 {  /*  Wilson 2011/10/26 */
0280     u32 MaskFromReg;
0281     s8 i;
0282     int res;
0283 
0284     switch (pRaInfo->RateID) {
0285     case RATR_INX_WIRELESS_NGB:
0286         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff015;
0287         break;
0288     case RATR_INX_WIRELESS_NG:
0289         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff010;
0290         break;
0291     case RATR_INX_WIRELESS_NB:
0292         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff005;
0293         break;
0294     case RATR_INX_WIRELESS_N:
0295         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff000;
0296         break;
0297     case RATR_INX_WIRELESS_GB:
0298         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff5;
0299         break;
0300     case RATR_INX_WIRELESS_G:
0301         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff0;
0302         break;
0303     case RATR_INX_WIRELESS_B:
0304         pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0000000d;
0305         break;
0306     case 12:
0307         res = rtw_read32(dm_odm->Adapter, REG_ARFR0, &MaskFromReg);
0308         if (res)
0309             return res;
0310 
0311         pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
0312         break;
0313     case 13:
0314         res = rtw_read32(dm_odm->Adapter, REG_ARFR1, &MaskFromReg);
0315         if (res)
0316             return res;
0317 
0318         pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
0319         break;
0320     case 14:
0321         res = rtw_read32(dm_odm->Adapter, REG_ARFR2, &MaskFromReg);
0322         if (res)
0323             return res;
0324 
0325         pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
0326         break;
0327     case 15:
0328         res = rtw_read32(dm_odm->Adapter, REG_ARFR3, &MaskFromReg);
0329         if (res)
0330             return res;
0331 
0332         pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
0333         break;
0334     default:
0335         pRaInfo->RAUseRate = (pRaInfo->RateMask);
0336         break;
0337     }
0338     /*  Highest rate */
0339     if (pRaInfo->RAUseRate) {
0340         for (i = RATESIZE; i >= 0; i--) {
0341             if ((pRaInfo->RAUseRate) & BIT(i)) {
0342                 pRaInfo->HighestRate = i;
0343                 break;
0344             }
0345         }
0346     } else {
0347         pRaInfo->HighestRate = 0;
0348     }
0349     /*  Lowest rate */
0350     if (pRaInfo->RAUseRate) {
0351         for (i = 0; i < RATESIZE; i++) {
0352             if ((pRaInfo->RAUseRate) & BIT(i)) {
0353                 pRaInfo->LowestRate = i;
0354                 break;
0355             }
0356         }
0357     } else {
0358         pRaInfo->LowestRate = 0;
0359     }
0360     if (pRaInfo->HighestRate > 0x13)
0361         pRaInfo->PTModeSS = 3;
0362     else if (pRaInfo->HighestRate > 0x0b)
0363         pRaInfo->PTModeSS = 2;
0364     else if (pRaInfo->HighestRate > 0x03)
0365         pRaInfo->PTModeSS = 1;
0366     else
0367         pRaInfo->PTModeSS = 0;
0368 
0369     if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
0370         pRaInfo->DecisionRate = pRaInfo->HighestRate;
0371 
0372     return 0;
0373 }
0374 
0375 static void odm_PTTryState_8188E(struct odm_ra_info *pRaInfo)
0376 {
0377     pRaInfo->PTTryState = 0;
0378     switch (pRaInfo->PTModeSS) {
0379     case 3:
0380         if (pRaInfo->DecisionRate >= 0x19)
0381             pRaInfo->PTTryState = 1;
0382         break;
0383     case 2:
0384         if (pRaInfo->DecisionRate >= 0x11)
0385             pRaInfo->PTTryState = 1;
0386         break;
0387     case 1:
0388         if (pRaInfo->DecisionRate >= 0x0a)
0389             pRaInfo->PTTryState = 1;
0390         break;
0391     case 0:
0392         if (pRaInfo->DecisionRate >= 0x03)
0393             pRaInfo->PTTryState = 1;
0394         break;
0395     default:
0396         pRaInfo->PTTryState = 0;
0397         break;
0398     }
0399 
0400     if (pRaInfo->RssiStaRA < 48) {
0401         pRaInfo->PTStage = 0;
0402     } else if (pRaInfo->PTTryState == 1) {
0403         if ((pRaInfo->PTStopCount >= 10) ||
0404             (pRaInfo->PTPreRssi > pRaInfo->RssiStaRA + 5) ||
0405             (pRaInfo->PTPreRssi < pRaInfo->RssiStaRA - 5) ||
0406             (pRaInfo->DecisionRate != pRaInfo->PTPreRate)) {
0407             if (pRaInfo->PTStage == 0)
0408                 pRaInfo->PTStage = 1;
0409             else if (pRaInfo->PTStage == 1)
0410                 pRaInfo->PTStage = 3;
0411             else
0412                 pRaInfo->PTStage = 5;
0413 
0414             pRaInfo->PTPreRssi = pRaInfo->RssiStaRA;
0415             pRaInfo->PTStopCount = 0;
0416         } else {
0417             pRaInfo->RAstage = 0;
0418             pRaInfo->PTStopCount++;
0419         }
0420     } else {
0421         pRaInfo->PTStage = 0;
0422         pRaInfo->RAstage = 0;
0423     }
0424     pRaInfo->PTPreRate = pRaInfo->DecisionRate;
0425 }
0426 
0427 static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo)
0428 {
0429     u8 j;
0430     u8 temp_stage;
0431     u32 numsc;
0432     u32 num_total;
0433     u8 stage_id;
0434 
0435     numsc  = 0;
0436     num_total = pRaInfo->TOTAL * PT_PENALTY[5];
0437     for (j = 0; j <= 4; j++) {
0438         numsc += pRaInfo->RTY[j] * PT_PENALTY[j];
0439         if (numsc > num_total)
0440             break;
0441     }
0442 
0443     j = j >> 1;
0444     temp_stage = (pRaInfo->PTStage + 1) >> 1;
0445     if (temp_stage > j)
0446         stage_id = temp_stage - j;
0447     else
0448         stage_id = 0;
0449 
0450     pRaInfo->PTSmoothFactor = (pRaInfo->PTSmoothFactor >> 1) + (pRaInfo->PTSmoothFactor >> 2) + stage_id * 16 + 2;
0451     if (pRaInfo->PTSmoothFactor > 192)
0452         pRaInfo->PTSmoothFactor = 192;
0453     stage_id = pRaInfo->PTSmoothFactor >> 6;
0454     temp_stage = stage_id * 2;
0455     if (temp_stage != 0)
0456         temp_stage -= 1;
0457     if (pRaInfo->DROP > 3)
0458         temp_stage = 0;
0459     pRaInfo->PTStage = temp_stage;
0460 }
0461 
0462 static void
0463 odm_RATxRPTTimerSetting(
0464         struct odm_dm_struct *dm_odm,
0465         u16 minRptTime
0466 )
0467 {
0468     if (dm_odm->CurrminRptTime != minRptTime) {
0469         rtw_rpt_timer_cfg_cmd(dm_odm->Adapter, minRptTime);
0470         dm_odm->CurrminRptTime = minRptTime;
0471     }
0472 }
0473 
0474 int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 macid)
0475 {
0476     struct odm_ra_info *pRaInfo = &dm_odm->RAInfo[macid];
0477     u8 WirelessMode = 0xFF; /* invalid value */
0478     u8 max_rate_idx = 0x13; /* MCS7 */
0479     if (dm_odm->pWirelessMode)
0480         WirelessMode = *dm_odm->pWirelessMode;
0481 
0482     if (WirelessMode != 0xFF) {
0483         if (WirelessMode & ODM_WM_N24G)
0484             max_rate_idx = 0x13;
0485         else if (WirelessMode & ODM_WM_G)
0486             max_rate_idx = 0x0b;
0487         else if (WirelessMode & ODM_WM_B)
0488             max_rate_idx = 0x03;
0489     }
0490 
0491     pRaInfo->DecisionRate = max_rate_idx;
0492     pRaInfo->PreRate = max_rate_idx;
0493     pRaInfo->HighestRate = max_rate_idx;
0494     pRaInfo->LowestRate = 0;
0495     pRaInfo->RateID = 0;
0496     pRaInfo->RateMask = 0xffffffff;
0497     pRaInfo->RssiStaRA = 0;
0498     pRaInfo->PreRssiStaRA = 0;
0499     pRaInfo->SGIEnable = 0;
0500     pRaInfo->RAUseRate = 0xffffffff;
0501     pRaInfo->NscDown = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2;
0502     pRaInfo->NscUp = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2;
0503     pRaInfo->RateSGI = 0;
0504     pRaInfo->Active = 1;    /* Active is not used at present. by page, 110819 */
0505     pRaInfo->RptTime = 0x927c;
0506     pRaInfo->DROP = 0;
0507     pRaInfo->RTY[0] = 0;
0508     pRaInfo->RTY[1] = 0;
0509     pRaInfo->RTY[2] = 0;
0510     pRaInfo->RTY[3] = 0;
0511     pRaInfo->RTY[4] = 0;
0512     pRaInfo->TOTAL = 0;
0513     pRaInfo->RAWaitingCounter = 0;
0514     pRaInfo->RAPendingCounter = 0;
0515     pRaInfo->PTActive = 1;   /*  Active when this STA is use */
0516     pRaInfo->PTTryState = 0;
0517     pRaInfo->PTStage = 5; /*  Need to fill into HW_PWR_STATUS */
0518     pRaInfo->PTSmoothFactor = 192;
0519     pRaInfo->PTStopCount = 0;
0520     pRaInfo->PTPreRate = 0;
0521     pRaInfo->PTPreRssi = 0;
0522     pRaInfo->PTModeSS = 0;
0523     pRaInfo->RAstage = 0;
0524     return 0;
0525 }
0526 
0527 int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm)
0528 {
0529     u8 macid = 0;
0530 
0531     dm_odm->CurrminRptTime = 0;
0532 
0533     for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++)
0534         ODM_RAInfo_Init(dm_odm, macid);
0535 
0536     return 0;
0537 }
0538 
0539 u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 macid)
0540 {
0541     if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
0542         return 0;
0543     return dm_odm->RAInfo[macid].RateSGI;
0544 }
0545 
0546 u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 macid)
0547 {
0548     u8 DecisionRate = 0;
0549 
0550     if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
0551         return 0;
0552     DecisionRate = (dm_odm->RAInfo[macid].DecisionRate);
0553     return DecisionRate;
0554 }
0555 
0556 u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 macid)
0557 {
0558     u8 PTStage = 5;
0559 
0560     if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
0561         return 0;
0562     PTStage = (dm_odm->RAInfo[macid].PTStage);
0563     return PTStage;
0564 }
0565 
0566 void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 RateID, u32 RateMask, u8 SGIEnable)
0567 {
0568     struct odm_ra_info *pRaInfo = NULL;
0569 
0570     if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
0571         return;
0572 
0573     pRaInfo = &dm_odm->RAInfo[macid];
0574     pRaInfo->RateID = RateID;
0575     pRaInfo->RateMask = RateMask;
0576     pRaInfo->SGIEnable = SGIEnable;
0577     odm_ARFBRefresh_8188E(dm_odm, pRaInfo);
0578 }
0579 
0580 void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 Rssi)
0581 {
0582     struct odm_ra_info *pRaInfo = NULL;
0583 
0584     if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
0585         return;
0586 
0587     pRaInfo = &dm_odm->RAInfo[macid];
0588     pRaInfo->RssiStaRA = Rssi;
0589 }
0590 
0591 void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime)
0592 {
0593     rtw_write16(dm_odm->Adapter, REG_TX_RPT_TIME, minRptTime);
0594 }
0595 
0596 void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm, u8 *TxRPT_Buf, u16 TxRPT_Len, u32 macid_entry0, u32 macid_entry1)
0597 {
0598     struct odm_ra_info *pRAInfo = NULL;
0599     u8 MacId = 0;
0600     u8 *pBuffer = NULL;
0601     u32 valid = 0, ItemNum = 0;
0602     u16 minRptTime = 0x927c;
0603 
0604     ItemNum = TxRPT_Len >> 3;
0605     pBuffer = TxRPT_Buf;
0606 
0607     do {
0608         if (MacId >= ODM_ASSOCIATE_ENTRY_NUM)
0609             valid = 0;
0610         else if (MacId >= 32)
0611             valid = (1 << (MacId - 32)) & macid_entry1;
0612         else
0613             valid = (1 << MacId) & macid_entry0;
0614 
0615         pRAInfo = &dm_odm->RAInfo[MacId];
0616         if (valid) {
0617             pRAInfo->RTY[0] = le16_to_cpup((__le16 *)pBuffer);
0618             pRAInfo->RTY[1] = pBuffer[2];
0619             pRAInfo->RTY[2] = pBuffer[3];
0620             pRAInfo->RTY[3] = pBuffer[4];
0621             pRAInfo->RTY[4] = pBuffer[5];
0622             pRAInfo->DROP = pBuffer[6];
0623             pRAInfo->TOTAL = pRAInfo->RTY[0] + pRAInfo->RTY[1] +
0624                      pRAInfo->RTY[2] + pRAInfo->RTY[3] +
0625                      pRAInfo->RTY[4] + pRAInfo->DROP;
0626             if (pRAInfo->TOTAL != 0) {
0627                 if (pRAInfo->PTActive) {
0628                     if (pRAInfo->RAstage < 5)
0629                         odm_RateDecision_8188E(dm_odm, pRAInfo);
0630                     else if (pRAInfo->RAstage == 5) /*  Power training try state */
0631                         odm_PTTryState_8188E(pRAInfo);
0632                     else /*  RAstage == 6 */
0633                         odm_PTDecision_8188E(pRAInfo);
0634 
0635                     /*  Stage_RA counter */
0636                     if (pRAInfo->RAstage <= 5)
0637                         pRAInfo->RAstage++;
0638                     else
0639                         pRAInfo->RAstage = 0;
0640                 } else {
0641                     odm_RateDecision_8188E(dm_odm, pRAInfo);
0642                 }
0643             }
0644         }
0645 
0646         if (minRptTime > pRAInfo->RptTime)
0647             minRptTime = pRAInfo->RptTime;
0648 
0649         pBuffer += TX_RPT2_ITEM_SIZE;
0650         MacId++;
0651     } while (MacId < ItemNum);
0652 
0653     odm_RATxRPTTimerSetting(dm_odm, minRptTime);
0654 }
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