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0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "qlge.h"
0003 
0004 int qlge_unpause_mpi_risc(struct qlge_adapter *qdev)
0005 {
0006     u32 tmp;
0007 
0008     /* Un-pause the RISC */
0009     tmp = qlge_read32(qdev, CSR);
0010     if (!(tmp & CSR_RP))
0011         return -EIO;
0012 
0013     qlge_write32(qdev, CSR, CSR_CMD_CLR_PAUSE);
0014     return 0;
0015 }
0016 
0017 int qlge_pause_mpi_risc(struct qlge_adapter *qdev)
0018 {
0019     u32 tmp;
0020     int count;
0021 
0022     /* Pause the RISC */
0023     qlge_write32(qdev, CSR, CSR_CMD_SET_PAUSE);
0024     for (count = UDELAY_COUNT; count; count--) {
0025         tmp = qlge_read32(qdev, CSR);
0026         if (tmp & CSR_RP)
0027             break;
0028         mdelay(UDELAY_DELAY);
0029     }
0030     return (count == 0) ? -ETIMEDOUT : 0;
0031 }
0032 
0033 int qlge_hard_reset_mpi_risc(struct qlge_adapter *qdev)
0034 {
0035     u32 tmp;
0036     int count;
0037 
0038     /* Reset the RISC */
0039     qlge_write32(qdev, CSR, CSR_CMD_SET_RST);
0040     for (count = UDELAY_COUNT; count; count--) {
0041         tmp = qlge_read32(qdev, CSR);
0042         if (tmp & CSR_RR) {
0043             qlge_write32(qdev, CSR, CSR_CMD_CLR_RST);
0044             break;
0045         }
0046         mdelay(UDELAY_DELAY);
0047     }
0048     return (count == 0) ? -ETIMEDOUT : 0;
0049 }
0050 
0051 int qlge_read_mpi_reg(struct qlge_adapter *qdev, u32 reg, u32 *data)
0052 {
0053     int status;
0054     /* wait for reg to come ready */
0055     status = qlge_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
0056     if (status)
0057         goto exit;
0058     /* set up for reg read */
0059     qlge_write32(qdev, PROC_ADDR, reg | PROC_ADDR_R);
0060     /* wait for reg to come ready */
0061     status = qlge_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
0062     if (status)
0063         goto exit;
0064     /* get the data */
0065     *data = qlge_read32(qdev, PROC_DATA);
0066 exit:
0067     return status;
0068 }
0069 
0070 int qlge_write_mpi_reg(struct qlge_adapter *qdev, u32 reg, u32 data)
0071 {
0072     int status = 0;
0073     /* wait for reg to come ready */
0074     status = qlge_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
0075     if (status)
0076         goto exit;
0077     /* write the data to the data reg */
0078     qlge_write32(qdev, PROC_DATA, data);
0079     /* trigger the write */
0080     qlge_write32(qdev, PROC_ADDR, reg);
0081     /* wait for reg to come ready */
0082     status = qlge_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
0083     if (status)
0084         goto exit;
0085 exit:
0086     return status;
0087 }
0088 
0089 int qlge_soft_reset_mpi_risc(struct qlge_adapter *qdev)
0090 {
0091     return qlge_write_mpi_reg(qdev, 0x00001010, 1);
0092 }
0093 
0094 /* Determine if we are in charge of the firmware. If
0095  * we are the lower of the 2 NIC pcie functions, or if
0096  * we are the higher function and the lower function
0097  * is not enabled.
0098  */
0099 int qlge_own_firmware(struct qlge_adapter *qdev)
0100 {
0101     u32 temp;
0102 
0103     /* If we are the lower of the 2 NIC functions
0104      * on the chip the we are responsible for
0105      * core dump and firmware reset after an error.
0106      */
0107     if (qdev->func < qdev->alt_func)
0108         return 1;
0109 
0110     /* If we are the higher of the 2 NIC functions
0111      * on the chip and the lower function is not
0112      * enabled, then we are responsible for
0113      * core dump and firmware reset after an error.
0114      */
0115     temp =  qlge_read32(qdev, STS);
0116     if (!(temp & (1 << (8 + qdev->alt_func))))
0117         return 1;
0118 
0119     return 0;
0120 }
0121 
0122 static int qlge_get_mb_sts(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0123 {
0124     int i, status;
0125 
0126     status = qlge_sem_spinlock(qdev, SEM_PROC_REG_MASK);
0127     if (status)
0128         return -EBUSY;
0129     for (i = 0; i < mbcp->out_count; i++) {
0130         status =
0131             qlge_read_mpi_reg(qdev, qdev->mailbox_out + i,
0132                       &mbcp->mbox_out[i]);
0133         if (status) {
0134             netif_err(qdev, drv, qdev->ndev, "Failed mailbox read.\n");
0135             break;
0136         }
0137     }
0138     qlge_sem_unlock(qdev, SEM_PROC_REG_MASK);   /* does flush too */
0139     return status;
0140 }
0141 
0142 /* Wait for a single mailbox command to complete.
0143  * Returns zero on success.
0144  */
0145 static int qlge_wait_mbx_cmd_cmplt(struct qlge_adapter *qdev)
0146 {
0147     int count;
0148     u32 value;
0149 
0150     for (count = 100; count; count--) {
0151         value = qlge_read32(qdev, STS);
0152         if (value & STS_PI)
0153             return 0;
0154         mdelay(UDELAY_DELAY); /* 100ms */
0155     }
0156     return -ETIMEDOUT;
0157 }
0158 
0159 /* Execute a single mailbox command.
0160  * Caller must hold PROC_ADDR semaphore.
0161  */
0162 static int qlge_exec_mb_cmd(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0163 {
0164     int i, status;
0165 
0166     /*
0167      * Make sure there's nothing pending.
0168      * This shouldn't happen.
0169      */
0170     if (qlge_read32(qdev, CSR) & CSR_HRI)
0171         return -EIO;
0172 
0173     status = qlge_sem_spinlock(qdev, SEM_PROC_REG_MASK);
0174     if (status)
0175         return status;
0176 
0177     /*
0178      * Fill the outbound mailboxes.
0179      */
0180     for (i = 0; i < mbcp->in_count; i++) {
0181         status = qlge_write_mpi_reg(qdev, qdev->mailbox_in + i,
0182                         mbcp->mbox_in[i]);
0183         if (status)
0184             goto end;
0185     }
0186     /*
0187      * Wake up the MPI firmware.
0188      */
0189     qlge_write32(qdev, CSR, CSR_CMD_SET_H2R_INT);
0190 end:
0191     qlge_sem_unlock(qdev, SEM_PROC_REG_MASK);
0192     return status;
0193 }
0194 
0195 /* We are being asked by firmware to accept
0196  * a change to the port.  This is only
0197  * a change to max frame sizes (Tx/Rx), pause
0198  * parameters, or loopback mode. We wake up a worker
0199  * to handler processing this since a mailbox command
0200  * will need to be sent to ACK the request.
0201  */
0202 static int qlge_idc_req_aen(struct qlge_adapter *qdev)
0203 {
0204     int status;
0205     struct mbox_params *mbcp = &qdev->idc_mbc;
0206 
0207     netif_err(qdev, drv, qdev->ndev, "Enter!\n");
0208     /* Get the status data and start up a thread to
0209      * handle the request.
0210      */
0211     mbcp->out_count = 4;
0212     status = qlge_get_mb_sts(qdev, mbcp);
0213     if (status) {
0214         netif_err(qdev, drv, qdev->ndev,
0215               "Could not read MPI, resetting ASIC!\n");
0216         qlge_queue_asic_error(qdev);
0217     } else  {
0218         /* Begin polled mode early so
0219          * we don't get another interrupt
0220          * when we leave mpi_worker.
0221          */
0222         qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
0223         queue_delayed_work(qdev->workqueue, &qdev->mpi_idc_work, 0);
0224     }
0225     return status;
0226 }
0227 
0228 /* Process an inter-device event completion.
0229  * If good, signal the caller's completion.
0230  */
0231 static int qlge_idc_cmplt_aen(struct qlge_adapter *qdev)
0232 {
0233     int status;
0234     struct mbox_params *mbcp = &qdev->idc_mbc;
0235 
0236     mbcp->out_count = 4;
0237     status = qlge_get_mb_sts(qdev, mbcp);
0238     if (status) {
0239         netif_err(qdev, drv, qdev->ndev,
0240               "Could not read MPI, resetting RISC!\n");
0241         qlge_queue_fw_error(qdev);
0242     } else {
0243         /* Wake up the sleeping mpi_idc_work thread that is
0244          * waiting for this event.
0245          */
0246         complete(&qdev->ide_completion);
0247     }
0248     return status;
0249 }
0250 
0251 static void qlge_link_up(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0252 {
0253     int status;
0254 
0255     mbcp->out_count = 2;
0256 
0257     status = qlge_get_mb_sts(qdev, mbcp);
0258     if (status) {
0259         netif_err(qdev, drv, qdev->ndev,
0260               "%s: Could not get mailbox status.\n", __func__);
0261         return;
0262     }
0263 
0264     qdev->link_status = mbcp->mbox_out[1];
0265     netif_err(qdev, drv, qdev->ndev, "Link Up.\n");
0266 
0267     /* If we're coming back from an IDC event
0268      * then set up the CAM and frame routing.
0269      */
0270     if (test_bit(QL_CAM_RT_SET, &qdev->flags)) {
0271         status = qlge_cam_route_initialize(qdev);
0272         if (status) {
0273             netif_err(qdev, ifup, qdev->ndev,
0274                   "Failed to init CAM/Routing tables.\n");
0275             return;
0276         }
0277         clear_bit(QL_CAM_RT_SET, &qdev->flags);
0278     }
0279 
0280     /* Queue up a worker to check the frame
0281      * size information, and fix it if it's not
0282      * to our liking.
0283      */
0284     if (!test_bit(QL_PORT_CFG, &qdev->flags)) {
0285         netif_err(qdev, drv, qdev->ndev, "Queue Port Config Worker!\n");
0286         set_bit(QL_PORT_CFG, &qdev->flags);
0287         /* Begin polled mode early so
0288          * we don't get another interrupt
0289          * when we leave mpi_worker dpc.
0290          */
0291         qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
0292         queue_delayed_work(qdev->workqueue,
0293                    &qdev->mpi_port_cfg_work, 0);
0294     }
0295 
0296     qlge_link_on(qdev);
0297 }
0298 
0299 static void qlge_link_down(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0300 {
0301     int status;
0302 
0303     mbcp->out_count = 3;
0304 
0305     status = qlge_get_mb_sts(qdev, mbcp);
0306     if (status)
0307         netif_err(qdev, drv, qdev->ndev, "Link down AEN broken!\n");
0308 
0309     qlge_link_off(qdev);
0310 }
0311 
0312 static int qlge_sfp_in(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0313 {
0314     int status;
0315 
0316     mbcp->out_count = 5;
0317 
0318     status = qlge_get_mb_sts(qdev, mbcp);
0319     if (status)
0320         netif_err(qdev, drv, qdev->ndev, "SFP in AEN broken!\n");
0321     else
0322         netif_err(qdev, drv, qdev->ndev, "SFP insertion detected.\n");
0323 
0324     return status;
0325 }
0326 
0327 static int qlge_sfp_out(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0328 {
0329     int status;
0330 
0331     mbcp->out_count = 1;
0332 
0333     status = qlge_get_mb_sts(qdev, mbcp);
0334     if (status)
0335         netif_err(qdev, drv, qdev->ndev, "SFP out AEN broken!\n");
0336     else
0337         netif_err(qdev, drv, qdev->ndev, "SFP removal detected.\n");
0338 
0339     return status;
0340 }
0341 
0342 static int qlge_aen_lost(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0343 {
0344     int status;
0345 
0346     mbcp->out_count = 6;
0347 
0348     status = qlge_get_mb_sts(qdev, mbcp);
0349     if (status) {
0350         netif_err(qdev, drv, qdev->ndev, "Lost AEN broken!\n");
0351     } else {
0352         int i;
0353 
0354         netif_err(qdev, drv, qdev->ndev, "Lost AEN detected.\n");
0355         for (i = 0; i < mbcp->out_count; i++)
0356             netif_err(qdev, drv, qdev->ndev, "mbox_out[%d] = 0x%.08x.\n",
0357                   i, mbcp->mbox_out[i]);
0358     }
0359 
0360     return status;
0361 }
0362 
0363 static void qlge_init_fw_done(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0364 {
0365     int status;
0366 
0367     mbcp->out_count = 2;
0368 
0369     status = qlge_get_mb_sts(qdev, mbcp);
0370     if (status) {
0371         netif_err(qdev, drv, qdev->ndev, "Firmware did not initialize!\n");
0372     } else {
0373         netif_err(qdev, drv, qdev->ndev, "Firmware Revision  = 0x%.08x.\n",
0374               mbcp->mbox_out[1]);
0375         qdev->fw_rev_id = mbcp->mbox_out[1];
0376         status = qlge_cam_route_initialize(qdev);
0377         if (status)
0378             netif_err(qdev, ifup, qdev->ndev,
0379                   "Failed to init CAM/Routing tables.\n");
0380     }
0381 }
0382 
0383 /* Process an async event and clear it unless it's an
0384  * error condition.
0385  *  This can get called iteratively from the mpi_work thread
0386  *  when events arrive via an interrupt.
0387  *  It also gets called when a mailbox command is polling for
0388  *  it's completion.
0389  */
0390 static int qlge_mpi_handler(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0391 {
0392     int status;
0393     int orig_count = mbcp->out_count;
0394 
0395     /* Just get mailbox zero for now. */
0396     mbcp->out_count = 1;
0397     status = qlge_get_mb_sts(qdev, mbcp);
0398     if (status) {
0399         netif_err(qdev, drv, qdev->ndev,
0400               "Could not read MPI, resetting ASIC!\n");
0401         qlge_queue_asic_error(qdev);
0402         goto end;
0403     }
0404 
0405     switch (mbcp->mbox_out[0]) {
0406         /* This case is only active when we arrive here
0407          * as a result of issuing a mailbox command to
0408          * the firmware.
0409          */
0410     case MB_CMD_STS_INTRMDT:
0411     case MB_CMD_STS_GOOD:
0412     case MB_CMD_STS_INVLD_CMD:
0413     case MB_CMD_STS_XFC_ERR:
0414     case MB_CMD_STS_CSUM_ERR:
0415     case MB_CMD_STS_ERR:
0416     case MB_CMD_STS_PARAM_ERR:
0417         /* We can only get mailbox status if we're polling from an
0418          * unfinished command.  Get the rest of the status data and
0419          * return back to the caller.
0420          * We only end up here when we're polling for a mailbox
0421          * command completion.
0422          */
0423         mbcp->out_count = orig_count;
0424         status = qlge_get_mb_sts(qdev, mbcp);
0425         return status;
0426 
0427         /* We are being asked by firmware to accept
0428          * a change to the port.  This is only
0429          * a change to max frame sizes (Tx/Rx), pause
0430          * parameters, or loopback mode.
0431          */
0432     case AEN_IDC_REQ:
0433         status = qlge_idc_req_aen(qdev);
0434         break;
0435 
0436         /* Process and inbound IDC event.
0437          * This will happen when we're trying to
0438          * change tx/rx max frame size, change pause
0439          * parameters or loopback mode.
0440          */
0441     case AEN_IDC_CMPLT:
0442     case AEN_IDC_EXT:
0443         status = qlge_idc_cmplt_aen(qdev);
0444         break;
0445 
0446     case AEN_LINK_UP:
0447         qlge_link_up(qdev, mbcp);
0448         break;
0449 
0450     case AEN_LINK_DOWN:
0451         qlge_link_down(qdev, mbcp);
0452         break;
0453 
0454     case AEN_FW_INIT_DONE:
0455         /* If we're in process on executing the firmware,
0456          * then convert the status to normal mailbox status.
0457          */
0458         if (mbcp->mbox_in[0] == MB_CMD_EX_FW) {
0459             mbcp->out_count = orig_count;
0460             status = qlge_get_mb_sts(qdev, mbcp);
0461             mbcp->mbox_out[0] = MB_CMD_STS_GOOD;
0462             return status;
0463         }
0464         qlge_init_fw_done(qdev, mbcp);
0465         break;
0466 
0467     case AEN_AEN_SFP_IN:
0468         qlge_sfp_in(qdev, mbcp);
0469         break;
0470 
0471     case AEN_AEN_SFP_OUT:
0472         qlge_sfp_out(qdev, mbcp);
0473         break;
0474 
0475         /* This event can arrive at boot time or after an
0476          * MPI reset if the firmware failed to initialize.
0477          */
0478     case AEN_FW_INIT_FAIL:
0479         /* If we're in process on executing the firmware,
0480          * then convert the status to normal mailbox status.
0481          */
0482         if (mbcp->mbox_in[0] == MB_CMD_EX_FW) {
0483             mbcp->out_count = orig_count;
0484             status = qlge_get_mb_sts(qdev, mbcp);
0485             mbcp->mbox_out[0] = MB_CMD_STS_ERR;
0486             return status;
0487         }
0488         netif_err(qdev, drv, qdev->ndev,
0489               "Firmware initialization failed.\n");
0490         status = -EIO;
0491         qlge_queue_fw_error(qdev);
0492         break;
0493 
0494     case AEN_SYS_ERR:
0495         netif_err(qdev, drv, qdev->ndev, "System Error.\n");
0496         qlge_queue_fw_error(qdev);
0497         status = -EIO;
0498         break;
0499 
0500     case AEN_AEN_LOST:
0501         qlge_aen_lost(qdev, mbcp);
0502         break;
0503 
0504     case AEN_DCBX_CHG:
0505         /* Need to support AEN 8110 */
0506         break;
0507     default:
0508         netif_err(qdev, drv, qdev->ndev,
0509               "Unsupported AE %.08x.\n", mbcp->mbox_out[0]);
0510         /* Clear the MPI firmware status. */
0511     }
0512 end:
0513     qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
0514     /* Restore the original mailbox count to
0515      * what the caller asked for.  This can get
0516      * changed when a mailbox command is waiting
0517      * for a response and an AEN arrives and
0518      * is handled.
0519      */
0520     mbcp->out_count = orig_count;
0521     return status;
0522 }
0523 
0524 /* Execute a single mailbox command.
0525  * mbcp is a pointer to an array of u32.  Each
0526  * element in the array contains the value for it's
0527  * respective mailbox register.
0528  */
0529 static int qlge_mailbox_command(struct qlge_adapter *qdev, struct mbox_params *mbcp)
0530 {
0531     int status;
0532     unsigned long count;
0533 
0534     mutex_lock(&qdev->mpi_mutex);
0535 
0536     /* Begin polled mode for MPI */
0537     qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
0538 
0539     /* Load the mailbox registers and wake up MPI RISC. */
0540     status = qlge_exec_mb_cmd(qdev, mbcp);
0541     if (status)
0542         goto end;
0543 
0544     /* If we're generating a system error, then there's nothing
0545      * to wait for.
0546      */
0547     if (mbcp->mbox_in[0] == MB_CMD_MAKE_SYS_ERR)
0548         goto end;
0549 
0550     /* Wait for the command to complete. We loop
0551      * here because some AEN might arrive while
0552      * we're waiting for the mailbox command to
0553      * complete. If more than 5 seconds expire we can
0554      * assume something is wrong.
0555      */
0556     count = jiffies + HZ * MAILBOX_TIMEOUT;
0557     do {
0558         /* Wait for the interrupt to come in. */
0559         status = qlge_wait_mbx_cmd_cmplt(qdev);
0560         if (status)
0561             continue;
0562 
0563         /* Process the event.  If it's an AEN, it
0564          * will be handled in-line or a worker
0565          * will be spawned. If it's our completion
0566          * we will catch it below.
0567          */
0568         status = qlge_mpi_handler(qdev, mbcp);
0569         if (status)
0570             goto end;
0571 
0572         /* It's either the completion for our mailbox
0573          * command complete or an AEN.  If it's our
0574          * completion then get out.
0575          */
0576         if (((mbcp->mbox_out[0] & 0x0000f000) ==
0577              MB_CMD_STS_GOOD) ||
0578             ((mbcp->mbox_out[0] & 0x0000f000) ==
0579              MB_CMD_STS_INTRMDT))
0580             goto done;
0581     } while (time_before(jiffies, count));
0582 
0583     netif_err(qdev, drv, qdev->ndev,
0584           "Timed out waiting for mailbox complete.\n");
0585     status = -ETIMEDOUT;
0586     goto end;
0587 
0588 done:
0589 
0590     /* Now we can clear the interrupt condition
0591      * and look at our status.
0592      */
0593     qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
0594 
0595     if (((mbcp->mbox_out[0] & 0x0000f000) !=
0596          MB_CMD_STS_GOOD) &&
0597         ((mbcp->mbox_out[0] & 0x0000f000) !=
0598          MB_CMD_STS_INTRMDT)) {
0599         status = -EIO;
0600     }
0601 end:
0602     /* End polled mode for MPI */
0603     qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
0604     mutex_unlock(&qdev->mpi_mutex);
0605     return status;
0606 }
0607 
0608 /* Get MPI firmware version. This will be used for
0609  * driver banner and for ethtool info.
0610  * Returns zero on success.
0611  */
0612 int qlge_mb_about_fw(struct qlge_adapter *qdev)
0613 {
0614     struct mbox_params mbc;
0615     struct mbox_params *mbcp = &mbc;
0616     int status = 0;
0617 
0618     memset(mbcp, 0, sizeof(struct mbox_params));
0619 
0620     mbcp->in_count = 1;
0621     mbcp->out_count = 3;
0622 
0623     mbcp->mbox_in[0] = MB_CMD_ABOUT_FW;
0624 
0625     status = qlge_mailbox_command(qdev, mbcp);
0626     if (status)
0627         return status;
0628 
0629     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0630         netif_err(qdev, drv, qdev->ndev,
0631               "Failed about firmware command\n");
0632         status = -EIO;
0633     }
0634 
0635     /* Store the firmware version */
0636     qdev->fw_rev_id = mbcp->mbox_out[1];
0637 
0638     return status;
0639 }
0640 
0641 /* Get functional state for MPI firmware.
0642  * Returns zero on success.
0643  */
0644 int qlge_mb_get_fw_state(struct qlge_adapter *qdev)
0645 {
0646     struct mbox_params mbc;
0647     struct mbox_params *mbcp = &mbc;
0648     int status = 0;
0649 
0650     memset(mbcp, 0, sizeof(struct mbox_params));
0651 
0652     mbcp->in_count = 1;
0653     mbcp->out_count = 2;
0654 
0655     mbcp->mbox_in[0] = MB_CMD_GET_FW_STATE;
0656 
0657     status = qlge_mailbox_command(qdev, mbcp);
0658     if (status)
0659         return status;
0660 
0661     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0662         netif_err(qdev, drv, qdev->ndev,
0663               "Failed Get Firmware State.\n");
0664         status = -EIO;
0665     }
0666 
0667     /* If bit zero is set in mbx 1 then the firmware is
0668      * running, but not initialized.  This should never
0669      * happen.
0670      */
0671     if (mbcp->mbox_out[1] & 1) {
0672         netif_err(qdev, drv, qdev->ndev,
0673               "Firmware waiting for initialization.\n");
0674         status = -EIO;
0675     }
0676 
0677     return status;
0678 }
0679 
0680 /* Send and ACK mailbox command to the firmware to
0681  * let it continue with the change.
0682  */
0683 static int qlge_mb_idc_ack(struct qlge_adapter *qdev)
0684 {
0685     struct mbox_params mbc;
0686     struct mbox_params *mbcp = &mbc;
0687     int status = 0;
0688 
0689     memset(mbcp, 0, sizeof(struct mbox_params));
0690 
0691     mbcp->in_count = 5;
0692     mbcp->out_count = 1;
0693 
0694     mbcp->mbox_in[0] = MB_CMD_IDC_ACK;
0695     mbcp->mbox_in[1] = qdev->idc_mbc.mbox_out[1];
0696     mbcp->mbox_in[2] = qdev->idc_mbc.mbox_out[2];
0697     mbcp->mbox_in[3] = qdev->idc_mbc.mbox_out[3];
0698     mbcp->mbox_in[4] = qdev->idc_mbc.mbox_out[4];
0699 
0700     status = qlge_mailbox_command(qdev, mbcp);
0701     if (status)
0702         return status;
0703 
0704     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0705         netif_err(qdev, drv, qdev->ndev, "Failed IDC ACK send.\n");
0706         status = -EIO;
0707     }
0708     return status;
0709 }
0710 
0711 /* Get link settings and maximum frame size settings
0712  * for the current port.
0713  * Most likely will block.
0714  */
0715 int qlge_mb_set_port_cfg(struct qlge_adapter *qdev)
0716 {
0717     struct mbox_params mbc;
0718     struct mbox_params *mbcp = &mbc;
0719     int status = 0;
0720 
0721     memset(mbcp, 0, sizeof(struct mbox_params));
0722 
0723     mbcp->in_count = 3;
0724     mbcp->out_count = 1;
0725 
0726     mbcp->mbox_in[0] = MB_CMD_SET_PORT_CFG;
0727     mbcp->mbox_in[1] = qdev->link_config;
0728     mbcp->mbox_in[2] = qdev->max_frame_size;
0729 
0730     status = qlge_mailbox_command(qdev, mbcp);
0731     if (status)
0732         return status;
0733 
0734     if (mbcp->mbox_out[0] == MB_CMD_STS_INTRMDT) {
0735         netif_err(qdev, drv, qdev->ndev,
0736               "Port Config sent, wait for IDC.\n");
0737     } else  if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0738         netif_err(qdev, drv, qdev->ndev,
0739               "Failed Set Port Configuration.\n");
0740         status = -EIO;
0741     }
0742     return status;
0743 }
0744 
0745 static int qlge_mb_dump_ram(struct qlge_adapter *qdev, u64 req_dma, u32 addr,
0746                 u32 size)
0747 {
0748     int status = 0;
0749     struct mbox_params mbc;
0750     struct mbox_params *mbcp = &mbc;
0751 
0752     memset(mbcp, 0, sizeof(struct mbox_params));
0753 
0754     mbcp->in_count = 9;
0755     mbcp->out_count = 1;
0756 
0757     mbcp->mbox_in[0] = MB_CMD_DUMP_RISC_RAM;
0758     mbcp->mbox_in[1] = LSW(addr);
0759     mbcp->mbox_in[2] = MSW(req_dma);
0760     mbcp->mbox_in[3] = LSW(req_dma);
0761     mbcp->mbox_in[4] = MSW(size);
0762     mbcp->mbox_in[5] = LSW(size);
0763     mbcp->mbox_in[6] = MSW(MSD(req_dma));
0764     mbcp->mbox_in[7] = LSW(MSD(req_dma));
0765     mbcp->mbox_in[8] = MSW(addr);
0766 
0767     status = qlge_mailbox_command(qdev, mbcp);
0768     if (status)
0769         return status;
0770 
0771     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0772         netif_err(qdev, drv, qdev->ndev, "Failed to dump risc RAM.\n");
0773         status = -EIO;
0774     }
0775     return status;
0776 }
0777 
0778 /* Issue a mailbox command to dump RISC RAM. */
0779 int qlge_dump_risc_ram_area(struct qlge_adapter *qdev, void *buf,
0780                 u32 ram_addr, int word_count)
0781 {
0782     int status;
0783     char *my_buf;
0784     dma_addr_t buf_dma;
0785 
0786     my_buf = dma_alloc_coherent(&qdev->pdev->dev,
0787                     word_count * sizeof(u32), &buf_dma,
0788                     GFP_ATOMIC);
0789     if (!my_buf)
0790         return -EIO;
0791 
0792     status = qlge_mb_dump_ram(qdev, buf_dma, ram_addr, word_count);
0793     if (!status)
0794         memcpy(buf, my_buf, word_count * sizeof(u32));
0795 
0796     dma_free_coherent(&qdev->pdev->dev, word_count * sizeof(u32), my_buf,
0797               buf_dma);
0798     return status;
0799 }
0800 
0801 /* Get link settings and maximum frame size settings
0802  * for the current port.
0803  * Most likely will block.
0804  */
0805 int qlge_mb_get_port_cfg(struct qlge_adapter *qdev)
0806 {
0807     struct mbox_params mbc;
0808     struct mbox_params *mbcp = &mbc;
0809     int status = 0;
0810 
0811     memset(mbcp, 0, sizeof(struct mbox_params));
0812 
0813     mbcp->in_count = 1;
0814     mbcp->out_count = 3;
0815 
0816     mbcp->mbox_in[0] = MB_CMD_GET_PORT_CFG;
0817 
0818     status = qlge_mailbox_command(qdev, mbcp);
0819     if (status)
0820         return status;
0821 
0822     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0823         netif_err(qdev, drv, qdev->ndev,
0824               "Failed Get Port Configuration.\n");
0825         status = -EIO;
0826     } else  {
0827         netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
0828                  "Passed Get Port Configuration.\n");
0829         qdev->link_config = mbcp->mbox_out[1];
0830         qdev->max_frame_size = mbcp->mbox_out[2];
0831     }
0832     return status;
0833 }
0834 
0835 int qlge_mb_wol_mode(struct qlge_adapter *qdev, u32 wol)
0836 {
0837     struct mbox_params mbc;
0838     struct mbox_params *mbcp = &mbc;
0839     int status;
0840 
0841     memset(mbcp, 0, sizeof(struct mbox_params));
0842 
0843     mbcp->in_count = 2;
0844     mbcp->out_count = 1;
0845 
0846     mbcp->mbox_in[0] = MB_CMD_SET_WOL_MODE;
0847     mbcp->mbox_in[1] = wol;
0848 
0849     status = qlge_mailbox_command(qdev, mbcp);
0850     if (status)
0851         return status;
0852 
0853     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0854         netif_err(qdev, drv, qdev->ndev, "Failed to set WOL mode.\n");
0855         status = -EIO;
0856     }
0857     return status;
0858 }
0859 
0860 int qlge_mb_wol_set_magic(struct qlge_adapter *qdev, u32 enable_wol)
0861 {
0862     struct mbox_params mbc;
0863     struct mbox_params *mbcp = &mbc;
0864     int status;
0865     const u8 *addr = qdev->ndev->dev_addr;
0866 
0867     memset(mbcp, 0, sizeof(struct mbox_params));
0868 
0869     mbcp->in_count = 8;
0870     mbcp->out_count = 1;
0871 
0872     mbcp->mbox_in[0] = MB_CMD_SET_WOL_MAGIC;
0873     if (enable_wol) {
0874         mbcp->mbox_in[1] = (u32)addr[0];
0875         mbcp->mbox_in[2] = (u32)addr[1];
0876         mbcp->mbox_in[3] = (u32)addr[2];
0877         mbcp->mbox_in[4] = (u32)addr[3];
0878         mbcp->mbox_in[5] = (u32)addr[4];
0879         mbcp->mbox_in[6] = (u32)addr[5];
0880         mbcp->mbox_in[7] = 0;
0881     } else {
0882         mbcp->mbox_in[1] = 0;
0883         mbcp->mbox_in[2] = 1;
0884         mbcp->mbox_in[3] = 1;
0885         mbcp->mbox_in[4] = 1;
0886         mbcp->mbox_in[5] = 1;
0887         mbcp->mbox_in[6] = 1;
0888         mbcp->mbox_in[7] = 0;
0889     }
0890 
0891     status = qlge_mailbox_command(qdev, mbcp);
0892     if (status)
0893         return status;
0894 
0895     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0896         netif_err(qdev, drv, qdev->ndev, "Failed to set WOL mode.\n");
0897         status = -EIO;
0898     }
0899     return status;
0900 }
0901 
0902 /* IDC - Inter Device Communication...
0903  * Some firmware commands require consent of adjacent FCOE
0904  * function.  This function waits for the OK, or a
0905  * counter-request for a little more time.i
0906  * The firmware will complete the request if the other
0907  * function doesn't respond.
0908  */
0909 static int qlge_idc_wait(struct qlge_adapter *qdev)
0910 {
0911     int status = -ETIMEDOUT;
0912     struct mbox_params *mbcp = &qdev->idc_mbc;
0913     long wait_time;
0914 
0915     for (wait_time = 1 * HZ; wait_time;) {
0916         /* Wait here for the command to complete
0917          * via the IDC process.
0918          */
0919         wait_time =
0920             wait_for_completion_timeout(&qdev->ide_completion,
0921                             wait_time);
0922         if (!wait_time) {
0923             netif_err(qdev, drv, qdev->ndev, "IDC Timeout.\n");
0924             break;
0925         }
0926         /* Now examine the response from the IDC process.
0927          * We might have a good completion or a request for
0928          * more wait time.
0929          */
0930         if (mbcp->mbox_out[0] == AEN_IDC_EXT) {
0931             netif_err(qdev, drv, qdev->ndev,
0932                   "IDC Time Extension from function.\n");
0933             wait_time += (mbcp->mbox_out[1] >> 8) & 0x0000000f;
0934         } else if (mbcp->mbox_out[0] == AEN_IDC_CMPLT) {
0935             netif_err(qdev, drv, qdev->ndev, "IDC Success.\n");
0936             status = 0;
0937             break;
0938         } else {
0939             netif_err(qdev, drv, qdev->ndev,
0940                   "IDC: Invalid State 0x%.04x.\n",
0941                   mbcp->mbox_out[0]);
0942             status = -EIO;
0943             break;
0944         }
0945     }
0946 
0947     return status;
0948 }
0949 
0950 int qlge_mb_set_led_cfg(struct qlge_adapter *qdev, u32 led_config)
0951 {
0952     struct mbox_params mbc;
0953     struct mbox_params *mbcp = &mbc;
0954     int status;
0955 
0956     memset(mbcp, 0, sizeof(struct mbox_params));
0957 
0958     mbcp->in_count = 2;
0959     mbcp->out_count = 1;
0960 
0961     mbcp->mbox_in[0] = MB_CMD_SET_LED_CFG;
0962     mbcp->mbox_in[1] = led_config;
0963 
0964     status = qlge_mailbox_command(qdev, mbcp);
0965     if (status)
0966         return status;
0967 
0968     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0969         netif_err(qdev, drv, qdev->ndev,
0970               "Failed to set LED Configuration.\n");
0971         status = -EIO;
0972     }
0973 
0974     return status;
0975 }
0976 
0977 int qlge_mb_get_led_cfg(struct qlge_adapter *qdev)
0978 {
0979     struct mbox_params mbc;
0980     struct mbox_params *mbcp = &mbc;
0981     int status;
0982 
0983     memset(mbcp, 0, sizeof(struct mbox_params));
0984 
0985     mbcp->in_count = 1;
0986     mbcp->out_count = 2;
0987 
0988     mbcp->mbox_in[0] = MB_CMD_GET_LED_CFG;
0989 
0990     status = qlge_mailbox_command(qdev, mbcp);
0991     if (status)
0992         return status;
0993 
0994     if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
0995         netif_err(qdev, drv, qdev->ndev,
0996               "Failed to get LED Configuration.\n");
0997         status = -EIO;
0998     } else {
0999         qdev->led_config = mbcp->mbox_out[1];
1000     }
1001     return status;
1002 }
1003 
1004 int qlge_mb_set_mgmnt_traffic_ctl(struct qlge_adapter *qdev, u32 control)
1005 {
1006     struct mbox_params mbc;
1007     struct mbox_params *mbcp = &mbc;
1008     int status;
1009 
1010     memset(mbcp, 0, sizeof(struct mbox_params));
1011 
1012     mbcp->in_count = 1;
1013     mbcp->out_count = 2;
1014 
1015     mbcp->mbox_in[0] = MB_CMD_SET_MGMNT_TFK_CTL;
1016     mbcp->mbox_in[1] = control;
1017 
1018     status = qlge_mailbox_command(qdev, mbcp);
1019     if (status)
1020         return status;
1021 
1022     if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD)
1023         return status;
1024 
1025     if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
1026         netif_err(qdev, drv, qdev->ndev,
1027               "Command not supported by firmware.\n");
1028         status = -EINVAL;
1029     } else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
1030         /* This indicates that the firmware is
1031          * already in the state we are trying to
1032          * change it to.
1033          */
1034         netif_err(qdev, drv, qdev->ndev,
1035               "Command parameters make no change.\n");
1036     }
1037     return status;
1038 }
1039 
1040 /* Returns a negative error code or the mailbox command status. */
1041 static int qlge_mb_get_mgmnt_traffic_ctl(struct qlge_adapter *qdev, u32 *control)
1042 {
1043     struct mbox_params mbc;
1044     struct mbox_params *mbcp = &mbc;
1045     int status;
1046 
1047     memset(mbcp, 0, sizeof(struct mbox_params));
1048     *control = 0;
1049 
1050     mbcp->in_count = 1;
1051     mbcp->out_count = 1;
1052 
1053     mbcp->mbox_in[0] = MB_CMD_GET_MGMNT_TFK_CTL;
1054 
1055     status = qlge_mailbox_command(qdev, mbcp);
1056     if (status)
1057         return status;
1058 
1059     if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD) {
1060         *control = mbcp->mbox_in[1];
1061         return status;
1062     }
1063 
1064     if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
1065         netif_err(qdev, drv, qdev->ndev,
1066               "Command not supported by firmware.\n");
1067         status = -EINVAL;
1068     } else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
1069         netif_err(qdev, drv, qdev->ndev,
1070               "Failed to get MPI traffic control.\n");
1071         status = -EIO;
1072     }
1073     return status;
1074 }
1075 
1076 int qlge_wait_fifo_empty(struct qlge_adapter *qdev)
1077 {
1078     int count;
1079     u32 mgmnt_fifo_empty;
1080     u32 nic_fifo_empty;
1081 
1082     for (count = 6; count; count--) {
1083         nic_fifo_empty = qlge_read32(qdev, STS) & STS_NFE;
1084         qlge_mb_get_mgmnt_traffic_ctl(qdev, &mgmnt_fifo_empty);
1085         mgmnt_fifo_empty &= MB_GET_MPI_TFK_FIFO_EMPTY;
1086         if (nic_fifo_empty && mgmnt_fifo_empty)
1087             return 0;
1088         msleep(100);
1089     }
1090     return -ETIMEDOUT;
1091 }
1092 
1093 /* API called in work thread context to set new TX/RX
1094  * maximum frame size values to match MTU.
1095  */
1096 static int qlge_set_port_cfg(struct qlge_adapter *qdev)
1097 {
1098     int status;
1099 
1100     status = qlge_mb_set_port_cfg(qdev);
1101     if (status)
1102         return status;
1103     status = qlge_idc_wait(qdev);
1104     return status;
1105 }
1106 
1107 /* The following routines are worker threads that process
1108  * events that may sleep waiting for completion.
1109  */
1110 
1111 /* This thread gets the maximum TX and RX frame size values
1112  * from the firmware and, if necessary, changes them to match
1113  * the MTU setting.
1114  */
1115 void qlge_mpi_port_cfg_work(struct work_struct *work)
1116 {
1117     struct qlge_adapter *qdev =
1118         container_of(work, struct qlge_adapter, mpi_port_cfg_work.work);
1119     int status;
1120 
1121     status = qlge_mb_get_port_cfg(qdev);
1122     if (status) {
1123         netif_err(qdev, drv, qdev->ndev,
1124               "Bug: Failed to get port config data.\n");
1125         goto err;
1126     }
1127 
1128     if (qdev->link_config & CFG_JUMBO_FRAME_SIZE &&
1129         qdev->max_frame_size == CFG_DEFAULT_MAX_FRAME_SIZE)
1130         goto end;
1131 
1132     qdev->link_config |=    CFG_JUMBO_FRAME_SIZE;
1133     qdev->max_frame_size = CFG_DEFAULT_MAX_FRAME_SIZE;
1134     status = qlge_set_port_cfg(qdev);
1135     if (status) {
1136         netif_err(qdev, drv, qdev->ndev,
1137               "Bug: Failed to set port config data.\n");
1138         goto err;
1139     }
1140 end:
1141     clear_bit(QL_PORT_CFG, &qdev->flags);
1142     return;
1143 err:
1144     qlge_queue_fw_error(qdev);
1145     goto end;
1146 }
1147 
1148 /* Process an inter-device request.  This is issues by
1149  * the firmware in response to another function requesting
1150  * a change to the port. We set a flag to indicate a change
1151  * has been made and then send a mailbox command ACKing
1152  * the change request.
1153  */
1154 void qlge_mpi_idc_work(struct work_struct *work)
1155 {
1156     struct qlge_adapter *qdev =
1157         container_of(work, struct qlge_adapter, mpi_idc_work.work);
1158     int status;
1159     struct mbox_params *mbcp = &qdev->idc_mbc;
1160     u32 aen;
1161     int timeout;
1162 
1163     aen = mbcp->mbox_out[1] >> 16;
1164     timeout = (mbcp->mbox_out[1] >> 8) & 0xf;
1165 
1166     switch (aen) {
1167     default:
1168         netif_err(qdev, drv, qdev->ndev,
1169               "Bug: Unhandled IDC action.\n");
1170         break;
1171     case MB_CMD_PORT_RESET:
1172     case MB_CMD_STOP_FW:
1173         qlge_link_off(qdev);
1174         fallthrough;
1175     case MB_CMD_SET_PORT_CFG:
1176         /* Signal the resulting link up AEN
1177          * that the frame routing and mac addr
1178          * needs to be set.
1179          */
1180         set_bit(QL_CAM_RT_SET, &qdev->flags);
1181         /* Do ACK if required */
1182         if (timeout) {
1183             status = qlge_mb_idc_ack(qdev);
1184             if (status)
1185                 netif_err(qdev, drv, qdev->ndev,
1186                       "Bug: No pending IDC!\n");
1187         } else {
1188             netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
1189                      "IDC ACK not required\n");
1190             status = 0; /* success */
1191         }
1192         break;
1193 
1194         /* These sub-commands issued by another (FCoE)
1195          * function are requesting to do an operation
1196          * on the shared resource (MPI environment).
1197          * We currently don't issue these so we just
1198          * ACK the request.
1199          */
1200     case MB_CMD_IOP_RESTART_MPI:
1201     case MB_CMD_IOP_PREP_LINK_DOWN:
1202         /* Drop the link, reload the routing
1203          * table when link comes up.
1204          */
1205         qlge_link_off(qdev);
1206         set_bit(QL_CAM_RT_SET, &qdev->flags);
1207         fallthrough;
1208     case MB_CMD_IOP_DVR_START:
1209     case MB_CMD_IOP_FLASH_ACC:
1210     case MB_CMD_IOP_CORE_DUMP_MPI:
1211     case MB_CMD_IOP_PREP_UPDATE_MPI:
1212     case MB_CMD_IOP_COMP_UPDATE_MPI:
1213     case MB_CMD_IOP_NONE:   /*  an IDC without params */
1214         /* Do ACK if required */
1215         if (timeout) {
1216             status = qlge_mb_idc_ack(qdev);
1217             if (status)
1218                 netif_err(qdev, drv, qdev->ndev,
1219                       "Bug: No pending IDC!\n");
1220         } else {
1221             netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
1222                      "IDC ACK not required\n");
1223             status = 0; /* success */
1224         }
1225         break;
1226     }
1227 }
1228 
1229 void qlge_mpi_work(struct work_struct *work)
1230 {
1231     struct qlge_adapter *qdev =
1232         container_of(work, struct qlge_adapter, mpi_work.work);
1233     struct mbox_params mbc;
1234     struct mbox_params *mbcp = &mbc;
1235     int err = 0;
1236 
1237     mutex_lock(&qdev->mpi_mutex);
1238     /* Begin polled mode for MPI */
1239     qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
1240 
1241     while (qlge_read32(qdev, STS) & STS_PI) {
1242         memset(mbcp, 0, sizeof(struct mbox_params));
1243         mbcp->out_count = 1;
1244         /* Don't continue if an async event
1245          * did not complete properly.
1246          */
1247         err = qlge_mpi_handler(qdev, mbcp);
1248         if (err)
1249             break;
1250     }
1251 
1252     /* End polled mode for MPI */
1253     qlge_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
1254     mutex_unlock(&qdev->mpi_mutex);
1255 }
1256 
1257 void qlge_mpi_reset_work(struct work_struct *work)
1258 {
1259     struct qlge_adapter *qdev =
1260         container_of(work, struct qlge_adapter, mpi_reset_work.work);
1261     cancel_delayed_work_sync(&qdev->mpi_work);
1262     cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
1263     cancel_delayed_work_sync(&qdev->mpi_idc_work);
1264     /* If we're not the dominant NIC function,
1265      * then there is nothing to do.
1266      */
1267     if (!qlge_own_firmware(qdev)) {
1268         netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n");
1269         return;
1270     }
1271 
1272     qlge_soft_reset_mpi_risc(qdev);
1273 }
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