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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * abstraction of the spi interface of HopeRf rf69 radio module
0004  *
0005  * Copyright (C) 2016 Wolf-Entwicklungen
0006  *  Marcus Wolf <linux@wolf-entwicklungen.de>
0007  */
0008 
0009 #include <linux/types.h>
0010 #include <linux/spi/spi.h>
0011 
0012 #include "rf69.h"
0013 #include "rf69_registers.h"
0014 
0015 #define F_OSC     32000000 /* in Hz */
0016 #define FIFO_SIZE 66       /* in byte */
0017 
0018 /*-------------------------------------------------------------------------*/
0019 
0020 u8 rf69_read_reg(struct spi_device *spi, u8 addr)
0021 {
0022     return spi_w8r8(spi, addr);
0023 }
0024 
0025 static int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value)
0026 {
0027     char buffer[2];
0028 
0029     buffer[0] = addr | WRITE_BIT;
0030     buffer[1] = value;
0031 
0032     return spi_write(spi, &buffer, ARRAY_SIZE(buffer));
0033 }
0034 
0035 /*-------------------------------------------------------------------------*/
0036 
0037 static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask)
0038 {
0039     u8 tmp;
0040 
0041     tmp = rf69_read_reg(spi, reg);
0042     tmp = tmp | mask;
0043     return rf69_write_reg(spi, reg, tmp);
0044 }
0045 
0046 static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask)
0047 {
0048     u8 tmp;
0049 
0050     tmp = rf69_read_reg(spi, reg);
0051     tmp = tmp & ~mask;
0052     return rf69_write_reg(spi, reg, tmp);
0053 }
0054 
0055 static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg,
0056                       u8 mask, u8 value)
0057 {
0058     u8 tmp;
0059 
0060     tmp = rf69_read_reg(spi, reg);
0061     tmp = (tmp & ~mask) | value;
0062     return rf69_write_reg(spi, reg, tmp);
0063 }
0064 
0065 /*-------------------------------------------------------------------------*/
0066 
0067 int rf69_get_version(struct spi_device *spi)
0068 {
0069     return rf69_read_reg(spi, REG_VERSION);
0070 }
0071 
0072 int rf69_set_mode(struct spi_device *spi, enum mode mode)
0073 {
0074     static const u8 mode_map[] = {
0075         [transmit] = OPMODE_MODE_TRANSMIT,
0076         [receive] = OPMODE_MODE_RECEIVE,
0077         [synthesizer] = OPMODE_MODE_SYNTHESIZER,
0078         [standby] = OPMODE_MODE_STANDBY,
0079         [mode_sleep] = OPMODE_MODE_SLEEP,
0080     };
0081 
0082     if (unlikely(mode >= ARRAY_SIZE(mode_map))) {
0083         dev_dbg(&spi->dev, "set: illegal mode %u\n", mode);
0084         return -EINVAL;
0085     }
0086 
0087     return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE,
0088                    mode_map[mode]);
0089 
0090     /*
0091      * we are using packet mode, so this check is not really needed
0092      * but waiting for mode ready is necessary when going from sleep
0093      * because the FIFO may not be immediately available from previous mode
0094      * while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) &
0095           RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady
0096      */
0097 }
0098 
0099 int rf69_set_data_mode(struct spi_device *spi, u8 data_mode)
0100 {
0101     return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODE,
0102                    data_mode);
0103 }
0104 
0105 int rf69_set_modulation(struct spi_device *spi, enum modulation modulation)
0106 {
0107     static const u8 modulation_map[] = {
0108         [OOK] = DATAMODUL_MODULATION_TYPE_OOK,
0109         [FSK] = DATAMODUL_MODULATION_TYPE_FSK,
0110     };
0111 
0112     if (unlikely(modulation >= ARRAY_SIZE(modulation_map))) {
0113         dev_dbg(&spi->dev, "set: illegal modulation %u\n", modulation);
0114         return -EINVAL;
0115     }
0116 
0117     return rf69_read_mod_write(spi, REG_DATAMODUL,
0118                    MASK_DATAMODUL_MODULATION_TYPE,
0119                    modulation_map[modulation]);
0120 }
0121 
0122 static enum modulation rf69_get_modulation(struct spi_device *spi)
0123 {
0124     u8 modulation_reg;
0125 
0126     modulation_reg = rf69_read_reg(spi, REG_DATAMODUL);
0127 
0128     switch (modulation_reg & MASK_DATAMODUL_MODULATION_TYPE) {
0129     case DATAMODUL_MODULATION_TYPE_OOK:
0130         return OOK;
0131     case DATAMODUL_MODULATION_TYPE_FSK:
0132         return FSK;
0133     default:
0134         return UNDEF;
0135     }
0136 }
0137 
0138 int rf69_set_modulation_shaping(struct spi_device *spi,
0139                 enum mod_shaping mod_shaping)
0140 {
0141     switch (rf69_get_modulation(spi)) {
0142     case FSK:
0143         switch (mod_shaping) {
0144         case SHAPING_OFF:
0145             return rf69_read_mod_write(spi, REG_DATAMODUL,
0146                            MASK_DATAMODUL_MODULATION_SHAPE,
0147                            DATAMODUL_MODULATION_SHAPE_NONE);
0148         case SHAPING_1_0:
0149             return rf69_read_mod_write(spi, REG_DATAMODUL,
0150                            MASK_DATAMODUL_MODULATION_SHAPE,
0151                            DATAMODUL_MODULATION_SHAPE_1_0);
0152         case SHAPING_0_5:
0153             return rf69_read_mod_write(spi, REG_DATAMODUL,
0154                            MASK_DATAMODUL_MODULATION_SHAPE,
0155                            DATAMODUL_MODULATION_SHAPE_0_5);
0156         case SHAPING_0_3:
0157             return rf69_read_mod_write(spi, REG_DATAMODUL,
0158                            MASK_DATAMODUL_MODULATION_SHAPE,
0159                            DATAMODUL_MODULATION_SHAPE_0_3);
0160         default:
0161             dev_dbg(&spi->dev, "set: illegal mod shaping for FSK %u\n", mod_shaping);
0162             return -EINVAL;
0163         }
0164     case OOK:
0165         switch (mod_shaping) {
0166         case SHAPING_OFF:
0167             return rf69_read_mod_write(spi, REG_DATAMODUL,
0168                            MASK_DATAMODUL_MODULATION_SHAPE,
0169                            DATAMODUL_MODULATION_SHAPE_NONE);
0170         case SHAPING_BR:
0171             return rf69_read_mod_write(spi, REG_DATAMODUL,
0172                            MASK_DATAMODUL_MODULATION_SHAPE,
0173                            DATAMODUL_MODULATION_SHAPE_BR);
0174         case SHAPING_2BR:
0175             return rf69_read_mod_write(spi, REG_DATAMODUL,
0176                            MASK_DATAMODUL_MODULATION_SHAPE,
0177                            DATAMODUL_MODULATION_SHAPE_2BR);
0178         default:
0179             dev_dbg(&spi->dev, "set: illegal mod shaping for OOK %u\n", mod_shaping);
0180             return -EINVAL;
0181         }
0182     default:
0183         dev_dbg(&spi->dev, "set: modulation undefined\n");
0184         return -EINVAL;
0185     }
0186 }
0187 
0188 int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate)
0189 {
0190     int retval;
0191     u32 bit_rate_reg;
0192     u8 msb;
0193     u8 lsb;
0194     enum modulation mod;
0195 
0196     // check if modulation is configured
0197     mod = rf69_get_modulation(spi);
0198     if (mod == UNDEF) {
0199         dev_dbg(&spi->dev, "setBitRate: modulation is undefined\n");
0200         return -EINVAL;
0201     }
0202 
0203     // check input value
0204     if (bit_rate < 1200 || (mod == OOK && bit_rate > 32768)) {
0205         dev_dbg(&spi->dev, "setBitRate: illegal input param\n");
0206         return -EINVAL;
0207     }
0208 
0209     // calculate reg settings
0210     bit_rate_reg = (F_OSC / bit_rate);
0211 
0212     msb = (bit_rate_reg & 0xff00) >> 8;
0213     lsb = (bit_rate_reg & 0xff);
0214 
0215     // transmit to RF 69
0216     retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb);
0217     if (retval)
0218         return retval;
0219     retval = rf69_write_reg(spi, REG_BITRATE_LSB, lsb);
0220     if (retval)
0221         return retval;
0222 
0223     return 0;
0224 }
0225 
0226 int rf69_set_deviation(struct spi_device *spi, u32 deviation)
0227 {
0228     int retval;
0229     u64 f_reg;
0230     u64 f_step;
0231     u32 bit_rate_reg;
0232     u32 bit_rate;
0233     u8 msb;
0234     u8 lsb;
0235     u64 factor = 1000000; // to improve precision of calculation
0236 
0237     // calculate bit rate
0238     bit_rate_reg = rf69_read_reg(spi, REG_BITRATE_MSB) << 8;
0239     bit_rate_reg |= rf69_read_reg(spi, REG_BITRATE_LSB);
0240     bit_rate = F_OSC / bit_rate_reg;
0241 
0242     /*
0243      * frequency deviation must exceed 600 Hz but not exceed
0244      * 500kHz when taking bitrate dependency into consideration
0245      * to ensure proper modulation
0246      */
0247     if (deviation < 600 || (deviation + (bit_rate / 2)) > 500000) {
0248         dev_dbg(&spi->dev,
0249             "set_deviation: illegal input param: %u\n", deviation);
0250         return -EINVAL;
0251     }
0252 
0253     // calculat f step
0254     f_step = F_OSC * factor;
0255     do_div(f_step, 524288); //  524288 = 2^19
0256 
0257     // calculate register settings
0258     f_reg = deviation * factor;
0259     do_div(f_reg, f_step);
0260 
0261     msb = (f_reg & 0xff00) >> 8;
0262     lsb = (f_reg & 0xff);
0263 
0264     // check msb
0265     if (msb & ~FDEVMASB_MASK) {
0266         dev_dbg(&spi->dev, "set_deviation: err in calc of msb\n");
0267         return -EINVAL;
0268     }
0269 
0270     // write to chip
0271     retval = rf69_write_reg(spi, REG_FDEV_MSB, msb);
0272     if (retval)
0273         return retval;
0274     retval = rf69_write_reg(spi, REG_FDEV_LSB, lsb);
0275     if (retval)
0276         return retval;
0277 
0278     return 0;
0279 }
0280 
0281 int rf69_set_frequency(struct spi_device *spi, u32 frequency)
0282 {
0283     int retval;
0284     u32 f_max;
0285     u64 f_reg;
0286     u64 f_step;
0287     u8 msb;
0288     u8 mid;
0289     u8 lsb;
0290     u64 factor = 1000000; // to improve precision of calculation
0291 
0292     // calculat f step
0293     f_step = F_OSC * factor;
0294     do_div(f_step, 524288); //  524288 = 2^19
0295 
0296     // check input value
0297     f_max = div_u64(f_step * 8388608, factor);
0298     if (frequency > f_max) {
0299         dev_dbg(&spi->dev, "setFrequency: illegal input param\n");
0300         return -EINVAL;
0301     }
0302 
0303     // calculate reg settings
0304     f_reg = frequency * factor;
0305     do_div(f_reg, f_step);
0306 
0307     msb = (f_reg & 0xff0000) >> 16;
0308     mid = (f_reg & 0xff00)   >>  8;
0309     lsb = (f_reg & 0xff);
0310 
0311     // write to chip
0312     retval = rf69_write_reg(spi, REG_FRF_MSB, msb);
0313     if (retval)
0314         return retval;
0315     retval = rf69_write_reg(spi, REG_FRF_MID, mid);
0316     if (retval)
0317         return retval;
0318     retval = rf69_write_reg(spi, REG_FRF_LSB, lsb);
0319     if (retval)
0320         return retval;
0321 
0322     return 0;
0323 }
0324 
0325 int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask)
0326 {
0327     return rf69_set_bit(spi, REG_PALEVEL, amplifier_mask);
0328 }
0329 
0330 int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask)
0331 {
0332     return rf69_clear_bit(spi, REG_PALEVEL, amplifier_mask);
0333 }
0334 
0335 int rf69_set_output_power_level(struct spi_device *spi, u8 power_level)
0336 {
0337     u8 pa_level, ocp, test_pa1, test_pa2;
0338     bool pa0, pa1, pa2, high_power;
0339     u8 min_power_level;
0340 
0341     // check register pa_level
0342     pa_level = rf69_read_reg(spi, REG_PALEVEL);
0343     pa0 = pa_level & MASK_PALEVEL_PA0;
0344     pa1 = pa_level & MASK_PALEVEL_PA1;
0345     pa2 = pa_level & MASK_PALEVEL_PA2;
0346 
0347     // check high power mode
0348     ocp = rf69_read_reg(spi, REG_OCP);
0349     test_pa1 = rf69_read_reg(spi, REG_TESTPA1);
0350     test_pa2 = rf69_read_reg(spi, REG_TESTPA2);
0351     high_power = (ocp == 0x0f) && (test_pa1 == 0x5d) && (test_pa2 == 0x7c);
0352 
0353     if (pa0 && !pa1 && !pa2) {
0354         power_level += 18;
0355         min_power_level = 0;
0356     } else if (!pa0 && pa1 && !pa2) {
0357         power_level += 18;
0358         min_power_level = 16;
0359     } else if (!pa0 && pa1 && pa2) {
0360         if (high_power)
0361             power_level += 11;
0362         else
0363             power_level += 14;
0364         min_power_level = 16;
0365     } else {
0366         goto failed;
0367     }
0368 
0369     // check input value
0370     if (power_level > 0x1f)
0371         goto failed;
0372 
0373     if (power_level < min_power_level)
0374         goto failed;
0375 
0376     // write value
0377     return rf69_read_mod_write(spi, REG_PALEVEL, MASK_PALEVEL_OUTPUT_POWER,
0378                    power_level);
0379 failed:
0380     dev_dbg(&spi->dev, "set: illegal power level %u\n", power_level);
0381     return -EINVAL;
0382 }
0383 
0384 int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp)
0385 {
0386     static const u8 pa_ramp_map[] = {
0387         [ramp3400] = PARAMP_3400,
0388         [ramp2000] = PARAMP_2000,
0389         [ramp1000] = PARAMP_1000,
0390         [ramp500] = PARAMP_500,
0391         [ramp250] = PARAMP_250,
0392         [ramp125] = PARAMP_125,
0393         [ramp100] = PARAMP_100,
0394         [ramp62] = PARAMP_62,
0395         [ramp50] = PARAMP_50,
0396         [ramp40] = PARAMP_40,
0397         [ramp31] = PARAMP_31,
0398         [ramp25] = PARAMP_25,
0399         [ramp20] = PARAMP_20,
0400         [ramp15] = PARAMP_15,
0401         [ramp10] = PARAMP_10,
0402     };
0403 
0404     if (unlikely(pa_ramp >= ARRAY_SIZE(pa_ramp_map))) {
0405         dev_dbg(&spi->dev, "set: illegal pa_ramp %u\n", pa_ramp);
0406         return -EINVAL;
0407     }
0408 
0409     return rf69_write_reg(spi, REG_PARAMP, pa_ramp_map[pa_ramp]);
0410 }
0411 
0412 int rf69_set_antenna_impedance(struct spi_device *spi,
0413                    enum antenna_impedance antenna_impedance)
0414 {
0415     switch (antenna_impedance) {
0416     case fifty_ohm:
0417         return rf69_clear_bit(spi, REG_LNA, MASK_LNA_ZIN);
0418     case two_hundred_ohm:
0419         return rf69_set_bit(spi, REG_LNA, MASK_LNA_ZIN);
0420     default:
0421         dev_dbg(&spi->dev, "set: illegal antenna impedance %u\n", antenna_impedance);
0422         return -EINVAL;
0423     }
0424 }
0425 
0426 int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain)
0427 {
0428     static const u8 lna_gain_map[] = {
0429         [automatic] = LNA_GAIN_AUTO,
0430         [max] = LNA_GAIN_MAX,
0431         [max_minus_6] = LNA_GAIN_MAX_MINUS_6,
0432         [max_minus_12] = LNA_GAIN_MAX_MINUS_12,
0433         [max_minus_24] = LNA_GAIN_MAX_MINUS_24,
0434         [max_minus_36] = LNA_GAIN_MAX_MINUS_36,
0435         [max_minus_48] = LNA_GAIN_MAX_MINUS_48,
0436     };
0437 
0438     if (unlikely(lna_gain >= ARRAY_SIZE(lna_gain_map))) {
0439         dev_dbg(&spi->dev, "set: illegal lna gain %u\n", lna_gain);
0440         return -EINVAL;
0441     }
0442 
0443     return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN,
0444                    lna_gain_map[lna_gain]);
0445 }
0446 
0447 static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg,
0448                      enum mantisse mantisse, u8 exponent)
0449 {
0450     u8 bandwidth;
0451 
0452     // check value for mantisse and exponent
0453     if (exponent > 7) {
0454         dev_dbg(&spi->dev, "set: illegal bandwidth exponent %u\n", exponent);
0455         return -EINVAL;
0456     }
0457 
0458     if (mantisse != mantisse16 &&
0459         mantisse != mantisse20 &&
0460         mantisse != mantisse24) {
0461         dev_dbg(&spi->dev, "set: illegal bandwidth mantisse %u\n", mantisse);
0462         return -EINVAL;
0463     }
0464 
0465     // read old value
0466     bandwidth = rf69_read_reg(spi, reg);
0467 
0468     // "delete" mantisse and exponent = just keep the DCC setting
0469     bandwidth = bandwidth & MASK_BW_DCC_FREQ;
0470 
0471     // add new mantisse
0472     switch (mantisse) {
0473     case mantisse16:
0474         bandwidth = bandwidth | BW_MANT_16;
0475         break;
0476     case mantisse20:
0477         bandwidth = bandwidth | BW_MANT_20;
0478         break;
0479     case mantisse24:
0480         bandwidth = bandwidth | BW_MANT_24;
0481         break;
0482     }
0483 
0484     // add new exponent
0485     bandwidth = bandwidth | exponent;
0486 
0487     // write back
0488     return rf69_write_reg(spi, reg, bandwidth);
0489 }
0490 
0491 int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse,
0492                u8 exponent)
0493 {
0494     return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent);
0495 }
0496 
0497 int rf69_set_bandwidth_during_afc(struct spi_device *spi,
0498                   enum mantisse mantisse,
0499                   u8 exponent)
0500 {
0501     return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent);
0502 }
0503 
0504 int rf69_set_ook_threshold_dec(struct spi_device *spi,
0505                    enum threshold_decrement threshold_decrement)
0506 {
0507     static const u8 td_map[] = {
0508         [dec_every8th] = OOKPEAK_THRESHDEC_EVERY_8TH,
0509         [dec_every4th] = OOKPEAK_THRESHDEC_EVERY_4TH,
0510         [dec_every2nd] = OOKPEAK_THRESHDEC_EVERY_2ND,
0511         [dec_once] = OOKPEAK_THRESHDEC_ONCE,
0512         [dec_twice] = OOKPEAK_THRESHDEC_TWICE,
0513         [dec_4times] = OOKPEAK_THRESHDEC_4_TIMES,
0514         [dec_8times] = OOKPEAK_THRESHDEC_8_TIMES,
0515         [dec_16times] = OOKPEAK_THRESHDEC_16_TIMES,
0516     };
0517 
0518     if (unlikely(threshold_decrement >= ARRAY_SIZE(td_map))) {
0519         dev_dbg(&spi->dev, "set: illegal OOK threshold decrement %u\n",
0520             threshold_decrement);
0521         return -EINVAL;
0522     }
0523 
0524     return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC,
0525                    td_map[threshold_decrement]);
0526 }
0527 
0528 int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value)
0529 {
0530     u8 mask;
0531     u8 shift;
0532     u8 dio_addr;
0533     u8 dio_value;
0534 
0535     switch (dio_number) {
0536     case 0:
0537         mask = MASK_DIO0;
0538         shift = SHIFT_DIO0;
0539         dio_addr = REG_DIOMAPPING1;
0540         break;
0541     case 1:
0542         mask = MASK_DIO1;
0543         shift = SHIFT_DIO1;
0544         dio_addr = REG_DIOMAPPING1;
0545         break;
0546     case 2:
0547         mask = MASK_DIO2;
0548         shift = SHIFT_DIO2;
0549         dio_addr = REG_DIOMAPPING1;
0550         break;
0551     case 3:
0552         mask = MASK_DIO3;
0553         shift = SHIFT_DIO3;
0554         dio_addr = REG_DIOMAPPING1;
0555         break;
0556     case 4:
0557         mask = MASK_DIO4;
0558         shift = SHIFT_DIO4;
0559         dio_addr = REG_DIOMAPPING2;
0560         break;
0561     case 5:
0562         mask = MASK_DIO5;
0563         shift = SHIFT_DIO5;
0564         dio_addr = REG_DIOMAPPING2;
0565         break;
0566     default:
0567         dev_dbg(&spi->dev, "set: illegal dio number %u\n", dio_number);
0568         return -EINVAL;
0569     }
0570 
0571     // read reg
0572     dio_value = rf69_read_reg(spi, dio_addr);
0573     // delete old value
0574     dio_value = dio_value & ~mask;
0575     // add new value
0576     dio_value = dio_value | value << shift;
0577     // write back
0578     return rf69_write_reg(spi, dio_addr, dio_value);
0579 }
0580 
0581 int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold)
0582 {
0583     /* no value check needed - u8 exactly matches register size */
0584 
0585     return rf69_write_reg(spi, REG_RSSITHRESH, threshold);
0586 }
0587 
0588 int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length)
0589 {
0590     int retval;
0591     u8 msb, lsb;
0592 
0593     /* no value check needed - u16 exactly matches register size */
0594 
0595     /* calculate reg settings */
0596     msb = (preamble_length & 0xff00) >> 8;
0597     lsb = (preamble_length & 0xff);
0598 
0599     /* transmit to chip */
0600     retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb);
0601     if (retval)
0602         return retval;
0603     return rf69_write_reg(spi, REG_PREAMBLE_LSB, lsb);
0604 }
0605 
0606 int rf69_enable_sync(struct spi_device *spi)
0607 {
0608     return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON);
0609 }
0610 
0611 int rf69_disable_sync(struct spi_device *spi)
0612 {
0613     return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON);
0614 }
0615 
0616 int rf69_set_fifo_fill_condition(struct spi_device *spi,
0617                  enum fifo_fill_condition fifo_fill_condition)
0618 {
0619     switch (fifo_fill_condition) {
0620     case always:
0621         return rf69_set_bit(spi, REG_SYNC_CONFIG,
0622                     MASK_SYNC_CONFIG_FIFO_FILL_CONDITION);
0623     case after_sync_interrupt:
0624         return rf69_clear_bit(spi, REG_SYNC_CONFIG,
0625                       MASK_SYNC_CONFIG_FIFO_FILL_CONDITION);
0626     default:
0627         dev_dbg(&spi->dev, "set: illegal fifo fill condition %u\n", fifo_fill_condition);
0628         return -EINVAL;
0629     }
0630 }
0631 
0632 int rf69_set_sync_size(struct spi_device *spi, u8 sync_size)
0633 {
0634     // check input value
0635     if (sync_size > 0x07) {
0636         dev_dbg(&spi->dev, "set: illegal sync size %u\n", sync_size);
0637         return -EINVAL;
0638     }
0639 
0640     // write value
0641     return rf69_read_mod_write(spi, REG_SYNC_CONFIG,
0642                    MASK_SYNC_CONFIG_SYNC_SIZE,
0643                    (sync_size << 3));
0644 }
0645 
0646 int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8])
0647 {
0648     int retval = 0;
0649 
0650     retval += rf69_write_reg(spi, REG_SYNCVALUE1, sync_values[0]);
0651     retval += rf69_write_reg(spi, REG_SYNCVALUE2, sync_values[1]);
0652     retval += rf69_write_reg(spi, REG_SYNCVALUE3, sync_values[2]);
0653     retval += rf69_write_reg(spi, REG_SYNCVALUE4, sync_values[3]);
0654     retval += rf69_write_reg(spi, REG_SYNCVALUE5, sync_values[4]);
0655     retval += rf69_write_reg(spi, REG_SYNCVALUE6, sync_values[5]);
0656     retval += rf69_write_reg(spi, REG_SYNCVALUE7, sync_values[6]);
0657     retval += rf69_write_reg(spi, REG_SYNCVALUE8, sync_values[7]);
0658 
0659     return retval;
0660 }
0661 
0662 int rf69_set_packet_format(struct spi_device *spi,
0663                enum packet_format packet_format)
0664 {
0665     switch (packet_format) {
0666     case packet_length_var:
0667         return rf69_set_bit(spi, REG_PACKETCONFIG1,
0668                     MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE);
0669     case packet_length_fix:
0670         return rf69_clear_bit(spi, REG_PACKETCONFIG1,
0671                       MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE);
0672     default:
0673         dev_dbg(&spi->dev, "set: illegal packet format %u\n", packet_format);
0674         return -EINVAL;
0675     }
0676 }
0677 
0678 int rf69_enable_crc(struct spi_device *spi)
0679 {
0680     return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON);
0681 }
0682 
0683 int rf69_disable_crc(struct spi_device *spi)
0684 {
0685     return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON);
0686 }
0687 
0688 int rf69_set_address_filtering(struct spi_device *spi,
0689                    enum address_filtering address_filtering)
0690 {
0691     static const u8 af_map[] = {
0692         [filtering_off] = PACKETCONFIG1_ADDRESSFILTERING_OFF,
0693         [node_address] = PACKETCONFIG1_ADDRESSFILTERING_NODE,
0694         [node_or_broadcast_address] =
0695             PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST,
0696     };
0697 
0698     if (unlikely(address_filtering >= ARRAY_SIZE(af_map))) {
0699         dev_dbg(&spi->dev, "set: illegal address filtering %u\n", address_filtering);
0700         return -EINVAL;
0701     }
0702 
0703     return rf69_read_mod_write(spi, REG_PACKETCONFIG1,
0704                    MASK_PACKETCONFIG1_ADDRESSFILTERING,
0705                    af_map[address_filtering]);
0706 }
0707 
0708 int rf69_set_payload_length(struct spi_device *spi, u8 payload_length)
0709 {
0710     return rf69_write_reg(spi, REG_PAYLOAD_LENGTH, payload_length);
0711 }
0712 
0713 int rf69_set_node_address(struct spi_device *spi, u8 node_address)
0714 {
0715     return rf69_write_reg(spi, REG_NODEADRS, node_address);
0716 }
0717 
0718 int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address)
0719 {
0720     return rf69_write_reg(spi, REG_BROADCASTADRS, broadcast_address);
0721 }
0722 
0723 int rf69_set_tx_start_condition(struct spi_device *spi,
0724                 enum tx_start_condition tx_start_condition)
0725 {
0726     switch (tx_start_condition) {
0727     case fifo_level:
0728         return rf69_clear_bit(spi, REG_FIFO_THRESH,
0729                       MASK_FIFO_THRESH_TXSTART);
0730     case fifo_not_empty:
0731         return rf69_set_bit(spi, REG_FIFO_THRESH,
0732                     MASK_FIFO_THRESH_TXSTART);
0733     default:
0734         dev_dbg(&spi->dev, "set: illegal tx start condition %u\n", tx_start_condition);
0735         return -EINVAL;
0736     }
0737 }
0738 
0739 int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold)
0740 {
0741     int retval;
0742 
0743     /* check input value */
0744     if (threshold & ~MASK_FIFO_THRESH_VALUE) {
0745         dev_dbg(&spi->dev, "set: illegal fifo threshold %u\n", threshold);
0746         return -EINVAL;
0747     }
0748 
0749     /* write value */
0750     retval = rf69_read_mod_write(spi, REG_FIFO_THRESH,
0751                      MASK_FIFO_THRESH_VALUE,
0752                      threshold);
0753     if (retval)
0754         return retval;
0755 
0756     /*
0757      * access the fifo to activate new threshold
0758      * retval (mis-) used as buffer here
0759      */
0760     return rf69_read_fifo(spi, (u8 *)&retval, 1);
0761 }
0762 
0763 int rf69_set_dagc(struct spi_device *spi, enum dagc dagc)
0764 {
0765     static const u8 dagc_map[] = {
0766         [normal_mode] = DAGC_NORMAL,
0767         [improve] = DAGC_IMPROVED_LOWBETA0,
0768         [improve_for_low_modulation_index] = DAGC_IMPROVED_LOWBETA1,
0769     };
0770 
0771     if (unlikely(dagc >= ARRAY_SIZE(dagc_map))) {
0772         dev_dbg(&spi->dev, "set: illegal dagc %u\n", dagc);
0773         return -EINVAL;
0774     }
0775 
0776     return rf69_write_reg(spi, REG_TESTDAGC, dagc_map[dagc]);
0777 }
0778 
0779 /*-------------------------------------------------------------------------*/
0780 
0781 int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size)
0782 {
0783     int i;
0784     struct spi_transfer transfer;
0785     u8 local_buffer[FIFO_SIZE + 1] = {};
0786     int retval;
0787 
0788     if (size > FIFO_SIZE) {
0789         dev_dbg(&spi->dev,
0790             "read fifo: passed in buffer bigger then internal buffer\n");
0791         return -EMSGSIZE;
0792     }
0793 
0794     /* prepare a bidirectional transfer */
0795     local_buffer[0] = REG_FIFO;
0796     memset(&transfer, 0, sizeof(transfer));
0797     transfer.tx_buf = local_buffer;
0798     transfer.rx_buf = local_buffer;
0799     transfer.len    = size + 1;
0800 
0801     retval = spi_sync_transfer(spi, &transfer, 1);
0802 
0803     /* print content read from fifo for debugging purposes */
0804     for (i = 0; i < size; i++)
0805         dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]);
0806 
0807     memcpy(buffer, &local_buffer[1], size);
0808 
0809     return retval;
0810 }
0811 
0812 int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size)
0813 {
0814     int i;
0815     u8 local_buffer[FIFO_SIZE + 1];
0816 
0817     if (size > FIFO_SIZE) {
0818         dev_dbg(&spi->dev,
0819             "read fifo: passed in buffer bigger then internal buffer\n");
0820         return -EMSGSIZE;
0821     }
0822 
0823     local_buffer[0] = REG_FIFO | WRITE_BIT;
0824     memcpy(&local_buffer[1], buffer, size);
0825 
0826     /* print content written from fifo for debugging purposes */
0827     for (i = 0; i < size; i++)
0828         dev_dbg(&spi->dev, "%d - 0x%x\n", i, buffer[i]);
0829 
0830     return spi_write(spi, local_buffer, size + 1);
0831 }
0832
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