0001
0002 #define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 512
0003
0004 #ifndef XKPHYS_TO_PHYS
0005 # define XKPHYS_TO_PHYS(p) (p)
0006 #endif
0007
0008 #define OCTEON_IRQ_WORKQ0 0
0009 #define OCTEON_IRQ_RML 0
0010 #define OCTEON_IRQ_TIMER1 0
0011 #define OCTEON_IS_MODEL(x) 0
0012 #define octeon_has_feature(x) 0
0013 #define octeon_get_clock_rate() 0
0014
0015 #define CVMX_SYNCIOBDMA do { } while (0)
0016
0017 #define CVMX_HELPER_INPUT_TAG_TYPE 0
0018 #define CVMX_HELPER_FIRST_MBUFF_SKIP 7
0019 #define CVMX_FAU_REG_END (2048)
0020 #define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
0021 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 16
0022 #define CVMX_FPA_PACKET_POOL (0)
0023 #define CVMX_FPA_PACKET_POOL_SIZE 16
0024 #define CVMX_FPA_WQE_POOL (1)
0025 #define CVMX_FPA_WQE_POOL_SIZE 16
0026 #define CVMX_GMXX_RXX_ADR_CAM_EN(a, b) ((a) + (b))
0027 #define CVMX_GMXX_RXX_ADR_CTL(a, b) ((a) + (b))
0028 #define CVMX_GMXX_PRTX_CFG(a, b) ((a) + (b))
0029 #define CVMX_GMXX_RXX_FRM_MAX(a, b) ((a) + (b))
0030 #define CVMX_GMXX_RXX_JABBER(a, b) ((a) + (b))
0031 #define CVMX_IPD_CTL_STATUS 0
0032 #define CVMX_PIP_FRM_LEN_CHKX(a) (a)
0033 #define CVMX_PIP_NUM_INPUT_PORTS 1
0034 #define CVMX_SCR_SCRATCH 0
0035 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 2
0036 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 2
0037 #define CVMX_IPD_SUB_PORT_FCS 0
0038 #define CVMX_SSO_WQ_IQ_DIS 0
0039 #define CVMX_SSO_WQ_INT 0
0040 #define CVMX_POW_WQ_INT 0
0041 #define CVMX_SSO_WQ_INT_PC 0
0042 #define CVMX_NPI_RSL_INT_BLOCKS 0
0043 #define CVMX_POW_WQ_INT_PC 0
0044
0045 union cvmx_pip_wqe_word2 {
0046 uint64_t u64;
0047 struct {
0048 uint64_t bufs:8;
0049 uint64_t ip_offset:8;
0050 uint64_t vlan_valid:1;
0051 uint64_t vlan_stacked:1;
0052 uint64_t unassigned:1;
0053 uint64_t vlan_cfi:1;
0054 uint64_t vlan_id:12;
0055 uint64_t pr:4;
0056 uint64_t unassigned2:8;
0057 uint64_t dec_ipcomp:1;
0058 uint64_t tcp_or_udp:1;
0059 uint64_t dec_ipsec:1;
0060 uint64_t is_v6:1;
0061 uint64_t software:1;
0062 uint64_t L4_error:1;
0063 uint64_t is_frag:1;
0064 uint64_t IP_exc:1;
0065 uint64_t is_bcast:1;
0066 uint64_t is_mcast:1;
0067 uint64_t not_IP:1;
0068 uint64_t rcv_error:1;
0069 uint64_t err_code:8;
0070 } s;
0071 struct {
0072 uint64_t bufs:8;
0073 uint64_t ip_offset:8;
0074 uint64_t vlan_valid:1;
0075 uint64_t vlan_stacked:1;
0076 uint64_t unassigned:1;
0077 uint64_t vlan_cfi:1;
0078 uint64_t vlan_id:12;
0079 uint64_t port:12;
0080 uint64_t dec_ipcomp:1;
0081 uint64_t tcp_or_udp:1;
0082 uint64_t dec_ipsec:1;
0083 uint64_t is_v6:1;
0084 uint64_t software:1;
0085 uint64_t L4_error:1;
0086 uint64_t is_frag:1;
0087 uint64_t IP_exc:1;
0088 uint64_t is_bcast:1;
0089 uint64_t is_mcast:1;
0090 uint64_t not_IP:1;
0091 uint64_t rcv_error:1;
0092 uint64_t err_code:8;
0093 } s_cn68xx;
0094
0095 struct {
0096 uint64_t unused1:16;
0097 uint64_t vlan:16;
0098 uint64_t unused2:32;
0099 } svlan;
0100 struct {
0101 uint64_t bufs:8;
0102 uint64_t unused:8;
0103 uint64_t vlan_valid:1;
0104 uint64_t vlan_stacked:1;
0105 uint64_t unassigned:1;
0106 uint64_t vlan_cfi:1;
0107 uint64_t vlan_id:12;
0108 uint64_t pr:4;
0109 uint64_t unassigned2:12;
0110 uint64_t software:1;
0111 uint64_t unassigned3:1;
0112 uint64_t is_rarp:1;
0113 uint64_t is_arp:1;
0114 uint64_t is_bcast:1;
0115 uint64_t is_mcast:1;
0116 uint64_t not_IP:1;
0117 uint64_t rcv_error:1;
0118 uint64_t err_code:8;
0119 } snoip;
0120
0121 };
0122
0123 union cvmx_pip_wqe_word0 {
0124 struct {
0125 uint64_t next_ptr:40;
0126 uint8_t unused;
0127 __wsum hw_chksum;
0128 } cn38xx;
0129 struct {
0130 uint64_t pknd:6;
0131 uint64_t unused2:2;
0132 uint64_t bpid:6;
0133 uint64_t unused1:18;
0134 uint64_t l2ptr:8;
0135 uint64_t l3ptr:8;
0136 uint64_t unused0:8;
0137 uint64_t l4ptr:8;
0138 } cn68xx;
0139 };
0140
0141 union cvmx_wqe_word0 {
0142 uint64_t u64;
0143 union cvmx_pip_wqe_word0 pip;
0144 };
0145
0146 union cvmx_wqe_word1 {
0147 uint64_t u64;
0148 struct {
0149 uint64_t tag:32;
0150 uint64_t tag_type:2;
0151 uint64_t varies:14;
0152 uint64_t len:16;
0153 };
0154 struct {
0155 uint64_t tag:32;
0156 uint64_t tag_type:2;
0157 uint64_t zero_2:3;
0158 uint64_t grp:6;
0159 uint64_t zero_1:1;
0160 uint64_t qos:3;
0161 uint64_t zero_0:1;
0162 uint64_t len:16;
0163 } cn68xx;
0164 struct {
0165 uint64_t tag:32;
0166 uint64_t tag_type:2;
0167 uint64_t zero_2:1;
0168 uint64_t grp:4;
0169 uint64_t qos:3;
0170 uint64_t ipprt:6;
0171 uint64_t len:16;
0172 } cn38xx;
0173 };
0174
0175 union cvmx_buf_ptr {
0176 void *ptr;
0177 uint64_t u64;
0178 struct {
0179 uint64_t i:1;
0180 uint64_t back:4;
0181 uint64_t pool:3;
0182 uint64_t size:16;
0183 uint64_t addr:40;
0184 } s;
0185 };
0186
0187 struct cvmx_wqe {
0188 union cvmx_wqe_word0 word0;
0189 union cvmx_wqe_word1 word1;
0190 union cvmx_pip_wqe_word2 word2;
0191 union cvmx_buf_ptr packet_ptr;
0192 uint8_t packet_data[96];
0193 };
0194
0195 union cvmx_helper_link_info {
0196 uint64_t u64;
0197 struct {
0198 uint64_t reserved_20_63:44;
0199 uint64_t link_up:1;
0200 uint64_t full_duplex:1;
0201 uint64_t speed:18;
0202 } s;
0203 };
0204
0205 enum cvmx_fau_reg_32 {
0206 CVMX_FAU_REG_32_START = 0,
0207 };
0208
0209 enum cvmx_fau_op_size {
0210 CVMX_FAU_OP_SIZE_8 = 0,
0211 CVMX_FAU_OP_SIZE_16 = 1,
0212 CVMX_FAU_OP_SIZE_32 = 2,
0213 CVMX_FAU_OP_SIZE_64 = 3
0214 };
0215
0216 typedef enum {
0217 CVMX_SPI_MODE_UNKNOWN = 0,
0218 CVMX_SPI_MODE_TX_HALFPLEX = 1,
0219 CVMX_SPI_MODE_RX_HALFPLEX = 2,
0220 CVMX_SPI_MODE_DUPLEX = 3
0221 } cvmx_spi_mode_t;
0222
0223 typedef enum {
0224 CVMX_HELPER_INTERFACE_MODE_DISABLED,
0225 CVMX_HELPER_INTERFACE_MODE_RGMII,
0226 CVMX_HELPER_INTERFACE_MODE_GMII,
0227 CVMX_HELPER_INTERFACE_MODE_SPI,
0228 CVMX_HELPER_INTERFACE_MODE_PCIE,
0229 CVMX_HELPER_INTERFACE_MODE_XAUI,
0230 CVMX_HELPER_INTERFACE_MODE_SGMII,
0231 CVMX_HELPER_INTERFACE_MODE_PICMG,
0232 CVMX_HELPER_INTERFACE_MODE_NPI,
0233 CVMX_HELPER_INTERFACE_MODE_LOOP,
0234 } cvmx_helper_interface_mode_t;
0235
0236 typedef enum {
0237 CVMX_POW_WAIT = 1,
0238 CVMX_POW_NO_WAIT = 0,
0239 } cvmx_pow_wait_t;
0240
0241 typedef enum {
0242 CVMX_PKO_LOCK_NONE = 0,
0243 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
0244 CVMX_PKO_LOCK_CMD_QUEUE = 2,
0245 } cvmx_pko_lock_t;
0246
0247 typedef enum {
0248 CVMX_PKO_SUCCESS,
0249 CVMX_PKO_INVALID_PORT,
0250 CVMX_PKO_INVALID_QUEUE,
0251 CVMX_PKO_INVALID_PRIORITY,
0252 CVMX_PKO_NO_MEMORY,
0253 CVMX_PKO_PORT_ALREADY_SETUP,
0254 CVMX_PKO_CMD_QUEUE_INIT_ERROR
0255 } cvmx_pko_status_t;
0256
0257 enum cvmx_pow_tag_type {
0258 CVMX_POW_TAG_TYPE_ORDERED = 0L,
0259 CVMX_POW_TAG_TYPE_ATOMIC = 1L,
0260 CVMX_POW_TAG_TYPE_NULL = 2L,
0261 CVMX_POW_TAG_TYPE_NULL_NULL = 3L
0262 };
0263
0264 union cvmx_ipd_ctl_status {
0265 uint64_t u64;
0266 struct cvmx_ipd_ctl_status_s {
0267 uint64_t reserved_18_63:46;
0268 uint64_t use_sop:1;
0269 uint64_t rst_done:1;
0270 uint64_t clken:1;
0271 uint64_t no_wptr:1;
0272 uint64_t pq_apkt:1;
0273 uint64_t pq_nabuf:1;
0274 uint64_t ipd_full:1;
0275 uint64_t pkt_off:1;
0276 uint64_t len_m8:1;
0277 uint64_t reset:1;
0278 uint64_t addpkt:1;
0279 uint64_t naddbuf:1;
0280 uint64_t pkt_lend:1;
0281 uint64_t wqe_lend:1;
0282 uint64_t pbp_en:1;
0283 uint64_t opc_mode:2;
0284 uint64_t ipd_en:1;
0285 } s;
0286 struct cvmx_ipd_ctl_status_cn30xx {
0287 uint64_t reserved_10_63:54;
0288 uint64_t len_m8:1;
0289 uint64_t reset:1;
0290 uint64_t addpkt:1;
0291 uint64_t naddbuf:1;
0292 uint64_t pkt_lend:1;
0293 uint64_t wqe_lend:1;
0294 uint64_t pbp_en:1;
0295 uint64_t opc_mode:2;
0296 uint64_t ipd_en:1;
0297 } cn30xx;
0298 struct cvmx_ipd_ctl_status_cn38xxp2 {
0299 uint64_t reserved_9_63:55;
0300 uint64_t reset:1;
0301 uint64_t addpkt:1;
0302 uint64_t naddbuf:1;
0303 uint64_t pkt_lend:1;
0304 uint64_t wqe_lend:1;
0305 uint64_t pbp_en:1;
0306 uint64_t opc_mode:2;
0307 uint64_t ipd_en:1;
0308 } cn38xxp2;
0309 struct cvmx_ipd_ctl_status_cn50xx {
0310 uint64_t reserved_15_63:49;
0311 uint64_t no_wptr:1;
0312 uint64_t pq_apkt:1;
0313 uint64_t pq_nabuf:1;
0314 uint64_t ipd_full:1;
0315 uint64_t pkt_off:1;
0316 uint64_t len_m8:1;
0317 uint64_t reset:1;
0318 uint64_t addpkt:1;
0319 uint64_t naddbuf:1;
0320 uint64_t pkt_lend:1;
0321 uint64_t wqe_lend:1;
0322 uint64_t pbp_en:1;
0323 uint64_t opc_mode:2;
0324 uint64_t ipd_en:1;
0325 } cn50xx;
0326 struct cvmx_ipd_ctl_status_cn58xx {
0327 uint64_t reserved_12_63:52;
0328 uint64_t ipd_full:1;
0329 uint64_t pkt_off:1;
0330 uint64_t len_m8:1;
0331 uint64_t reset:1;
0332 uint64_t addpkt:1;
0333 uint64_t naddbuf:1;
0334 uint64_t pkt_lend:1;
0335 uint64_t wqe_lend:1;
0336 uint64_t pbp_en:1;
0337 uint64_t opc_mode:2;
0338 uint64_t ipd_en:1;
0339 } cn58xx;
0340 struct cvmx_ipd_ctl_status_cn63xxp1 {
0341 uint64_t reserved_16_63:48;
0342 uint64_t clken:1;
0343 uint64_t no_wptr:1;
0344 uint64_t pq_apkt:1;
0345 uint64_t pq_nabuf:1;
0346 uint64_t ipd_full:1;
0347 uint64_t pkt_off:1;
0348 uint64_t len_m8:1;
0349 uint64_t reset:1;
0350 uint64_t addpkt:1;
0351 uint64_t naddbuf:1;
0352 uint64_t pkt_lend:1;
0353 uint64_t wqe_lend:1;
0354 uint64_t pbp_en:1;
0355 uint64_t opc_mode:2;
0356 uint64_t ipd_en:1;
0357 } cn63xxp1;
0358 };
0359
0360 union cvmx_ipd_sub_port_fcs {
0361 uint64_t u64;
0362 struct cvmx_ipd_sub_port_fcs_s {
0363 uint64_t port_bit:32;
0364 uint64_t reserved_32_35:4;
0365 uint64_t port_bit2:4;
0366 uint64_t reserved_40_63:24;
0367 } s;
0368 struct cvmx_ipd_sub_port_fcs_cn30xx {
0369 uint64_t port_bit:3;
0370 uint64_t reserved_3_63:61;
0371 } cn30xx;
0372 struct cvmx_ipd_sub_port_fcs_cn38xx {
0373 uint64_t port_bit:32;
0374 uint64_t reserved_32_63:32;
0375 } cn38xx;
0376 };
0377
0378 union cvmx_ipd_sub_port_qos_cnt {
0379 uint64_t u64;
0380 struct cvmx_ipd_sub_port_qos_cnt_s {
0381 uint64_t cnt:32;
0382 uint64_t port_qos:9;
0383 uint64_t reserved_41_63:23;
0384 } s;
0385 };
0386
0387 typedef struct {
0388 uint32_t dropped_octets;
0389 uint32_t dropped_packets;
0390 uint32_t pci_raw_packets;
0391 uint32_t octets;
0392 uint32_t packets;
0393 uint32_t multicast_packets;
0394 uint32_t broadcast_packets;
0395 uint32_t len_64_packets;
0396 uint32_t len_65_127_packets;
0397 uint32_t len_128_255_packets;
0398 uint32_t len_256_511_packets;
0399 uint32_t len_512_1023_packets;
0400 uint32_t len_1024_1518_packets;
0401 uint32_t len_1519_max_packets;
0402 uint32_t fcs_align_err_packets;
0403 uint32_t runt_packets;
0404 uint32_t runt_crc_packets;
0405 uint32_t oversize_packets;
0406 uint32_t oversize_crc_packets;
0407 uint32_t inb_packets;
0408 uint64_t inb_octets;
0409 uint16_t inb_errors;
0410 } cvmx_pip_port_status_t;
0411
0412 typedef struct {
0413 uint32_t packets;
0414 uint64_t octets;
0415 uint64_t doorbell;
0416 } cvmx_pko_port_status_t;
0417
0418 union cvmx_pip_frm_len_chkx {
0419 uint64_t u64;
0420 struct cvmx_pip_frm_len_chkx_s {
0421 uint64_t reserved_32_63:32;
0422 uint64_t maxlen:16;
0423 uint64_t minlen:16;
0424 } s;
0425 };
0426
0427 union cvmx_gmxx_rxx_frm_ctl {
0428 uint64_t u64;
0429 struct cvmx_gmxx_rxx_frm_ctl_s {
0430 uint64_t pre_chk:1;
0431 uint64_t pre_strp:1;
0432 uint64_t ctl_drp:1;
0433 uint64_t ctl_bck:1;
0434 uint64_t ctl_mcst:1;
0435 uint64_t ctl_smac:1;
0436 uint64_t pre_free:1;
0437 uint64_t vlan_len:1;
0438 uint64_t pad_len:1;
0439 uint64_t pre_align:1;
0440 uint64_t null_dis:1;
0441 uint64_t reserved_11_11:1;
0442 uint64_t ptp_mode:1;
0443 uint64_t reserved_13_63:51;
0444 } s;
0445 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
0446 uint64_t pre_chk:1;
0447 uint64_t pre_strp:1;
0448 uint64_t ctl_drp:1;
0449 uint64_t ctl_bck:1;
0450 uint64_t ctl_mcst:1;
0451 uint64_t ctl_smac:1;
0452 uint64_t pre_free:1;
0453 uint64_t vlan_len:1;
0454 uint64_t pad_len:1;
0455 uint64_t reserved_9_63:55;
0456 } cn30xx;
0457 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
0458 uint64_t pre_chk:1;
0459 uint64_t pre_strp:1;
0460 uint64_t ctl_drp:1;
0461 uint64_t ctl_bck:1;
0462 uint64_t ctl_mcst:1;
0463 uint64_t ctl_smac:1;
0464 uint64_t pre_free:1;
0465 uint64_t vlan_len:1;
0466 uint64_t reserved_8_63:56;
0467 } cn31xx;
0468 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
0469 uint64_t pre_chk:1;
0470 uint64_t pre_strp:1;
0471 uint64_t ctl_drp:1;
0472 uint64_t ctl_bck:1;
0473 uint64_t ctl_mcst:1;
0474 uint64_t ctl_smac:1;
0475 uint64_t pre_free:1;
0476 uint64_t reserved_7_8:2;
0477 uint64_t pre_align:1;
0478 uint64_t null_dis:1;
0479 uint64_t reserved_11_63:53;
0480 } cn50xx;
0481 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
0482 uint64_t pre_chk:1;
0483 uint64_t pre_strp:1;
0484 uint64_t ctl_drp:1;
0485 uint64_t ctl_bck:1;
0486 uint64_t ctl_mcst:1;
0487 uint64_t ctl_smac:1;
0488 uint64_t pre_free:1;
0489 uint64_t reserved_7_8:2;
0490 uint64_t pre_align:1;
0491 uint64_t reserved_10_63:54;
0492 } cn56xxp1;
0493 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
0494 uint64_t pre_chk:1;
0495 uint64_t pre_strp:1;
0496 uint64_t ctl_drp:1;
0497 uint64_t ctl_bck:1;
0498 uint64_t ctl_mcst:1;
0499 uint64_t ctl_smac:1;
0500 uint64_t pre_free:1;
0501 uint64_t vlan_len:1;
0502 uint64_t pad_len:1;
0503 uint64_t pre_align:1;
0504 uint64_t null_dis:1;
0505 uint64_t reserved_11_63:53;
0506 } cn58xx;
0507 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
0508 uint64_t pre_chk:1;
0509 uint64_t pre_strp:1;
0510 uint64_t ctl_drp:1;
0511 uint64_t ctl_bck:1;
0512 uint64_t ctl_mcst:1;
0513 uint64_t ctl_smac:1;
0514 uint64_t pre_free:1;
0515 uint64_t reserved_7_8:2;
0516 uint64_t pre_align:1;
0517 uint64_t null_dis:1;
0518 uint64_t reserved_11_11:1;
0519 uint64_t ptp_mode:1;
0520 uint64_t reserved_13_63:51;
0521 } cn61xx;
0522 };
0523
0524 union cvmx_gmxx_rxx_int_reg {
0525 uint64_t u64;
0526 struct cvmx_gmxx_rxx_int_reg_s {
0527 uint64_t minerr:1;
0528 uint64_t carext:1;
0529 uint64_t maxerr:1;
0530 uint64_t jabber:1;
0531 uint64_t fcserr:1;
0532 uint64_t alnerr:1;
0533 uint64_t lenerr:1;
0534 uint64_t rcverr:1;
0535 uint64_t skperr:1;
0536 uint64_t niberr:1;
0537 uint64_t ovrerr:1;
0538 uint64_t pcterr:1;
0539 uint64_t rsverr:1;
0540 uint64_t falerr:1;
0541 uint64_t coldet:1;
0542 uint64_t ifgerr:1;
0543 uint64_t phy_link:1;
0544 uint64_t phy_spd:1;
0545 uint64_t phy_dupx:1;
0546 uint64_t pause_drp:1;
0547 uint64_t loc_fault:1;
0548 uint64_t rem_fault:1;
0549 uint64_t bad_seq:1;
0550 uint64_t bad_term:1;
0551 uint64_t unsop:1;
0552 uint64_t uneop:1;
0553 uint64_t undat:1;
0554 uint64_t hg2fld:1;
0555 uint64_t hg2cc:1;
0556 uint64_t reserved_29_63:35;
0557 } s;
0558 struct cvmx_gmxx_rxx_int_reg_cn30xx {
0559 uint64_t minerr:1;
0560 uint64_t carext:1;
0561 uint64_t maxerr:1;
0562 uint64_t jabber:1;
0563 uint64_t fcserr:1;
0564 uint64_t alnerr:1;
0565 uint64_t lenerr:1;
0566 uint64_t rcverr:1;
0567 uint64_t skperr:1;
0568 uint64_t niberr:1;
0569 uint64_t ovrerr:1;
0570 uint64_t pcterr:1;
0571 uint64_t rsverr:1;
0572 uint64_t falerr:1;
0573 uint64_t coldet:1;
0574 uint64_t ifgerr:1;
0575 uint64_t phy_link:1;
0576 uint64_t phy_spd:1;
0577 uint64_t phy_dupx:1;
0578 uint64_t reserved_19_63:45;
0579 } cn30xx;
0580 struct cvmx_gmxx_rxx_int_reg_cn50xx {
0581 uint64_t reserved_0_0:1;
0582 uint64_t carext:1;
0583 uint64_t reserved_2_2:1;
0584 uint64_t jabber:1;
0585 uint64_t fcserr:1;
0586 uint64_t alnerr:1;
0587 uint64_t reserved_6_6:1;
0588 uint64_t rcverr:1;
0589 uint64_t skperr:1;
0590 uint64_t niberr:1;
0591 uint64_t ovrerr:1;
0592 uint64_t pcterr:1;
0593 uint64_t rsverr:1;
0594 uint64_t falerr:1;
0595 uint64_t coldet:1;
0596 uint64_t ifgerr:1;
0597 uint64_t phy_link:1;
0598 uint64_t phy_spd:1;
0599 uint64_t phy_dupx:1;
0600 uint64_t pause_drp:1;
0601 uint64_t reserved_20_63:44;
0602 } cn50xx;
0603 struct cvmx_gmxx_rxx_int_reg_cn52xx {
0604 uint64_t reserved_0_0:1;
0605 uint64_t carext:1;
0606 uint64_t reserved_2_2:1;
0607 uint64_t jabber:1;
0608 uint64_t fcserr:1;
0609 uint64_t reserved_5_6:2;
0610 uint64_t rcverr:1;
0611 uint64_t skperr:1;
0612 uint64_t reserved_9_9:1;
0613 uint64_t ovrerr:1;
0614 uint64_t pcterr:1;
0615 uint64_t rsverr:1;
0616 uint64_t falerr:1;
0617 uint64_t coldet:1;
0618 uint64_t ifgerr:1;
0619 uint64_t reserved_16_18:3;
0620 uint64_t pause_drp:1;
0621 uint64_t loc_fault:1;
0622 uint64_t rem_fault:1;
0623 uint64_t bad_seq:1;
0624 uint64_t bad_term:1;
0625 uint64_t unsop:1;
0626 uint64_t uneop:1;
0627 uint64_t undat:1;
0628 uint64_t hg2fld:1;
0629 uint64_t hg2cc:1;
0630 uint64_t reserved_29_63:35;
0631 } cn52xx;
0632 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
0633 uint64_t reserved_0_0:1;
0634 uint64_t carext:1;
0635 uint64_t reserved_2_2:1;
0636 uint64_t jabber:1;
0637 uint64_t fcserr:1;
0638 uint64_t reserved_5_6:2;
0639 uint64_t rcverr:1;
0640 uint64_t skperr:1;
0641 uint64_t reserved_9_9:1;
0642 uint64_t ovrerr:1;
0643 uint64_t pcterr:1;
0644 uint64_t rsverr:1;
0645 uint64_t falerr:1;
0646 uint64_t coldet:1;
0647 uint64_t ifgerr:1;
0648 uint64_t reserved_16_18:3;
0649 uint64_t pause_drp:1;
0650 uint64_t loc_fault:1;
0651 uint64_t rem_fault:1;
0652 uint64_t bad_seq:1;
0653 uint64_t bad_term:1;
0654 uint64_t unsop:1;
0655 uint64_t uneop:1;
0656 uint64_t undat:1;
0657 uint64_t reserved_27_63:37;
0658 } cn56xxp1;
0659 struct cvmx_gmxx_rxx_int_reg_cn58xx {
0660 uint64_t minerr:1;
0661 uint64_t carext:1;
0662 uint64_t maxerr:1;
0663 uint64_t jabber:1;
0664 uint64_t fcserr:1;
0665 uint64_t alnerr:1;
0666 uint64_t lenerr:1;
0667 uint64_t rcverr:1;
0668 uint64_t skperr:1;
0669 uint64_t niberr:1;
0670 uint64_t ovrerr:1;
0671 uint64_t pcterr:1;
0672 uint64_t rsverr:1;
0673 uint64_t falerr:1;
0674 uint64_t coldet:1;
0675 uint64_t ifgerr:1;
0676 uint64_t phy_link:1;
0677 uint64_t phy_spd:1;
0678 uint64_t phy_dupx:1;
0679 uint64_t pause_drp:1;
0680 uint64_t reserved_20_63:44;
0681 } cn58xx;
0682 struct cvmx_gmxx_rxx_int_reg_cn61xx {
0683 uint64_t minerr:1;
0684 uint64_t carext:1;
0685 uint64_t reserved_2_2:1;
0686 uint64_t jabber:1;
0687 uint64_t fcserr:1;
0688 uint64_t reserved_5_6:2;
0689 uint64_t rcverr:1;
0690 uint64_t skperr:1;
0691 uint64_t reserved_9_9:1;
0692 uint64_t ovrerr:1;
0693 uint64_t pcterr:1;
0694 uint64_t rsverr:1;
0695 uint64_t falerr:1;
0696 uint64_t coldet:1;
0697 uint64_t ifgerr:1;
0698 uint64_t reserved_16_18:3;
0699 uint64_t pause_drp:1;
0700 uint64_t loc_fault:1;
0701 uint64_t rem_fault:1;
0702 uint64_t bad_seq:1;
0703 uint64_t bad_term:1;
0704 uint64_t unsop:1;
0705 uint64_t uneop:1;
0706 uint64_t undat:1;
0707 uint64_t hg2fld:1;
0708 uint64_t hg2cc:1;
0709 uint64_t reserved_29_63:35;
0710 } cn61xx;
0711 };
0712
0713 union cvmx_gmxx_prtx_cfg {
0714 uint64_t u64;
0715 struct cvmx_gmxx_prtx_cfg_s {
0716 uint64_t reserved_22_63:42;
0717 uint64_t pknd:6;
0718 uint64_t reserved_14_15:2;
0719 uint64_t tx_idle:1;
0720 uint64_t rx_idle:1;
0721 uint64_t reserved_9_11:3;
0722 uint64_t speed_msb:1;
0723 uint64_t reserved_4_7:4;
0724 uint64_t slottime:1;
0725 uint64_t duplex:1;
0726 uint64_t speed:1;
0727 uint64_t en:1;
0728 } s;
0729 struct cvmx_gmxx_prtx_cfg_cn30xx {
0730 uint64_t reserved_4_63:60;
0731 uint64_t slottime:1;
0732 uint64_t duplex:1;
0733 uint64_t speed:1;
0734 uint64_t en:1;
0735 } cn30xx;
0736 struct cvmx_gmxx_prtx_cfg_cn52xx {
0737 uint64_t reserved_14_63:50;
0738 uint64_t tx_idle:1;
0739 uint64_t rx_idle:1;
0740 uint64_t reserved_9_11:3;
0741 uint64_t speed_msb:1;
0742 uint64_t reserved_4_7:4;
0743 uint64_t slottime:1;
0744 uint64_t duplex:1;
0745 uint64_t speed:1;
0746 uint64_t en:1;
0747 } cn52xx;
0748 };
0749
0750 union cvmx_gmxx_rxx_adr_ctl {
0751 uint64_t u64;
0752 struct cvmx_gmxx_rxx_adr_ctl_s {
0753 uint64_t reserved_4_63:60;
0754 uint64_t cam_mode:1;
0755 uint64_t mcst:2;
0756 uint64_t bcst:1;
0757 } s;
0758 };
0759
0760 union cvmx_pip_prt_tagx {
0761 uint64_t u64;
0762 struct cvmx_pip_prt_tagx_s {
0763 uint64_t reserved_54_63:10;
0764 uint64_t portadd_en:1;
0765 uint64_t inc_hwchk:1;
0766 uint64_t reserved_50_51:2;
0767 uint64_t grptagbase_msb:2;
0768 uint64_t reserved_46_47:2;
0769 uint64_t grptagmask_msb:2;
0770 uint64_t reserved_42_43:2;
0771 uint64_t grp_msb:2;
0772 uint64_t grptagbase:4;
0773 uint64_t grptagmask:4;
0774 uint64_t grptag:1;
0775 uint64_t grptag_mskip:1;
0776 uint64_t tag_mode:2;
0777 uint64_t inc_vs:2;
0778 uint64_t inc_vlan:1;
0779 uint64_t inc_prt_flag:1;
0780 uint64_t ip6_dprt_flag:1;
0781 uint64_t ip4_dprt_flag:1;
0782 uint64_t ip6_sprt_flag:1;
0783 uint64_t ip4_sprt_flag:1;
0784 uint64_t ip6_nxth_flag:1;
0785 uint64_t ip4_pctl_flag:1;
0786 uint64_t ip6_dst_flag:1;
0787 uint64_t ip4_dst_flag:1;
0788 uint64_t ip6_src_flag:1;
0789 uint64_t ip4_src_flag:1;
0790 uint64_t tcp6_tag_type:2;
0791 uint64_t tcp4_tag_type:2;
0792 uint64_t ip6_tag_type:2;
0793 uint64_t ip4_tag_type:2;
0794 uint64_t non_tag_type:2;
0795 uint64_t grp:4;
0796 } s;
0797 struct cvmx_pip_prt_tagx_cn30xx {
0798 uint64_t reserved_40_63:24;
0799 uint64_t grptagbase:4;
0800 uint64_t grptagmask:4;
0801 uint64_t grptag:1;
0802 uint64_t reserved_30_30:1;
0803 uint64_t tag_mode:2;
0804 uint64_t inc_vs:2;
0805 uint64_t inc_vlan:1;
0806 uint64_t inc_prt_flag:1;
0807 uint64_t ip6_dprt_flag:1;
0808 uint64_t ip4_dprt_flag:1;
0809 uint64_t ip6_sprt_flag:1;
0810 uint64_t ip4_sprt_flag:1;
0811 uint64_t ip6_nxth_flag:1;
0812 uint64_t ip4_pctl_flag:1;
0813 uint64_t ip6_dst_flag:1;
0814 uint64_t ip4_dst_flag:1;
0815 uint64_t ip6_src_flag:1;
0816 uint64_t ip4_src_flag:1;
0817 uint64_t tcp6_tag_type:2;
0818 uint64_t tcp4_tag_type:2;
0819 uint64_t ip6_tag_type:2;
0820 uint64_t ip4_tag_type:2;
0821 uint64_t non_tag_type:2;
0822 uint64_t grp:4;
0823 } cn30xx;
0824 struct cvmx_pip_prt_tagx_cn50xx {
0825 uint64_t reserved_40_63:24;
0826 uint64_t grptagbase:4;
0827 uint64_t grptagmask:4;
0828 uint64_t grptag:1;
0829 uint64_t grptag_mskip:1;
0830 uint64_t tag_mode:2;
0831 uint64_t inc_vs:2;
0832 uint64_t inc_vlan:1;
0833 uint64_t inc_prt_flag:1;
0834 uint64_t ip6_dprt_flag:1;
0835 uint64_t ip4_dprt_flag:1;
0836 uint64_t ip6_sprt_flag:1;
0837 uint64_t ip4_sprt_flag:1;
0838 uint64_t ip6_nxth_flag:1;
0839 uint64_t ip4_pctl_flag:1;
0840 uint64_t ip6_dst_flag:1;
0841 uint64_t ip4_dst_flag:1;
0842 uint64_t ip6_src_flag:1;
0843 uint64_t ip4_src_flag:1;
0844 uint64_t tcp6_tag_type:2;
0845 uint64_t tcp4_tag_type:2;
0846 uint64_t ip6_tag_type:2;
0847 uint64_t ip4_tag_type:2;
0848 uint64_t non_tag_type:2;
0849 uint64_t grp:4;
0850 } cn50xx;
0851 };
0852
0853 union cvmx_spxx_int_reg {
0854 uint64_t u64;
0855 struct cvmx_spxx_int_reg_s {
0856 uint64_t reserved_32_63:32;
0857 uint64_t spf:1;
0858 uint64_t reserved_12_30:19;
0859 uint64_t calerr:1;
0860 uint64_t syncerr:1;
0861 uint64_t diperr:1;
0862 uint64_t tpaovr:1;
0863 uint64_t rsverr:1;
0864 uint64_t drwnng:1;
0865 uint64_t clserr:1;
0866 uint64_t spiovr:1;
0867 uint64_t reserved_2_3:2;
0868 uint64_t abnorm:1;
0869 uint64_t prtnxa:1;
0870 } s;
0871 };
0872
0873 union cvmx_spxx_int_msk {
0874 uint64_t u64;
0875 struct cvmx_spxx_int_msk_s {
0876 uint64_t reserved_12_63:52;
0877 uint64_t calerr:1;
0878 uint64_t syncerr:1;
0879 uint64_t diperr:1;
0880 uint64_t tpaovr:1;
0881 uint64_t rsverr:1;
0882 uint64_t drwnng:1;
0883 uint64_t clserr:1;
0884 uint64_t spiovr:1;
0885 uint64_t reserved_2_3:2;
0886 uint64_t abnorm:1;
0887 uint64_t prtnxa:1;
0888 } s;
0889 };
0890
0891 union cvmx_pow_wq_int {
0892 uint64_t u64;
0893 struct cvmx_pow_wq_int_s {
0894 uint64_t wq_int:16;
0895 uint64_t iq_dis:16;
0896 uint64_t reserved_32_63:32;
0897 } s;
0898 };
0899
0900 union cvmx_sso_wq_int_thrx {
0901 uint64_t u64;
0902 struct {
0903 uint64_t iq_thr:12;
0904 uint64_t reserved_12_13:2;
0905 uint64_t ds_thr:12;
0906 uint64_t reserved_26_27:2;
0907 uint64_t tc_thr:4;
0908 uint64_t tc_en:1;
0909 uint64_t reserved_33_63:31;
0910 } s;
0911 };
0912
0913 union cvmx_stxx_int_reg {
0914 uint64_t u64;
0915 struct cvmx_stxx_int_reg_s {
0916 uint64_t reserved_9_63:55;
0917 uint64_t syncerr:1;
0918 uint64_t frmerr:1;
0919 uint64_t unxfrm:1;
0920 uint64_t nosync:1;
0921 uint64_t diperr:1;
0922 uint64_t datovr:1;
0923 uint64_t ovrbst:1;
0924 uint64_t calpar1:1;
0925 uint64_t calpar0:1;
0926 } s;
0927 };
0928
0929 union cvmx_stxx_int_msk {
0930 uint64_t u64;
0931 struct cvmx_stxx_int_msk_s {
0932 uint64_t reserved_8_63:56;
0933 uint64_t frmerr:1;
0934 uint64_t unxfrm:1;
0935 uint64_t nosync:1;
0936 uint64_t diperr:1;
0937 uint64_t datovr:1;
0938 uint64_t ovrbst:1;
0939 uint64_t calpar1:1;
0940 uint64_t calpar0:1;
0941 } s;
0942 };
0943
0944 union cvmx_pow_wq_int_pc {
0945 uint64_t u64;
0946 struct cvmx_pow_wq_int_pc_s {
0947 uint64_t reserved_0_7:8;
0948 uint64_t pc_thr:20;
0949 uint64_t reserved_28_31:4;
0950 uint64_t pc:28;
0951 uint64_t reserved_60_63:4;
0952 } s;
0953 };
0954
0955 union cvmx_pow_wq_int_thrx {
0956 uint64_t u64;
0957 struct cvmx_pow_wq_int_thrx_s {
0958 uint64_t reserved_29_63:35;
0959 uint64_t tc_en:1;
0960 uint64_t tc_thr:4;
0961 uint64_t reserved_23_23:1;
0962 uint64_t ds_thr:11;
0963 uint64_t reserved_11_11:1;
0964 uint64_t iq_thr:11;
0965 } s;
0966 struct cvmx_pow_wq_int_thrx_cn30xx {
0967 uint64_t reserved_29_63:35;
0968 uint64_t tc_en:1;
0969 uint64_t tc_thr:4;
0970 uint64_t reserved_18_23:6;
0971 uint64_t ds_thr:6;
0972 uint64_t reserved_6_11:6;
0973 uint64_t iq_thr:6;
0974 } cn30xx;
0975 struct cvmx_pow_wq_int_thrx_cn31xx {
0976 uint64_t reserved_29_63:35;
0977 uint64_t tc_en:1;
0978 uint64_t tc_thr:4;
0979 uint64_t reserved_20_23:4;
0980 uint64_t ds_thr:8;
0981 uint64_t reserved_8_11:4;
0982 uint64_t iq_thr:8;
0983 } cn31xx;
0984 struct cvmx_pow_wq_int_thrx_cn52xx {
0985 uint64_t reserved_29_63:35;
0986 uint64_t tc_en:1;
0987 uint64_t tc_thr:4;
0988 uint64_t reserved_21_23:3;
0989 uint64_t ds_thr:9;
0990 uint64_t reserved_9_11:3;
0991 uint64_t iq_thr:9;
0992 } cn52xx;
0993 struct cvmx_pow_wq_int_thrx_cn63xx {
0994 uint64_t reserved_29_63:35;
0995 uint64_t tc_en:1;
0996 uint64_t tc_thr:4;
0997 uint64_t reserved_22_23:2;
0998 uint64_t ds_thr:10;
0999 uint64_t reserved_10_11:2;
1000 uint64_t iq_thr:10;
1001 } cn63xx;
1002 };
1003
1004 union cvmx_npi_rsl_int_blocks {
1005 uint64_t u64;
1006 struct cvmx_npi_rsl_int_blocks_s {
1007 uint64_t reserved_32_63:32;
1008 uint64_t rint_31:1;
1009 uint64_t iob:1;
1010 uint64_t reserved_28_29:2;
1011 uint64_t rint_27:1;
1012 uint64_t rint_26:1;
1013 uint64_t rint_25:1;
1014 uint64_t rint_24:1;
1015 uint64_t asx1:1;
1016 uint64_t asx0:1;
1017 uint64_t rint_21:1;
1018 uint64_t pip:1;
1019 uint64_t spx1:1;
1020 uint64_t spx0:1;
1021 uint64_t lmc:1;
1022 uint64_t l2c:1;
1023 uint64_t rint_15:1;
1024 uint64_t reserved_13_14:2;
1025 uint64_t pow:1;
1026 uint64_t tim:1;
1027 uint64_t pko:1;
1028 uint64_t ipd:1;
1029 uint64_t rint_8:1;
1030 uint64_t zip:1;
1031 uint64_t dfa:1;
1032 uint64_t fpa:1;
1033 uint64_t key:1;
1034 uint64_t npi:1;
1035 uint64_t gmx1:1;
1036 uint64_t gmx0:1;
1037 uint64_t mio:1;
1038 } s;
1039 struct cvmx_npi_rsl_int_blocks_cn30xx {
1040 uint64_t reserved_32_63:32;
1041 uint64_t rint_31:1;
1042 uint64_t iob:1;
1043 uint64_t rint_29:1;
1044 uint64_t rint_28:1;
1045 uint64_t rint_27:1;
1046 uint64_t rint_26:1;
1047 uint64_t rint_25:1;
1048 uint64_t rint_24:1;
1049 uint64_t asx1:1;
1050 uint64_t asx0:1;
1051 uint64_t rint_21:1;
1052 uint64_t pip:1;
1053 uint64_t spx1:1;
1054 uint64_t spx0:1;
1055 uint64_t lmc:1;
1056 uint64_t l2c:1;
1057 uint64_t rint_15:1;
1058 uint64_t rint_14:1;
1059 uint64_t usb:1;
1060 uint64_t pow:1;
1061 uint64_t tim:1;
1062 uint64_t pko:1;
1063 uint64_t ipd:1;
1064 uint64_t rint_8:1;
1065 uint64_t zip:1;
1066 uint64_t dfa:1;
1067 uint64_t fpa:1;
1068 uint64_t key:1;
1069 uint64_t npi:1;
1070 uint64_t gmx1:1;
1071 uint64_t gmx0:1;
1072 uint64_t mio:1;
1073 } cn30xx;
1074 struct cvmx_npi_rsl_int_blocks_cn38xx {
1075 uint64_t reserved_32_63:32;
1076 uint64_t rint_31:1;
1077 uint64_t iob:1;
1078 uint64_t rint_29:1;
1079 uint64_t rint_28:1;
1080 uint64_t rint_27:1;
1081 uint64_t rint_26:1;
1082 uint64_t rint_25:1;
1083 uint64_t rint_24:1;
1084 uint64_t asx1:1;
1085 uint64_t asx0:1;
1086 uint64_t rint_21:1;
1087 uint64_t pip:1;
1088 uint64_t spx1:1;
1089 uint64_t spx0:1;
1090 uint64_t lmc:1;
1091 uint64_t l2c:1;
1092 uint64_t rint_15:1;
1093 uint64_t rint_14:1;
1094 uint64_t rint_13:1;
1095 uint64_t pow:1;
1096 uint64_t tim:1;
1097 uint64_t pko:1;
1098 uint64_t ipd:1;
1099 uint64_t rint_8:1;
1100 uint64_t zip:1;
1101 uint64_t dfa:1;
1102 uint64_t fpa:1;
1103 uint64_t key:1;
1104 uint64_t npi:1;
1105 uint64_t gmx1:1;
1106 uint64_t gmx0:1;
1107 uint64_t mio:1;
1108 } cn38xx;
1109 struct cvmx_npi_rsl_int_blocks_cn50xx {
1110 uint64_t reserved_31_63:33;
1111 uint64_t iob:1;
1112 uint64_t lmc1:1;
1113 uint64_t agl:1;
1114 uint64_t reserved_24_27:4;
1115 uint64_t asx1:1;
1116 uint64_t asx0:1;
1117 uint64_t reserved_21_21:1;
1118 uint64_t pip:1;
1119 uint64_t spx1:1;
1120 uint64_t spx0:1;
1121 uint64_t lmc:1;
1122 uint64_t l2c:1;
1123 uint64_t reserved_15_15:1;
1124 uint64_t rad:1;
1125 uint64_t usb:1;
1126 uint64_t pow:1;
1127 uint64_t tim:1;
1128 uint64_t pko:1;
1129 uint64_t ipd:1;
1130 uint64_t reserved_8_8:1;
1131 uint64_t zip:1;
1132 uint64_t dfa:1;
1133 uint64_t fpa:1;
1134 uint64_t key:1;
1135 uint64_t npi:1;
1136 uint64_t gmx1:1;
1137 uint64_t gmx0:1;
1138 uint64_t mio:1;
1139 } cn50xx;
1140 };
1141
1142 union cvmx_pko_command_word0 {
1143 uint64_t u64;
1144 struct {
1145 uint64_t total_bytes:16;
1146 uint64_t segs:6;
1147 uint64_t dontfree:1;
1148 uint64_t ignore_i:1;
1149 uint64_t ipoffp1:7;
1150 uint64_t gather:1;
1151 uint64_t rsp:1;
1152 uint64_t wqp:1;
1153 uint64_t n2:1;
1154 uint64_t le:1;
1155 uint64_t reg0:11;
1156 uint64_t subone0:1;
1157 uint64_t reg1:11;
1158 uint64_t subone1:1;
1159 uint64_t size0:2;
1160 uint64_t size1:2;
1161 } s;
1162 };
1163
1164 union cvmx_ciu_timx {
1165 uint64_t u64;
1166 struct cvmx_ciu_timx_s {
1167 uint64_t reserved_37_63:27;
1168 uint64_t one_shot:1;
1169 uint64_t len:36;
1170 } s;
1171 };
1172
1173 union cvmx_gmxx_rxx_rx_inbnd {
1174 uint64_t u64;
1175 struct cvmx_gmxx_rxx_rx_inbnd_s {
1176 uint64_t status:1;
1177 uint64_t speed:2;
1178 uint64_t duplex:1;
1179 uint64_t reserved_4_63:60;
1180 } s;
1181 };
1182
1183 static inline int32_t cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg,
1184 int32_t value)
1185 {
1186 return value;
1187 }
1188
1189 static inline void cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg,
1190 int32_t value)
1191 { }
1192
1193 static inline void cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg,
1194 int32_t value)
1195 { }
1196
1197 static inline uint64_t cvmx_scratch_read64(uint64_t address)
1198 {
1199 return 0;
1200 }
1201
1202 static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
1203 { }
1204
1205 static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
1206 {
1207 return 0;
1208 }
1209
1210 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
1211 {
1212 return (void *)(uintptr_t)(physical_address);
1213 }
1214
1215 static inline uint64_t cvmx_ptr_to_phys(void *ptr)
1216 {
1217 return (unsigned long)ptr;
1218 }
1219
1220 static inline int cvmx_helper_get_interface_num(int ipd_port)
1221 {
1222 return ipd_port;
1223 }
1224
1225 static inline int cvmx_helper_get_interface_index_num(int ipd_port)
1226 {
1227 return ipd_port;
1228 }
1229
1230 static inline void cvmx_fpa_enable(void)
1231 { }
1232
1233 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
1234 {
1235 return 0;
1236 }
1237
1238 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
1239 { }
1240
1241 static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1242 {
1243 return 0;
1244 }
1245
1246 static inline void *cvmx_fpa_alloc(uint64_t pool)
1247 {
1248 return NULL;
1249 }
1250
1251 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
1252 uint64_t num_cache_lines)
1253 { }
1254
1255 static inline int octeon_is_simulation(void)
1256 {
1257 return 1;
1258 }
1259
1260 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
1261 cvmx_pip_port_status_t *status)
1262 { }
1263
1264 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
1265 cvmx_pko_port_status_t *status)
1266 { }
1267
1268 static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
1269 interface)
1270 {
1271 return 0;
1272 }
1273
1274 static inline union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port)
1275 {
1276 union cvmx_helper_link_info ret = { .u64 = 0 };
1277
1278 return ret;
1279 }
1280
1281 static inline int cvmx_helper_link_set(int ipd_port,
1282 union cvmx_helper_link_info link_info)
1283 {
1284 return 0;
1285 }
1286
1287 static inline int cvmx_helper_initialize_packet_io_global(void)
1288 {
1289 return 0;
1290 }
1291
1292 static inline int cvmx_helper_get_number_of_interfaces(void)
1293 {
1294 return 2;
1295 }
1296
1297 static inline int cvmx_helper_ports_on_interface(int interface)
1298 {
1299 return 1;
1300 }
1301
1302 static inline int cvmx_helper_get_ipd_port(int interface, int port)
1303 {
1304 return 0;
1305 }
1306
1307 static inline int cvmx_helper_ipd_and_packet_input_enable(void)
1308 {
1309 return 0;
1310 }
1311
1312 static inline void cvmx_ipd_disable(void)
1313 { }
1314
1315 static inline void cvmx_ipd_free_ptr(void)
1316 { }
1317
1318 static inline void cvmx_pko_disable(void)
1319 { }
1320
1321 static inline void cvmx_pko_shutdown(void)
1322 { }
1323
1324 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
1325 {
1326 return port;
1327 }
1328
1329 static inline int cvmx_pko_get_base_queue(int port)
1330 {
1331 return port;
1332 }
1333
1334 static inline int cvmx_pko_get_num_queues(int port)
1335 {
1336 return port;
1337 }
1338
1339 static inline unsigned int cvmx_get_core_num(void)
1340 {
1341 return 0;
1342 }
1343
1344 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1345 cvmx_pow_wait_t wait)
1346 { }
1347
1348 static inline void cvmx_pow_work_request_async(int scr_addr,
1349 cvmx_pow_wait_t wait)
1350 { }
1351
1352 static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
1353 {
1354 struct cvmx_wqe *wqe = (void *)(unsigned long)scr_addr;
1355
1356 return wqe;
1357 }
1358
1359 static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1360 {
1361 return (void *)(unsigned long)wait;
1362 }
1363
1364 static inline int cvmx_spi_restart_interface(int interface,
1365 cvmx_spi_mode_t mode, int timeout)
1366 {
1367 return 0;
1368 }
1369
1370 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
1371 enum cvmx_fau_reg_32 reg,
1372 int32_t value)
1373 { }
1374
1375 static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
1376 int interface,
1377 int port)
1378 {
1379 union cvmx_gmxx_rxx_rx_inbnd r;
1380
1381 r.u64 = 0;
1382 return r;
1383 }
1384
1385 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
1386 cvmx_pko_lock_t use_locking)
1387 { }
1388
1389 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port,
1390 uint64_t queue, union cvmx_pko_command_word0 pko_command,
1391 union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking)
1392 {
1393 return 0;
1394 }
1395
1396 static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
1397 { }
1398
1399 static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
1400 { }
1401
1402 static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
1403 {
1404 return 0;
1405 }
1406
1407 static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
1408 { }
1409
1410 static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag,
1411 enum cvmx_pow_tag_type tag_type,
1412 uint64_t qos, uint64_t grp)
1413 { }
1414
1415 #define CVMX_ASXX_RX_CLK_SETX(a, b) ((a) + (b))
1416 #define CVMX_ASXX_TX_CLK_SETX(a, b) ((a) + (b))
1417 #define CVMX_CIU_TIMX(a) (a)
1418 #define CVMX_GMXX_RXX_ADR_CAM0(a, b) ((a) + (b))
1419 #define CVMX_GMXX_RXX_ADR_CAM1(a, b) ((a) + (b))
1420 #define CVMX_GMXX_RXX_ADR_CAM2(a, b) ((a) + (b))
1421 #define CVMX_GMXX_RXX_ADR_CAM3(a, b) ((a) + (b))
1422 #define CVMX_GMXX_RXX_ADR_CAM4(a, b) ((a) + (b))
1423 #define CVMX_GMXX_RXX_ADR_CAM5(a, b) ((a) + (b))
1424 #define CVMX_GMXX_RXX_FRM_CTL(a, b) ((a) + (b))
1425 #define CVMX_GMXX_RXX_INT_REG(a, b) ((a) + (b))
1426 #define CVMX_GMXX_SMACX(a, b) ((a) + (b))
1427 #define CVMX_PIP_PRT_TAGX(a) (a)
1428 #define CVMX_POW_PP_GRP_MSKX(a) (a)
1429 #define CVMX_POW_WQ_INT_THRX(a) (a)
1430 #define CVMX_SPXX_INT_MSK(a) (a)
1431 #define CVMX_SPXX_INT_REG(a) (a)
1432 #define CVMX_SSO_PPX_GRP_MSK(a) (a)
1433 #define CVMX_SSO_WQ_INT_THRX(a) (a)
1434 #define CVMX_STXX_INT_MSK(a) (a)
1435 #define CVMX_STXX_INT_REG(a) (a)
